llvm.org GIT mirror llvm / 8dd37f7
Add cdp/cdp2 instructions for thumb/thumb2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 9 years ago
5 changed file(s) with 57 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
13771377 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
13781378
13791379 //===----------------------------------------------------------------------===//
1380 // Other Coprocessor Instructions. For disassembly only.
1381 //
1382 def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1383 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1384 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1385 [/* For disassembly only; pattern left blank */]> {
1386 let Inst{27-24} = 0b1110;
1387
1388 bits<4> opc1;
1389 bits<4> CRn;
1390 bits<4> CRd;
1391 bits<4> cop;
1392 bits<3> opc2;
1393 bits<4> CRm;
1394
1395 let Inst{3-0} = CRm;
1396 let Inst{4} = 0;
1397 let Inst{7-5} = opc2;
1398 let Inst{11-8} = cop;
1399 let Inst{15-12} = CRd;
1400 let Inst{19-16} = CRn;
1401 let Inst{23-20} = opc1;
1402 }
1403
1404 //===----------------------------------------------------------------------===//
13801405 // TLS Instructions
13811406 //
13821407
33773377 def t2MCRR : t2MovRRCopro<"mcrr2",0/* from ARM core register to coprocessor */>;
33783378 def t2MRRC : t2MovRRCopro<"mrrc2",1/* from coprocessor to ARM core register */>;
33793379
3380 //===----------------------------------------------------------------------===//
3381 // Other Coprocessor Instructions. For disassembly only.
3382 //
3383
3384 def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3385 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3386 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3387 [/* For disassembly only; pattern left blank */]> {
3388 let Inst{27-24} = 0b1110;
3389
3390 bits<4> opc1;
3391 bits<4> CRn;
3392 bits<4> CRd;
3393 bits<4> cop;
3394 bits<3> opc2;
3395 bits<4> CRm;
3396
3397 let Inst{3-0} = CRm;
3398 let Inst{4} = 0;
3399 let Inst{7-5} = opc2;
3400 let Inst{11-8} = cop;
3401 let Inst{15-12} = CRd;
3402 let Inst{19-16} = CRn;
3403 let Inst{23-20} = opc1;
3404 }
12011201
12021202 if (isThumb)
12031203 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
1204 Mnemonic == "mrc" || Mnemonic == "mrrc")
1204 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
12051205 CanAcceptPredicationCode = false;
12061206 }
12071207
5050 @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57]
5151 mrrc p7, #1, r5, r4, c1
5252
53 @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17]
54 cdp p7, #1, c1, c1, c1, #4
55
193193 @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]
194194 mrrc2 p7, #1, r5, r4, c1
195195
196 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17]
197 cdp2 p7, #1, c1, c1, c1, #4
198