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[PowerPC]Update Power VSX test cases to also test fast-isel Update of some of the VSX test cases for Power to check fast-isel codegen as well as the regular codegen. http://reviews.llvm.org/D6357 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223509 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Seurer 5 years ago
7 changed file(s) with 542 addition(s) and 132 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
1 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck %s
12 target datalayout = "E-m:e-i64:64-n32:64"
23 target triple = "powerpc64-unknown-linux-gnu"
34
0 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
1 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
12
23 ; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
34 ; live-interval-updating logic.
2122 ; CHECK-DAG: stxsdx 3, 0, 7
2223 ; CHECK-DAG: stxsdx 1, 7, [[C1]]
2324 ; CHECK: blr
25
26 ; CHECK-FISL-LABEL: @test1
27 ; CHECK-FISL-DAG: fmr 0, 1
28 ; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
29 ; CHECK-FISL-DAG: stxsdx 0, 0, 7
30 ; CHECK-FISL-DAG: xsmaddadp 1, 2, 4
31 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
32 ; CHECK-FISL-DAG: stxsdx 1, 7, [[C1]]
33 ; CHECK-FISL: blr
2434 }
2535
2636 define void @test2(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
4555 ; CHECK-DAG: stxsdx 4, 8, [[C1]]
4656 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
4757 ; CHECK: blr
58
59 ; CHECK-FISL-LABEL: @test2
60 ; CHECK-FISL-DAG: fmr 0, 1
61 ; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
62 ; CHECK-FISL-DAG: stxsdx 0, 0, 8
63 ; CHECK-FISL-DAG: fmr 0, 1
64 ; CHECK-FISL-DAG: xsmaddadp 0, 2, 4
65 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
66 ; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
67 ; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
68 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
69 ; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
70 ; CHECK-FISL: blr
4871 }
4972
5073 define void @test3(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
80103 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
81104 ; CHECK-DAG: stxsdx 4, 8, [[C3]]
82105 ; CHECK: blr
106
107 ; CHECK-FISL-LABEL: @test3
108 ; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
109 ; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
110 ; CHECK-FISL-DAG: fmr 4, [[F1]]
111 ; CHECK-FISL-DAG: xsmaddadp 4, 2, 3
112 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
113 ; CHECK-FISL-DAG: stxsdx 4, 8, [[C1]]
114 ; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
115 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
116 ; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
117 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
118 ; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
119 ; CHECK-FISL: blr
83120 }
84121
85122 define void @test4(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
115152 ; CHECK-DAG: stxsdx 4, 8, [[C3]]
116153 ; CHECK-DAG: stxsdx 1, 8, [[C2]]
117154 ; CHECK: blr
155
156 ; CHECK-FISL-LABEL: @test4
157 ; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
158 ; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 3
159 ; CHECK-FISL-DAG: stxsdx 0, 0, 8
160 ; CHECK-FISL-DAG: fmr [[F1]], 1
161 ; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
162 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
163 ; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
164 ; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
165 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
166 ; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
167 ; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
168 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
169 ; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
170 ; CHECK-FISL: blr
118171 }
119172
120173 declare double @llvm.fma.f64(double, double, double) #0
135188 ; CHECK-DAG: stxvd2x 36, 0, 3
136189 ; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
137190 ; CHECK: blr
191
192 ; CHECK-FISL-LABEL: @testv1
193 ; CHECK-FISL-DAG: xxlor 0, 34, 34
194 ; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
195 ; CHECK-FISL-DAG: stxvd2x 0, 0, 3
196 ; CHECK-FISL-DAG: xvmaddadp 34, 35, 37
197 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
198 ; CHECK-FISL-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
199 ; CHECK-FISL: blr
138200 }
139201
140202 define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
159221 ; CHECK-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]
160222 ; CHECK-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
161223 ; CHECK: blr
224
225 ; CHECK-FISL-LABEL: @testv2
226 ; CHECK-FISL-DAG: xxlor 0, 34, 34
227 ; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
228 ; CHECK-FISL-DAG: stxvd2x 0, 0, 3
229 ; CHECK-FISL-DAG: xxlor 0, 34, 34
230 ; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
231 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
232 ; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1:[0-9]+]]
233 ; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
234 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
235 ; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
236 ; CHECK-FISL: blr
162237 }
163238
164239 define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
200275 ; CHECK-DAG: stxvd2x 34, 3, [[C2]]
201276 ; CHECK-DAG: stxvd2x 37, 3, [[C3]]
202277 ; CHECK: blr
278
279 ; CHECK-FISL-LABEL: @testv3
280 ; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
281 ; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
282 ; CHECK-FISL-DAG: stxvd2x [[V1]], 0, 3
283 ; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
284 ; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
285 ; CHECK-FISL-DAG: xxlor [[V3:[0-9]+]], 0, 0
286 ; CHECK-FISL-DAG: xvmaddadp [[V3]], 35, 36
287 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 48
288 ; CHECK-FISL-DAG: stxvd2x [[V3]], 3, [[C1]]
289 ; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
290 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
291 ; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
292 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 16
293 ; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
294 ; CHECK-FISL: blr
203295 }
204296
205297 define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
235327 ; CHECK-DAG: stxvd2x 37, 3, [[C3]]
236328 ; CHECK-DAG: stxvd2x 34, 3, [[C2]]
237329 ; CHECK: blr
330
331 ; CHECK-FISL-LABEL: @testv4
332 ; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
333 ; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
334 ; CHECK-FISL-DAG: stxvd2x 0, 0, 3
335 ; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
336 ; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
337 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
338 ; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1]]
339 ; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
340 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 48
341 ; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
342 ; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
343 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
344 ; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
345 ; CHECK-FISL: blr
238346 }
239347
240348 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0
0 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64-unknown-linux-gnu < %s > %t
1 ; RUN: grep lxvw4x < %t | count 3
2 ; RUN: grep lxvd2x < %t | count 3
3 ; RUN: grep stxvw4x < %t | count 3
4 ; RUN: grep stxvd2x < %t | count 3
5 ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 -mtriple=powerpc64-unknown-linux-gnu < %s > %t
16 ; RUN: grep lxvw4x < %t | count 3
27 ; RUN: grep lxvd2x < %t | count 3
38 ; RUN: grep stxvw4x < %t | count 3
0 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s
2 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
14 target datalayout = "E-m:e-i64:64-n32:64"
25 target triple = "powerpc64-unknown-linux-gnu"
36
2528 %v = load <4 x float>* %a, align 8
2629 ret <4 x float> %v
2730
28 ; CHECK-LABEL: @test32u
29 ; CHECK: lxvw4x 34, 0, 3
30 ; CHECK: blr
31 ; CHECK-REG-LABEL: @test32u
32 ; CHECK-REG: lxvw4x 34, 0, 3
33 ; CHECK-REG: blr
34
35 ; CHECK-FISL-LABEL: @test32u
36 ; CHECK-FISL: lxvw4x 0, 0, 3
37 ; CHECK-FISL: xxlor 34, 0, 0
38 ; CHECK-FISL: blr
3139 }
3240
3341 define void @test33u(<4 x float>* %a, <4 x float> %b) {
3442 store <4 x float> %b, <4 x float>* %a, align 8
3543 ret void
3644
37 ; CHECK-LABEL: @test33u
38 ; CHECK: stxvw4x 34, 0, 3
39 ; CHECK: blr
45 ; CHECK-REG-LABEL: @test33u
46 ; CHECK-REG: stxvw4x 34, 0, 3
47 ; CHECK-REG: blr
48
49 ; CHECK-FISL-LABEL: @test33u
50 ; CHECK-FISL: vor 3, 2, 2
51 ; CHECK-FISL: stxvw4x 35, 0, 3
52 ; CHECK-FISL: blr
4053 }
4154
0 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
12 target datalayout = "E-m:e-i64:64-n32:64"
23 target triple = "powerpc64-unknown-linux-gnu"
34
0 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
2 ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
14 target datalayout = "E-m:e-i64:64-n32:64"
25 target triple = "powerpc64-unknown-linux-gnu"
36
69 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
710 br label %return
811
9 ; CHECK: @foo1
10 ; CHECK: xxlor [[R1:[0-9]+]], 1, 1
11 ; CHECK: xxlor 1, [[R1]], [[R1]]
12 ; CHECK: blr
12 ; CHECK-REG: @foo1
13 ; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1
14 ; CHECK-REG: xxlor 1, [[R1]], [[R1]]
15 ; CHECK-REG: blr
16
17 ; CHECK-FISL: @foo1
18 ; CHECK-FISL: lis 0, -1
19 ; CHECK-FISL: ori 0, 0, 65384
20 ; CHECK-FISL: stxsdx 1, 1, 0
21 ; CHECK-FISL: blr
1322
1423 return: ; preds = %entry
1524 ret double %a
2130 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
2231 br label %return
2332
24 ; CHECK: @foo2
25 ; CHECK: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
26 ; CHECK: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
27 ; CHECK: blr
33 ; CHECK-REG: @foo2
34 ; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
35 ; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
36 ; CHECK-REG: blr
37
38 ; CHECK-FISL: @foo2
39 ; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1
40 ; CHECK-FISL: stxsdx [[R1]], [[R1]], 0
41 ; CHECK-FISL: lxsdx [[R1]], [[R1]], 0
42 ; CHECK-FISL: blr
2843
2944 return: ; preds = %entry
3045 ret double %b
0 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
1 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
2 ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
14 target datalayout = "E-m:e-i64:64-n32:64"
25 target triple = "powerpc64-unknown-linux-gnu"
36
4649 %v = xor <4 x i32> %a, %b
4750 ret <4 x i32> %v
4851
49 ; CHECK-LABEL: @test5
50 ; CHECK: xxlxor 34, 34, 35
51 ; CHECK: blr
52 ; CHECK-REG-LABEL: @test5
53 ; CHECK-REG: xxlxor 34, 34, 35
54 ; CHECK-REG: blr
55
56 ; CHECK-FISL-LABEL: @test5
57 ; CHECK-FISL: vor 4, 2, 2
58 ; CHECK-FISL: vor 5, 3, 3
59 ; CHECK-FISL: xxlxor 36, 36, 37
60 ; CHECK-FISL: vor 2, 4, 4
61 ; CHECK-FISL: blr
5262 }
5363
5464 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
5666 %v = xor <8 x i16> %a, %b
5767 ret <8 x i16> %v
5868
59 ; CHECK-LABEL: @test6
60 ; CHECK: xxlxor 34, 34, 35
61 ; CHECK: blr
69 ; CHECK-REG-LABEL: @test6
70 ; CHECK-REG: xxlxor 34, 34, 35
71 ; CHECK-REG: blr
72
73 ; CHECK-FISL-LABEL: @test6
74 ; CHECK-FISL: vor 4, 2, 2
75 ; CHECK-FISL: vor 5, 3, 3
76 ; CHECK-FISL: xxlxor 36, 36, 37
77 ; CHECK-FISL: vor 2, 4, 4
78 ; CHECK-FISL: blr
6279 }
6380
6481 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
6683 %v = xor <16 x i8> %a, %b
6784 ret <16 x i8> %v
6885
69 ; CHECK-LABEL: @test7
70 ; CHECK: xxlxor 34, 34, 35
71 ; CHECK: blr
86 ; CHECK-REG-LABEL: @test7
87 ; CHECK-REG: xxlxor 34, 34, 35
88 ; CHECK-REG: blr
89
90 ; CHECK-FISL-LABEL: @test7
91 ; CHECK-FISL: vor 4, 2, 2
92 ; CHECK-FISL: vor 5, 3, 3
93 ; CHECK-FISL: xxlxor 36, 36, 37
94 ; CHECK-FISL: vor 2, 4, 4
95 ; CHECK-FISL: blr
7296 }
7397
7498 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
76100 %v = or <4 x i32> %a, %b
77101 ret <4 x i32> %v
78102
79 ; CHECK-LABEL: @test8
80 ; CHECK: xxlor 34, 34, 35
81 ; CHECK: blr
103 ; CHECK-REG-LABEL: @test8
104 ; CHECK-REG: xxlor 34, 34, 35
105 ; CHECK-REG: blr
106
107 ; CHECK-FISL-LABEL: @test8
108 ; CHECK-FISL: vor 4, 2, 2
109 ; CHECK-FISL: vor 5, 3, 3
110 ; CHECK-FISL: xxlor 36, 36, 37
111 ; CHECK-FISL: vor 2, 4, 4
112 ; CHECK-FISL: blr
82113 }
83114
84115 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
86117 %v = or <8 x i16> %a, %b
87118 ret <8 x i16> %v
88119
89 ; CHECK-LABEL: @test9
90 ; CHECK: xxlor 34, 34, 35
91 ; CHECK: blr
120 ; CHECK-REG-LABEL: @test9
121 ; CHECK-REG: xxlor 34, 34, 35
122 ; CHECK-REG: blr
123
124 ; CHECK-FISL-LABEL: @test9
125 ; CHECK-FISL: vor 4, 2, 2
126 ; CHECK-FISL: vor 5, 3, 3
127 ; CHECK-FISL: xxlor 36, 36, 37
128 ; CHECK-FISL: vor 2, 4, 4
129 ; CHECK-FISL: blr
92130 }
93131
94132 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
96134 %v = or <16 x i8> %a, %b
97135 ret <16 x i8> %v
98136
99 ; CHECK-LABEL: @test10
100 ; CHECK: xxlor 34, 34, 35
101 ; CHECK: blr
137 ; CHECK-REG-LABEL: @test10
138 ; CHECK-REG: xxlor 34, 34, 35
139 ; CHECK-REG: blr
140
141 ; CHECK-FISL-LABEL: @test10
142 ; CHECK-FISL: vor 4, 2, 2
143 ; CHECK-FISL: vor 5, 3, 3
144 ; CHECK-FISL: xxlor 36, 36, 37
145 ; CHECK-FISL: vor 2, 4, 4
146 ; CHECK-FISL: blr
102147 }
103148
104149 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
106151 %v = and <4 x i32> %a, %b
107152 ret <4 x i32> %v
108153
109 ; CHECK-LABEL: @test11
110 ; CHECK: xxland 34, 34, 35
111 ; CHECK: blr
154 ; CHECK-REG-LABEL: @test11
155 ; CHECK-REG: xxland 34, 34, 35
156 ; CHECK-REG: blr
157
158 ; CHECK-FISL-LABEL: @test11
159 ; CHECK-FISL: vor 4, 2, 2
160 ; CHECK-FISL: vor 5, 3, 3
161 ; CHECK-FISL: xxland 36, 36, 37
162 ; CHECK-FISL: vor 2, 4, 4
163 ; CHECK-FISL: blr
112164 }
113165
114166 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
116168 %v = and <8 x i16> %a, %b
117169 ret <8 x i16> %v
118170
119 ; CHECK-LABEL: @test12
120 ; CHECK: xxland 34, 34, 35
121 ; CHECK: blr
171 ; CHECK-REG-LABEL: @test12
172 ; CHECK-REG: xxland 34, 34, 35
173 ; CHECK-REG: blr
174
175 ; CHECK-FISL-LABEL: @test12
176 ; CHECK-FISL: vor 4, 2, 2
177 ; CHECK-FISL: vor 5, 3, 3
178 ; CHECK-FISL: xxland 36, 36, 37
179 ; CHECK-FISL: vor 2, 4, 4
180 ; CHECK-FISL: blr
122181 }
123182
124183 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
126185 %v = and <16 x i8> %a, %b
127186 ret <16 x i8> %v
128187
129 ; CHECK-LABEL: @test13
130 ; CHECK: xxland 34, 34, 35
131 ; CHECK: blr
188 ; CHECK-REG-LABEL: @test13
189 ; CHECK-REG: xxland 34, 34, 35
190 ; CHECK-REG: blr
191
192 ; CHECK-FISL-LABEL: @test13
193 ; CHECK-FISL: vor 4, 2, 2
194 ; CHECK-FISL: vor 5, 3, 3
195 ; CHECK-FISL: xxland 36, 36, 37
196 ; CHECK-FISL: vor 2, 4, 4
197 ; CHECK-FISL: blr
132198 }
133199
134200 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
137203 %w = xor <4 x i32> %v,
138204 ret <4 x i32> %w
139205
140 ; CHECK-LABEL: @test14
141 ; CHECK: xxlnor 34, 34, 35
142 ; CHECK: blr
206 ; CHECK-REG-LABEL: @test14
207 ; CHECK-REG: xxlnor 34, 34, 35
208 ; CHECK-REG: blr
209
210 ; CHECK-FISL-LABEL: @test14
211 ; CHECK-FISL: vor 4, 2, 2
212 ; CHECK-FISL: vor 5, 3, 3
213 ; CHECK-FISL: xxlor 36, 36, 37
214 ; CHECK-FISL: vor 0, 4, 4
215 ; CHECK-FISL: vor 4, 2, 2
216 ; CHECK-FISL: vor 5, 3, 3
217 ; CHECK-FISL: xxlnor 36, 36, 37
218 ; CHECK-FISL: vor 2, 4, 4
219 ; CHECK-FISL: lis 0, -1
220 ; CHECK-FISL: ori 0, 0, 65520
221 ; CHECK-FISL: stvx 0, 1, 0
222 ; CHECK-FISL: blr
143223 }
144224
145225 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
148228 %w = xor <8 x i16> %v,
149229 ret <8 x i16> %w
150230
151 ; CHECK-LABEL: @test15
152 ; CHECK: xxlnor 34, 34, 35
153 ; CHECK: blr
231 ; CHECK-REG-LABEL: @test15
232 ; CHECK-REG: xxlnor 34, 34, 35
233 ; CHECK-REG: blr
234
235 ; CHECK-FISL-LABEL: @test15
236 ; CHECK-FISL: vor 4, 2, 2
237 ; CHECK-FISL: vor 5, 3, 3
238 ; CHECK-FISL: xxlor 36, 36, 37
239 ; CHECK-FISL: vor 0, 4, 4
240 ; CHECK-FISL: vor 4, 2, 2
241 ; CHECK-FISL: vor 5, 3, 3
242 ; CHECK-FISL: xxlnor 36, 36, 37
243 ; CHECK-FISL: vor 2, 4, 4
244 ; CHECK-FISL: lis 0, -1
245 ; CHECK-FISL: ori 0, 0, 65520
246 ; CHECK-FISL: stvx 0, 1, 0
247 ; CHECK-FISL: blr
154248 }
155249
156250 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
159253 %w = xor <16 x i8> %v,
160254 ret <16 x i8> %w
161255
162 ; CHECK-LABEL: @test16
163 ; CHECK: xxlnor 34, 34, 35
164 ; CHECK: blr
256 ; CHECK-REG-LABEL: @test16
257 ; CHECK-REG: xxlnor 34, 34, 35
258 ; CHECK-REG: blr
259
260 ; CHECK-FISL-LABEL: @test16
261 ; CHECK-FISL: vor 4, 2, 2
262 ; CHECK-FISL: vor 5, 3, 3
263 ; CHECK-FISL: xxlor 36, 36, 37
264 ; CHECK-FISL: vor 0, 4, 4
265 ; CHECK-FISL: vor 4, 2, 2
266 ; CHECK-FISL: vor 5, 3, 3
267 ; CHECK-FISL: xxlnor 36, 36, 37
268 ; CHECK-FISL: vor 2, 4, 4
269 ; CHECK-FISL: lis 0, -1
270 ; CHECK-FISL: ori 0, 0, 65520
271 ; CHECK-FISL: stvx 0, 1, 0
272 ; CHECK-FISL: blr
165273 }
166274
167275 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
170278 %v = and <4 x i32> %a, %w
171279 ret <4 x i32> %v
172280
173 ; CHECK-LABEL: @test17
174 ; CHECK: xxlandc 34, 34, 35
175 ; CHECK: blr
281 ; CHECK-REG-LABEL: @test17
282 ; CHECK-REG: xxlandc 34, 34, 35
283 ; CHECK-REG: blr
284
285 ; CHECK-FISL-LABEL: @test17
286 ; CHECK-FISL: vspltisb 4, -1
287 ; CHECK-FISL: vor 5, 3, 3
288 ; CHECK-FISL: vor 0, 4, 4
289 ; CHECK-FISL: xxlxor 37, 37, 32
290 ; CHECK-FISL: vor 3, 5, 5
291 ; CHECK-FISL: vor 5, 2, 2
292 ; CHECK-FISL: vor 0, 3, 3
293 ; CHECK-FISL: xxland 37, 37, 32
294 ; CHECK-FISL: vor 2, 5, 5
295 ; CHECK-FISL: blr
176296 }
177297
178298 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
181301 %v = and <8 x i16> %a, %w
182302 ret <8 x i16> %v
183303
184 ; CHECK-LABEL: @test18
185 ; CHECK: xxlandc 34, 34, 35
186 ; CHECK: blr
304 ; CHECK-REG-LABEL: @test18
305 ; CHECK-REG: xxlandc 34, 34, 35
306 ; CHECK-REG: blr
307
308 ; CHECK-FISL-LABEL: @test18
309 ; CHECK-FISL: vspltisb 4, -1
310 ; CHECK-FISL: vor 5, 3, 3
311 ; CHECK-FISL: vor 0, 4, 4
312 ; CHECK-FISL: xxlxor 37, 37, 32
313 ; CHECK-FISL: vor 4, 5, 5
314 ; CHECK-FISL: vor 5, 2, 2
315 ; CHECK-FISL: vor 0, 3, 3
316 ; CHECK-FISL: xxlandc 37, 37, 32
317 ; CHECK-FISL: vor 2, 5, 5
318 ; CHECK-FISL: lis 0, -1
319 ; CHECK-FISL: ori 0, 0, 65520
320 ; CHECK-FISL: stvx 4, 1, 0
321 ; CHECK-FISL: blr
187322 }
188323
189324 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
192327 %v = and <16 x i8> %a, %w
193328 ret <16 x i8> %v
194329
195 ; CHECK-LABEL: @test19
196 ; CHECK: xxlandc 34, 34, 35
197 ; CHECK: blr
330 ; CHECK-REG-LABEL: @test19
331 ; CHECK-REG: xxlandc 34, 34, 35
332 ; CHECK-REG: blr
333
334 ; CHECK-FISL-LABEL: @test19
335 ; CHECK-FISL: vspltisb 4, -1
336 ; CHECK-FISL: vor 5, 3, 3
337 ; CHECK-FISL: vor 0, 4, 4
338 ; CHECK-FISL: xxlxor 37, 37, 32
339 ; CHECK-FISL: vor 4, 5, 5
340 ; CHECK-FISL: vor 5, 2, 2
341 ; CHECK-FISL: vor 0, 3, 3
342 ; CHECK-FISL: xxlandc 37, 37, 32
343 ; CHECK-FISL: vor 2, 5, 5
344 ; CHECK-FISL: lis 0, -1
345 ; CHECK-FISL: ori 0, 0, 65520
346 ; CHECK-FISL: stvx 4, 1, 0
347 ; CHECK-FISL: blr
198348 }
199349
200350 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
203353 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
204354 ret <4 x i32> %v
205355
206 ; CHECK-LABEL: @test20
207 ; CHECK: vcmpequw {{[0-9]+}}, 4, 5
208 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
209 ; CHECK: blr
356 ; CHECK-REG-LABEL: @test20
357 ; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
358 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
359 ; CHECK-REG: blr
360
361 ; CHECK-FISL-LABEL: @test20
362 ; CHECK-FISL: vcmpequw 4, 4, 5
363 ; CHECK-FISL: vor 0, 3, 3
364 ; CHECK-FISL: vor 1, 2, 2
365 ; CHECK-FISL: vor 6, 4, 4
366 ; CHECK-FISL: xxsel 32, 32, 33, 38
367 ; CHECK-FISL: vor 2, 0, 0
368 ; CHECK-FISL: blr
210369 }
211370
212371 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
215374 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
216375 ret <4 x float> %v
217376
218 ; CHECK-LABEL: @test21
219 ; CHECK: xvcmpeqsp [[V1:[0-9]+]], 36, 37
220 ; CHECK: xxsel 34, 35, 34, [[V1]]
221 ; CHECK: blr
377 ; CHECK-REG-LABEL: @test21
378 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
379 ; CHECK-REG: xxsel 34, 35, 34, [[V1]]
380 ; CHECK-REG: blr
381
382 ; CHECK-FISL-LABEL: @test21
383 ; CHECK-FISL: vor 0, 5, 5
384 ; CHECK-FISL: vor 1, 4, 4
385 ; CHECK-FISL: vor 6, 3, 3
386 ; CHECK-FISL: vor 7, 2, 2
387 ; CHECK-FISL: xvcmpeqsp 32, 33, 32
388 ; CHECK-FISL: xxsel 32, 38, 39, 32
389 ; CHECK-FISL: vor 2, 0, 0
390 ; CHECK-FISL: blr
222391 }
223392
224393 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
227396 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
228397 ret <4 x float> %v
229398
230 ; CHECK-LABEL: @test22
231 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
232 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
233 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
234 ; CHECK-DAG: xxlnor
235 ; CHECK-DAG: xxlnor
236 ; CHECK-DAG: xxlor
237 ; CHECK-DAG: xxlor
238 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
239 ; CHECK: blr
399 ; CHECK-REG-LABEL: @test22
400 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
401 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
402 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
403 ; CHECK-REG-DAG: xxlnor
404 ; CHECK-REG-DAG: xxlnor
405 ; CHECK-REG-DAG: xxlor
406 ; CHECK-REG-DAG: xxlor
407 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
408 ; CHECK-REG: blr
409
410 ; CHECK-FISL-LABEL: @test22
411 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
412 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
413 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
414 ; CHECK-FISL-DAG: xxlnor
415 ; CHECK-FISL-DAG: xxlnor
416 ; CHECK-FISL-DAG: xxlor
417 ; CHECK-FISL-DAG: xxlor
418 ; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
419 ; CHECK-FISL: blr
240420 }
241421
242422 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
245425 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
246426 ret <8 x i16> %v
247427
248 ; CHECK-LABEL: @test23
249 ; CHECK: vcmpequh {{[0-9]+}}, 4, 5
250 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
251 ; CHECK: blr
428 ; CHECK-REG-LABEL: @test23
429 ; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
430 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
431 ; CHECK-REG: blr
432
433 ; CHECK-FISL-LABEL: @test23
434 ; CHECK-FISL: vcmpequh 4, 4, 5
435 ; CHECK-FISL: vor 0, 3, 3
436 ; CHECK-FISL: vor 1, 2, 2
437 ; CHECK-FISL: vor 6, 4, 4
438 ; CHECK-FISL: xxsel 32, 32, 33, 38
439 ; CHECK-FISL: vor 2, 0,
440 ; CHECK-FISL: blr
252441 }
253442
254443 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
257446 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
258447 ret <16 x i8> %v
259448
260 ; CHECK-LABEL: @test24
261 ; CHECK: vcmpequb {{[0-9]+}}, 4, 5
262 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
263 ; CHECK: blr
449 ; CHECK-REG-LABEL: @test24
450 ; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
451 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
452 ; CHECK-REG: blr
453
454 ; CHECK-FISL-LABEL: @test24
455 ; CHECK-FISL: vcmpequb 4, 4, 5
456 ; CHECK-FISL: vor 0, 3, 3
457 ; CHECK-FISL: vor 1, 2, 2
458 ; CHECK-FISL: vor 6, 4, 4
459 ; CHECK-FISL: xxsel 32, 32, 33, 38
460 ; CHECK-FISL: vor 2, 0, 0
461 ; CHECK-FISL: blr
264462 }
265463
266464 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
341539 %v = load <2 x i64>* %a, align 16
342540 ret <2 x i64> %v
343541
344 ; CHECK-LABEL: @test30
345 ; CHECK: lxvd2x 34, 0, 3
346 ; CHECK: blr
542 ; CHECK-REG-LABEL: @test30
543 ; CHECK-REG: lxvd2x 34, 0, 3
544 ; CHECK-REG: blr
545
546 ; CHECK-FISL-LABEL: @test30
547 ; CHECK-FISL: lxvd2x 0, 0, 3
548 ; CHECK-FISL: xxlor 34, 0, 0
549 ; CHECK-FISL: vor 3, 2, 2
550 ; CHECK-FISL: vor 2, 3, 3
551 ; CHECK-FISL: blr
347552 }
348553
349554 define void @test31(<2 x i64>* %a, <2 x i64> %b) {
359564 %v = load <4 x float>* %a, align 16
360565 ret <4 x float> %v
361566
362 ; CHECK-LABEL: @test32
363 ; CHECK: lxvw4x 34, 0, 3
364 ; CHECK: blr
567 ; CHECK-REG-LABEL: @test32
568 ; CHECK-REG: lxvw4x 34, 0, 3
569 ; CHECK-REG: blr
570
571 ; CHECK-FISL-LABEL: @test32
572 ; CHECK-FISL: lxvw4x 0, 0, 3
573 ; CHECK-FISL: xxlor 34, 0, 0
574 ; CHECK-FISL: blr
365575 }
366576
367577 define void @test33(<4 x float>* %a, <4 x float> %b) {
368578 store <4 x float> %b, <4 x float>* %a, align 16
369579 ret void
370580
371 ; CHECK-LABEL: @test33
372 ; CHECK: stxvw4x 34, 0, 3
373 ; CHECK: blr
581 ; CHECK-REG-LABEL: @test33
582 ; CHECK-REG: stxvw4x 34, 0, 3
583 ; CHECK-REG: blr
584
585 ; CHECK-FISL-LABEL: @test33
586 ; CHECK-FISL: vor 3, 2, 2
587 ; CHECK-FISL: stxvw4x 35, 0, 3
588 ; CHECK-FISL: blr
374589 }
375590
376591 define <4 x float> @test32u(<4 x float>* %a) {
389604 store <4 x float> %b, <4 x float>* %a, align 8
390605 ret void
391606
392 ; CHECK-LABEL: @test33u
393 ; CHECK: stxvw4x 34, 0, 3
394 ; CHECK: blr
607 ; CHECK-REG-LABEL: @test33u
608 ; CHECK-REG: stxvw4x 34, 0, 3
609 ; CHECK-REG: blr
610
611 ; CHECK-FISL-LABEL: @test33u
612 ; CHECK-FISL: vor 3, 2, 2
613 ; CHECK-FISL: stxvw4x 35, 0, 3
614 ; CHECK-FISL: blr
395615 }
396616
397617 define <4 x i32> @test34(<4 x i32>* %a) {
398618 %v = load <4 x i32>* %a, align 16
399619 ret <4 x i32> %v
400620
401 ; CHECK-LABEL: @test34
402 ; CHECK: lxvw4x 34, 0, 3
403 ; CHECK: blr
621 ; CHECK-REG-LABEL: @test34
622 ; CHECK-REG: lxvw4x 34, 0, 3
623 ; CHECK-REG: blr
624
625 ; CHECK-FISL-LABEL: @test34
626 ; CHECK-FISL: lxvw4x 0, 0, 3
627 ; CHECK-FISL: xxlor 34, 0, 0
628 ; CHECK-FISL: vor 3, 2, 2
629 ; CHECK-FISL: vor 2, 3, 3
630 ; CHECK-FISL: blr
404631 }
405632
406633 define void @test35(<4 x i32>* %a, <4 x i32> %b) {
407634 store <4 x i32> %b, <4 x i32>* %a, align 16
408635 ret void
409636
410 ; CHECK-LABEL: @test35
411 ; CHECK: stxvw4x 34, 0, 3
412 ; CHECK: blr
637 ; CHECK-REG-LABEL: @test35
638 ; CHECK-REG: stxvw4x 34, 0, 3
639 ; CHECK-REG: blr
640
641 ; CHECK-FISL-LABEL: @test35
642 ; CHECK-FISL: vor 3, 2, 2
643 ; CHECK-FISL: stxvw4x 35, 0, 3
644 ; CHECK-FISL: blr
413645 }
414646
415647 define <2 x double> @test40(<2 x i64> %a) {
595827 %v = extractelement <2 x double> %a, i32 0
596828 ret double %v
597829
598 ; CHECK-LABEL: @test63
599 ; CHECK: xxlor 1, 34, 34
600 ; CHECK: blr
830 ; CHECK-REG-LABEL: @test63
831 ; CHECK-REG: xxlor 1, 34, 34
832 ; CHECK-REG: blr
833
834 ; CHECK-FISL-LABEL: @test63
835 ; CHECK-FISL: xxlor 0, 34, 34
836 ; CHECK-FISL: fmr 1, 0
837 ; CHECK-FISL: blr
601838 }
602839
603840 define double @test64(<2 x double> %a) {
604841 %v = extractelement <2 x double> %a, i32 1
605842 ret double %v
606843
607 ; CHECK-LABEL: @test64
608 ; CHECK: xxpermdi 1, 34, 34, 2
609 ; CHECK: blr
844 ; CHECK-REG-LABEL: @test64
845 ; CHECK-REG: xxpermdi 1, 34, 34, 2
846 ; CHECK-REG: blr
847
848 ; CHECK-FISL-LABEL: @test64
849 ; CHECK-FISL: xxpermdi 34, 34, 34, 2
850 ; CHECK-FISL: xxlor 0, 34, 34
851 ; CHECK-FISL: fmr 1, 0
852 ; CHECK-FISL: blr
610853 }
611854
612855 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
613856 %w = icmp eq <2 x i64> %a, %b
614857 ret <2 x i1> %w
615858
616 ; CHECK-LABEL: @test65
617 ; CHECK: vcmpequw 2, 2, 3
618 ; CHECK: blr
859 ; CHECK-REG-LABEL: @test65
860 ; CHECK-REG: vcmpequw 2, 2, 3
861 ; CHECK-REG: blr
862
863 ; CHECK-FISL-LABEL: @test65
864 ; CHECK-FISL: vor 4, 3, 3
865 ; CHECK-FISL: vor 5, 2, 2
866 ; CHECK-FISL: vcmpequw 4, 5, 4
867 ; CHECK-FISL: vor 2, 4, 4
868 ; CHECK-FISL: blr
619869 }
620870
621871 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
622872 %w = icmp ne <2 x i64> %a, %b
623873 ret <2 x i1> %w
624874
625 ; CHECK-LABEL: @test66
626 ; CHECK: vcmpequw {{[0-9]+}}, 2, 3
627 ; CHECK: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
628 ; CHECK: blr
875 ; CHECK-REG-LABEL: @test66
876 ; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
877 ; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
878 ; CHECK-REG: blr
879
880 ; CHECK-FISL-LABEL: @test66
881 ; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
882 ; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
883 ; CHECK-FISL: blr
629884 }
630885
631886 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
659914 ; CHECK-LABEL: @test69
660915 ; CHECK: vspltisw [[V1:[0-9]+]], 8
661916 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
662 ; CHECK: vslw [[V3:[0-9]+]], 2, [[V2]]
917 ; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
663918 ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
664919 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
665920 ; CHECK: xvcvsxwdp 34, [[V4]]
673928 ; CHECK-LABEL: @test70
674929 ; CHECK: vspltisw [[V1:[0-9]+]], 12
675930 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
676 ; CHECK: vslw [[V3:[0-9]+]], 2, [[V2]]
931 ; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
677932 ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
678933 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
679934 ; CHECK: xvcvsxwdp 34, [[V4]]
686941 %i = add <2 x i32> %b2,
687942 ret <2 x i32> %i
688943
689 ; CHECK-LABEL: @test80
690 ; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3
691 ; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16
692 ; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2
693 ; CHECK: std [[R1]], -8(1)
694 ; CHECK: std [[R3]], -16(1)
695 ; CHECK: lxvd2x 34, 0, [[R2]]
696 ; CHECK-NOT: stxvd2x
697 ; CHECK: blr
944 ; CHECK-REG-LABEL: @test80
945 ; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
946 ; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
947 ; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
948 ; CHECK-REG: std [[R1]], -8(1)
949 ; CHECK-REG: std [[R3]], -16(1)
950 ; CHECK-REG: lxvd2x 34, 0, [[R2]]
951 ; CHECK-REG-NOT: stxvd2x
952 ; CHECK-REG: blr
953
954 ; CHECK-FISL-LABEL: @test80
955 ; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3
956 ; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16
957 ; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2
958 ; CHECK-FISL-DAG: std [[R1]], -8(1)
959 ; CHECK-FISL-DAG: std [[R3]], -16(1)
960 ; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
961 ; CHECK-FISL: blr
698962 }
699963
700964 define <2 x double> @test81(<4 x float> %b) {
711975 %v = select i1 %m, double %a, double %b
712976 ret double %v
713977
714 ; CHECK-LABEL: @test82
715 ; CHECK: xscmpudp [[REG:[0-9]+]], 3, 4
716 ; CHECK: beqlr [[REG]]
717 }
718
978 ; CHECK-REG-LABEL: @test82
979 ; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
980 ; CHECK-REG: beqlr [[REG]]
981
982 ; CHECK-FISL-LABEL: @test82
983 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
984 ; CHECK-FISL: beq [[REG]], {{.*}}
985 }