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Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD." This reverts commit r267733 due to a -Werror,-Wunused-function error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267752 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 4 years ago
9 changed file(s) with 14 addition(s) and 147 deletion(s). Raw diff Collapse all Expand all
610610 default: return -1;
611611 case 1: return AMDGPU::TTMP_32RegClassID;
612612 case 2: return AMDGPU::TTMP_64RegClassID;
613 case 4: return AMDGPU::TTMP_128RegClassID;
614613 }
615614 } else if (Is == IS_SGPR) {
616615 switch (RegWidth) {
617616 default: return -1;
618617 case 1: return AMDGPU::SGPR_32RegClassID;
619618 case 2: return AMDGPU::SGPR_64RegClassID;
620 case 4: return AMDGPU::SGPR_128RegClassID;
619 case 4: return AMDGPU::SReg_128RegClassID;
621620 case 8: return AMDGPU::SReg_256RegClassID;
622621 case 16: return AMDGPU::SReg_512RegClassID;
623622 }
6767
6868 DECODE_OPERAND(SGPR_32)
6969 DECODE_OPERAND(SReg_32)
70 DECODE_OPERAND(SReg_32_XM0)
7170 DECODE_OPERAND(SReg_64)
7271 DECODE_OPERAND(SReg_128)
7372 DECODE_OPERAND(SReg_256)
246245 // leaving only registry class so SSrc_32 operand turns into SReg_32
247246 // and therefore we accept immediates and literals here as well
248247 return decodeSrcOp(OP32, Val);
249 }
250
251 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {
252 // SReg_32_XM0 is SReg_32 without M0
253 return decodeOperand_SReg_32(Val);
254248 }
255249
256250 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
6363
6464 MCOperand decodeOperand_SGPR_32(unsigned Val) const;
6565 MCOperand decodeOperand_SReg_32(unsigned Val) const;
66 MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
6766 MCOperand decodeOperand_SReg_64(unsigned Val) const;
6867 MCOperand decodeOperand_SReg_128(unsigned Val) const;
6968 MCOperand decodeOperand_SReg_256(unsigned Val) const;
239239 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
240240 Type = "v";
241241 NumRegs = 4;
242 } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(reg)) {
242 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
243243 Type = "s";
244 NumRegs = 4;
245 } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(reg)) {
246 Type = "ttmp";
247244 NumRegs = 4;
248245 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
249246 Type = "v";
5959 // SMRD Instructions
6060 //===----------------------------------------------------------------------===//
6161
62 // We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
63 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
62 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
63 // SMRD instructions, because the SGPR_32 register class does not include M0
6464 // and writing to M0 from an SMRD instruction will hang the GPU.
65 defm S_LOAD_DWORD : SMRD_Helper , "s_load_dword", SReg_64, SReg_32_XM0>;
65 defm S_LOAD_DWORD : SMRD_Helper , "s_load_dword", SReg_64, SGPR_32>;
6666 defm S_LOAD_DWORDX2 : SMRD_Helper , "s_load_dwordx2", SReg_64, SReg_64>;
6767 defm S_LOAD_DWORDX4 : SMRD_Helper , "s_load_dwordx4", SReg_64, SReg_128>;
6868 defm S_LOAD_DWORDX8 : SMRD_Helper , "s_load_dwordx8", SReg_64, SReg_256>;
6969 defm S_LOAD_DWORDX16 : SMRD_Helper , "s_load_dwordx16", SReg_64, SReg_512>;
7070
7171 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
72 smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0
72 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32
7373 >;
7474
7575 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
20862086 }
20872087
20882088 // It's unclear whether you can use M0 as the output of v_readlane_b32
2089 // instructions, so use SReg_32_XM0 register class for spills to prevent
2089 // instructions, so use SGPR_32 register class for spills to prevent
20902090 // this from happening.
2091 defm SI_SPILL_S32 : SI_SPILL_SGPR Reg_32_XM0>;
2091 defm SI_SPILL_S32 : SI_SPILL_SGPR GPR_32>;
20922092 defm SI_SPILL_S64 : SI_SPILL_SGPR ;
20932093 defm SI_SPILL_S128 : SI_SPILL_SGPR ;
20942094 defm SI_SPILL_S256 : SI_SPILL_SGPR ;
34303430 def : Pat <
34313431 (i64 (sext i32:$src)),
34323432 (REG_SEQUENCE SReg_64, $src, sub0,
3433 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
3433 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SGPR_32)), sub1)
34343434 >;
34353435
34363436 def : Pat <
131131 (add (decimate (shl SGPR_32, 1), 2))]>;
132132
133133 // SGPR 128-bit registers
134 def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
134 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
135135 [(add (decimate SGPR_32, 4)),
136136 (add (decimate (shl SGPR_32, 1), 4)),
137137 (add (decimate (shl SGPR_32, 2), 4)),
254254 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
255255 >;
256256
257 // Subset of SReg_32 without M0 for SMRD instructions and alike.
258 // See comments in SIInstructions.td for more info.
259 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32,
260 (add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
261 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
262 >;
263
264257 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;
265258
266259 def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
271264 (add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA)
272265 >;
273266
274 // Requires 2 s_mov_b64 to copy
275 let CopyCost = 2 in {
276
277 def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)>;
278
279 def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
280 let isAllocatable = 0;
281 }
282
283 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)>;
284
285 } // End CopyCost = 2
267 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)> {
268 // Requires 2 s_mov_b64 to copy
269 let CopyCost = 2;
270 }
286271
287272 def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
288273 // Requires 4 s_mov_b64 to copy
1717 // SICI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
1818 // VI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
1919
20 buffer_load_dword v1, ttmp[4:7], s1
21 // SICI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]
22 // VI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]
23
2420 buffer_load_dword v1, s[4:7], s1 offset:4
2521 // SICI: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
2622 // VI: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
4541 // SICI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
4642 // VI: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
4743
48 buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe
49 // SICI: buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xdd,0x01]
50 // VI: buffer_load_dword v1, ttmp[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x9d,0x01]
5144
5245 //===----------------------------------------------------------------------===//
5346 // load - vgpr offset
8174 // SICI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01]
8275 // VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x81,0x01]
8376
84 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
85 // SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xdd,0x01]
86 // VI: buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52,0xe0,0x02,0x01,0x9d,0x01]
87
8877 //===----------------------------------------------------------------------===//
8978 // load - vgpr index
9079 //===----------------------------------------------------------------------===//
117106 // SICI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01]
118107 // VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x81,0x01]
119108
120 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
121 // SICI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xdd,0x01]
122 // VI: buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52,0xe0,0x02,0x01,0x9d,0x01]
123
124109 //===----------------------------------------------------------------------===//
125110 // load - vgpr index and offset
126111 //===----------------------------------------------------------------------===//
153138 // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01]
154139 // VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x81,0x01]
155140
156 buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
157 // SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xdd,0x71]
158 // VI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x52,0xe0,0x02,0x01,0x9d,0x71]
159
160141 //===----------------------------------------------------------------------===//
161142 // load - addr64
162143 //===----------------------------------------------------------------------===//
187168
188169 buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
189170 // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01]
190 // NOVI: error: instruction not supported on this GPU
191
192 buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
193 // SICI: buffer_load_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xdd,0x71]
194171 // NOVI: error: instruction not supported on this GPU
195172
196173 //===----------------------------------------------------------------------===//
225202 // SICI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
226203 // VI: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x81,0x01]
227204
228 buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe
229 // SICI: buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xdd,0x71]
230 // VI: buffer_store_dword v1, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x9d,0x71]
231
232205 //===----------------------------------------------------------------------===//
233206 // store - vgpr offset
234207 //===----------------------------------------------------------------------===//
261234 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
262235 // VI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x81,0x01]
263236
264 buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
265 // SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xdd,0x71]
266 // VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x9d,0x71]
267
268237 //===----------------------------------------------------------------------===//
269238 // store - vgpr index
270239 //===----------------------------------------------------------------------===//
297266 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
298267 // VI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x81,0x01]
299268
300 buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe
301 // SICI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xdd,0x71]
302 // VI: buffer_store_dword v1, v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x9d,0x71]
303
304269 //===----------------------------------------------------------------------===//
305270 // store - vgpr index and offset
306271 //===----------------------------------------------------------------------===//
333298 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
334299 // VI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x81,0x01]
335300
336 buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
337 // SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xdd,0x71]
338 // VI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x9d,0x71]
339
340301 //===----------------------------------------------------------------------===//
341302 // store - addr64
342303 //===----------------------------------------------------------------------===//
367328
368329 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
369330 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
370 // NOVI: error: instruction not supported on this GPU
371
372 buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
373 // SICI: buffer_store_dword v1, v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xdd,0x71]
374331 // NOVI: error: instruction not supported on this GPU
375332
376333 //===----------------------------------------------------------------------===//
409366 // SICI: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]
410367 // VI: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01]
411368
412 buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1
413 // SICI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
414 // VI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
415
416369 buffer_load_ubyte v1, s[4:7], s1
417370 // SICI: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]
418371 // VI: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x01,0x01]
419372
420 buffer_load_ubyte v1, ttmp[4:7], ttmp1
421 // SICI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]
422 // VI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]
423
424373 buffer_load_sbyte v1, s[4:7], s1
425374 // SICI: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01]
426375 // VI: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x44,0xe0,0x00,0x01,0x01,0x01]
437386 // SICI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
438387 // VI: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
439388
440 buffer_load_dword v1, ttmp[4:7], ttmp1
441 // SICI: buffer_load_dword v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x71]
442 // VI: buffer_load_dword v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x71]
443
444389 buffer_load_dwordx2 v[1:2], s[4:7], s1
445390 // SICI: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01]
446391 // VI: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x54,0xe0,0x00,0x01,0x01,0x01]
449394 // SICI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]
450395 // VI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]
451396
452 buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1
453 // SICI: buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x1d,0x71]
454 // VI: buffer_load_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x1d,0x71]
455
456397 buffer_store_byte v1, s[4:7], s1
457398 // SICI: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]
458399 // VI: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01]
459400
460 buffer_store_byte v1, ttmp[4:7], ttmp1
461 // SICI: buffer_store_byte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]
462 // VI: buffer_store_byte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x1d,0x71]
463
464401 buffer_store_short v1, s[4:7], s1
465402 // SICI: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]
466403 // VI: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01]
476413 buffer_store_dwordx4 v[1:4], s[4:7], s1
477414 // SICI: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01]
478415 // VI: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x01,0x01]
479
480 buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1
481 // SICI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]
482 // VI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]
483416
484417 //===----------------------------------------------------------------------===//
485418 // Cache invalidation
5252 buffer_load_dwordx4 [v1,v2,v3,v4], [s4,s5,s6,s7], s1
5353 // SICI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01]
5454 // VI: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x5c,0xe0,0x00,0x01,0x01,0x01]
55
56 buffer_load_dword v1, [ttmp4,ttmp5,ttmp6,ttmp7], s1
57 // SICI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0x01]
58 // VI: buffer_load_dword v1, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0x01]
59
60 buffer_store_format_xyzw v[1:4], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
61 // SICI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
62 // VI: buffer_store_format_xyzw v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x1d,0x71]
63
64 buffer_load_ubyte v1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
65 // SICI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x1d,0x71]
66 // VI: buffer_load_ubyte v1, ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x40,0xe0,0x00,0x01,0x1d,0x71]
67
68 buffer_store_dwordx4 v[1:4], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1
69 // SICI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x1d,0x71]
70 // VI: buffer_store_dwordx4 v[1:4], ttmp[4:7], ttmp1 ; encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x1d,0x71]
71
72 s_load_dwordx4 [ttmp4,ttmp5,ttmp6,ttmp7], [ttmp2,ttmp3], ttmp4
73 // SICI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]
74 // VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]
75
76 s_buffer_load_dword ttmp1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
77 // SICI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
78 // VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]
79
80 s_buffer_load_dwordx4 [ttmp8,ttmp9,ttmp10,ttmp11], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
81 // SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
82 // VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
5151 // GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
5252 // VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
5353
54 s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4
55 // GCN: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x74,0x72,0xba,0xc0]
56 // VI: s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 ; encoding: [0x39,0x1d,0x08,0xc0,0x74,0x00,0x00,0x00]
57
5854 s_load_dwordx4 s[100:103], s[2:3], s4
5955 // GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
6056 // NOVI: error: invalid operand for instruction
9187 // GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]
9288 // VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
9389
94 s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4
95 // GCN: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
96 // VI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]
97
9890 s_buffer_load_dwordx2 s[8:9], s[4:7], 1
9991 // GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2]
10092 // VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]
110102 s_buffer_load_dwordx4 s[8:11], s[4:7], s4
111103 // GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2]
112104 // VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]
113
114 s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4
115 // GCN: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
116 // VI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
117105
118106 s_buffer_load_dwordx4 s[100:103], s[4:7], s4
119107 // GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]