llvm.org GIT mirror llvm / 8d1440d
Merging r155668: ------------------------------------------------------------------------ r155668 | atrick | 2012-04-26 14:48:25 -0700 (Thu, 26 Apr 2012) | 8 lines Fix the SD scheduler to avoid gluing the same node twice. DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_31@155672 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
2 changed file(s) with 51 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
137137 // Don't add glue from a node to itself.
138138 if (GlueDestNode == N) return;
139139
140 // Don't add glue to something which already has glue.
141 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return;
142
140 // Don't add glue to something that already has it, either as a use or value.
141 if (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue ||
142 N->getValueType(N->getNumValues() - 1) == MVT::Glue) {
143 return;
144 }
143145 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
144146 VTs.push_back(N->getValueType(I));
145147
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx | FileCheck %s
1 ; rdar://11314175: SD Scheduler, BuildSchedUnits assert:
2 ; N->getNodeId() == -1 && "Node already inserted!
3
4 ; It's hard to test for the ISEL condition because CodeGen optimizes
5 ; away the bugpointed code. Just ensure the basics are still there.
6 ;CHECK: func:
7 ;CHECK: vmovups
8 ;CHECK: vpshufd
9 ;CHECK: vpshufd
10 ;CHECK: vmulps
11 ;CHECK: vmulps
12 ;CHECK: ret
13
14 define void @func() nounwind ssp {
15 %tmp = load <4 x float>* null, align 1
16 %tmp14 = getelementptr <4 x float>* null, i32 2
17 %tmp15 = load <4 x float>* %tmp14, align 1
18 %tmp16 = shufflevector <4 x float> %tmp, <4 x float> , <8 x i32>
19 %tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)
20 %tmp18 = bitcast <4 x float> %tmp to <16 x i8>
21 %tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32>
22 %tmp20 = bitcast <16 x i8> %tmp19 to <4 x float>
23 %tmp21 = bitcast <4 x float> %tmp15 to <16 x i8>
24 %tmp22 = shufflevector <16 x i8> undef, <16 x i8> %tmp21, <16 x i32>
25 %tmp23 = bitcast <16 x i8> %tmp22 to <4 x float>
26 %tmp24 = shufflevector <4 x float> %tmp20, <4 x float> , <8 x i32>
27 %tmp25 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp24, <4 x float> %tmp23, i8 1)
28 %tmp26 = fmul <8 x float> %tmp17, undef
29 %tmp27 = fmul <8 x float> %tmp25, undef
30 %tmp28 = fadd <8 x float> %tmp26, %tmp27
31 %tmp29 = fadd <8 x float> %tmp28, undef
32 %tmp30 = shufflevector <8 x float> %tmp29, <8 x float> undef, <4 x i32>
33 %tmp31 = fmul <4 x float> undef, %tmp30
34 %tmp32 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> zeroinitializer, <4 x float> %tmp31, i8 1)
35 %tmp33 = fadd <8 x float> undef, %tmp32
36 %tmp34 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %tmp33, <8 x float> undef) nounwind
37 %tmp35 = fsub <8 x float> %tmp34, undef
38 %tmp36 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> zeroinitializer, <8 x float> %tmp35) nounwind
39 store <8 x float> %tmp36, <8 x float>* undef, align 32
40 ret void
41 }
42
43 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
44
45 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone