llvm.org GIT mirror llvm / 8cd08bf
Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163511 91177308-0d34-0410-b5e6-96231b3b80d8 James Molloy 8 years ago
3 changed file(s) with 22 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
80948094 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
80958095 return SDValue();
80968096
8097 // If the input vector type has a different base type to the output
8098 // vector type, bail out.
8099 if (VecIn1.getValueType().getVectorElementType() !=
8100 VT.getVectorElementType())
8101 return SDValue();
8102
80978103 // Widen the input vector by adding undef values.
80988104 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
80998105 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
29332933 // expanding large vector constants.
29342934 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
29352935 SDValue Elt = N1.getOperand(N2C->getZExtValue());
2936 EVT VEltTy = N1.getValueType().getVectorElementType();
2937 if (Elt.getValueType() != VEltTy) {
2936
2937 if (VT != Elt.getValueType())
29382938 // If the vector element type is not legal, the BUILD_VECTOR operands
2939 // are promoted and implicitly truncated. Make that explicit here.
2940 Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt);
2941 }
2942 if (VT != VEltTy) {
2943 // If the vector element type is not legal, the EXTRACT_VECTOR_ELT
2944 // result is implicitly extended.
2945 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt);
2946 }
2939 // are promoted and implicitly truncated, and the result implicitly
2940 // extended. Make that explicit here.
2941 Elt = getAnyExtOrTrunc(Elt, DL, VT);
2942
29472943 return Elt;
29482944 }
29492945
0 ; RUN: llc < %s -mtriple=armv7
1
2 declare void @g(<16 x i8>)
3 define void @f(<4 x i8> %param1, <4 x i8> %param2) {
4 %y1 = shufflevector <4 x i8> %param1, <4 x i8> undef, <16 x i32>
5 %y2 = shufflevector <4 x i8> %param2, <4 x i8> undef, <16 x i32>
6 %z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32>
7 call void @g(<16 x i8> %z)
8 ret void
9 }