llvm.org GIT mirror llvm / 8cc6281
[ARM] Fix disassembly of invalid banked register moves When disassembling banked register move instructions, we don't have an assembly syntax for the unallocated register numbers, so we have to return Fail rather than SoftFail. Previously we were returning SoftFail, then crashing in the InstPrinter as we have no way to represent these encodings in an assembly string. This also switches the decoder to use the table-generated list of banked registers, removing the duplicated list of encodings. Differential revision: https://reviews.llvm.org/D43066 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324600 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 2 years ago
3 changed file(s) with 35 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
42044204 // The table of encodings for these banked registers comes from B9.2.3 of the
42054205 // ARM ARM. There are patterns, but nothing regular enough to make this logic
42064206 // neater. So by fiat, these values are UNPREDICTABLE:
4207 if (!R) {
4208 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4209 SysM == 0x1a || SysM == 0x1b)
4210 return MCDisassembler::SoftFail;
4211 } else {
4212 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4213 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4214 return MCDisassembler::SoftFail;
4215 }
4207 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4208 return MCDisassembler::Fail;
42164209
42174210 Inst.addOperand(MCOperand::createImm(Val));
42184211 return MCDisassembler::Success;
None # RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
0 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple armv7 2>&1 | FileCheck %s
11
22 # This file is checking ARMv7 encodings which are globally invalid, usually due
33 # to the constraints of the instructions not being met. For example invalid
499499 [0x3d 0x3c 0xa0 0xf4]
500500 # CHECK: invalid instruction encoding
501501 # CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
502
503
504 #------------------------------------------------------------------------------
505 # Undefined encodings for MSR/MRS (banked register)
506 #------------------------------------------------------------------------------
507 # These have a banked register encoding of 0b111111, which is unallocated.
508
509 # msr , r0
510 [0x00,0xf3,0x6f,0xe1]
511 # CHECK: invalid instruction encoding
512 # CHECK-NEXT: [0x00,0xf3,0x6f,0xe1]
513
514 # mrs r0,
515 [0x00,0x03,0x4f,0xe1]
516 # CHECK: invalid instruction encoding
517 # CHECK-NEXT: [0x00,0x03,0x4f,0xe1]
None # RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
0 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
11 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
22
33 # This file is checking Thumbv7 encodings which are globally invalid, usually due
378378 [0x63 0xeb 0x2d 0x46]
379379 # CHECK-V7: warning: potentially undefined instruction encoding
380380 # CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]
381
382 #------------------------------------------------------------------------------
383 # Undefined encodings for MSR/MRS (banked register)
384 #------------------------------------------------------------------------------
385 # These have a banked register encoding of 0b111111, which is unallocated.
386
387 # msr , r0
388 [0x90,0xf3,0x30,0x8f]
389 # CHECK: invalid instruction encoding
390 # CHECK-NEXT: [0x90,0xf3,0x30,0x8f]
391
392 # mrs r0,
393 [0xff,0xf3,0x30,0x80]
394 # CHECK: invalid instruction encoding
395 # CHECK-NEXT: [0xff,0xf3,0x30,0x80]