llvm.org GIT mirror llvm / 8ca5c67
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
6 changed file(s) with 42 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
3131
3232 template class SmallVectorImpl;
3333
34 //---------------------------------------------------------------------------
34 //===----------------------------------------------------------------------===//
3535 // Data types used to define information about a single machine instruction
36 //---------------------------------------------------------------------------
36 //===----------------------------------------------------------------------===//
3737
3838 typedef short MachineOpCode;
3939 typedef unsigned InstrSchedClass;
4040
41 //---------------------------------------------------------------------------
41 //===----------------------------------------------------------------------===//
4242 // struct TargetInstrDescriptor:
4343 // Predefined information about each machine instruction.
4444 // Designed to initialized statically.
123123 // both! If neither flag is set, then the instruction *always* has side effects.
124124 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
125125
126
127 //===----------------------------------------------------------------------===//
126128 // Machine operand flags
127 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
128 // requires a callback to look up its register class.
129 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
130
131 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
132 /// predicate operand that controls an M_PREDICATED instruction.
133 const unsigned M_PREDICATE_OPERAND = 1 << 1;
134
135 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
136 ///
137 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
138
129 //===----------------------------------------------------------------------===//
130
139131 namespace TOI {
140132 // Operand constraints: only "tied_to" for now.
141133 enum OperandConstraint {
142134 TIED_TO = 0 // Must be allocated the same register as.
135 };
136
137 /// OperandFlags - These are flags set on operands, but should be considered
138 /// private, all access should go through the TargetOperandInfo accessors.
139 /// See the accessors for a description of what these are.
140 enum OperandFlags {
141 LookupPtrRegClass = 1 << 0,
142 Predicate = 1 << 1,
143 OptionalDef = 1 << 2
143144 };
144145 }
145146
156157 /// bits are used to specify the value of constraints (4 bits each).
157158 unsigned int Constraints;
158159 /// Currently no other information.
160
161 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
162 /// requires a callback to look up its register class.
163 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
164
165 /// isPredicate - Set if this is one of the operands that made up of
166 /// the predicate operand that controls an M_PREDICATED instruction.
167 bool isPredicate() const { return Flags & TOI::Predicate; }
168
169 /// isOptionalDef - Set if this operand is a optional def.
170 ///
171 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
159172 };
160173
161174
540540 const TargetInstrDescriptor *TID = getDesc();
541541 if (TID->isPredicable()) {
542542 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
543 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
543 if (TID->OpInfo[i].isPredicate())
544544 return i;
545545 }
546546
590590 const TargetInstrDescriptor *TID = MI->getDesc();
591591 if (TID->isPredicable()) {
592592 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
593 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
593 if (TID->OpInfo[i].isPredicate()) {
594594 // Predicated operands must be last operands.
595595 addOperand(MI->getOperand(i));
596596 }
295295 assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
296296 return NULL;
297297 }
298 const TargetOperandInfo &toi = II->OpInfo[Op];
299 return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
300 ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
298 if (II->OpInfo[Op].isLookupPtrRegClass())
299 return TII->getPointerRegClass();
300 return MRI->getRegClass(II->OpInfo[Op].RegClass);
301301 }
302302
303303 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
434434 unsigned VReg = getVR(Op, VRBaseMap);
435435 const TargetInstrDescriptor *TID = MI->getDesc();
436436 bool isOptDef = (IIOpNum < TID->numOperands)
437 ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
437 ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
438438 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
439439
440440 // Verify that it is right.
3737 const TargetInstrDescriptor *TID = MI->getDesc();
3838 if (TID->isPredicable()) {
3939 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
40 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
40 if (TID->OpInfo[i].isPredicate()) {
4141 MachineOperand &MO = MI->getOperand(i);
4242 if (MO.isReg()) {
4343 MO.setReg(Pred[j].getReg());
18811881
18821882 const TargetInstrDescriptor &TID = get(Opc);
18831883 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1884 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1884 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
18851885 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
18861886 SmallVector AddrOps;
18871887 SmallVector BeforeOps;
19561956 // Emit the store instruction.
19571957 if (UnfoldStore) {
19581958 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1959 const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1959 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
19601960 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
19611961 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
19621962 }
19801980 bool FoldedStore = I->second.second & (1 << 5);
19811981 const TargetInstrDescriptor &TID = get(Opc);
19821982 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1983 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1983 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
19841984 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
19851985 std::vector AddrOps;
19861986 std::vector BeforeOps;
20122012 const TargetRegisterClass *DstRC = 0;
20132013 if (TID.numDefs > 0) {
20142014 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2015 DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
2015 DstRC = DstTOI.isLookupPtrRegClass()
20162016 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
20172017 VTs.push_back(*DstRC->vt_begin());
20182018 }
9393
9494 // Ptr value whose register class is resolved via callback.
9595 if (OpR->getName() == "ptr_rc")
96 Res += "|M_LOOK_UP_PTR_REG_CLASS";
96 Res += "|TOI::LookupPtrRegClass";
9797
9898 // Predicate operands. Check to see if the original unexpanded operand
9999 // was of type PredicateOperand.
100100 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
101 Res += "|M_PREDICATE_OPERAND";
101 Res += "|TOI::Predicate";
102102
103103 // Optional def operands. Check to see if the original unexpanded operand
104104 // was of type OptionalDefOperand.
105105 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
106 Res += "|M_OPTIONAL_DEF_OPERAND";
106 Res += "|TOI::OptionalDef";
107107
108108 // Fill in constraint info.
109109 Res += ", " + Inst.OperandList[i].Constraints[j];