llvm.org GIT mirror llvm / 8c9e52a
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 7 years ago
11 changed file(s) with 104 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
5858 "FP compare + branch is slow">;
5959 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
6060 "Floating point unit supports single precision only">;
61 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
62 "Enable support for TrustZone security extensions">;
6163
6264 // Some processors have FP multiply-accumulate instructions that don't
6365 // play nicely with other VFP / NEON instructions, and it's generally better
143145 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
144146 "Cortex-A5 ARM processors",
145147 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
146 FeatureVMLxForwarding, FeatureT2XtPk]>;
148 FeatureVMLxForwarding, FeatureT2XtPk,
149 FeatureTrustZone]>;
147150 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
148151 "Cortex-A8 ARM processors",
149152 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
150 FeatureVMLxForwarding, FeatureT2XtPk]>;
153 FeatureVMLxForwarding, FeatureT2XtPk,
154 FeatureTrustZone]>;
151155 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
152156 "Cortex-A9 ARM processors",
153157 [FeatureVMLxForwarding,
154158 FeatureT2XtPk, FeatureFP16,
155 FeatureAvoidPartialCPSR]>;
159 FeatureAvoidPartialCPSR,
160 FeatureTrustZone]>;
156161 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
157162 "Swift ARM processors",
158163 [FeatureNEONForFP, FeatureT2XtPk,
159164 FeatureVFP4, FeatureMP, FeatureHWDiv,
160165 FeatureHWDivARM, FeatureAvoidPartialCPSR,
161166 FeatureAvoidMOVsShOp,
162 FeatureHasSlowFPVMLx]>;
167 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
163168
164169 // FIXME: It has not been determined if A15 has these features.
165170 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
166171 "Cortex-A15 ARM processors",
167172 [FeatureT2XtPk, FeatureFP16,
168 FeatureAvoidPartialCPSR]>;
173 FeatureAvoidPartialCPSR,
174 FeatureTrustZone]>;
169175 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
170176 "Cortex-R5 ARM processors",
171177 [FeatureSlowFPBrcc, FeatureHWDivARM,
220220 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
221221 AssemblerPredicate<"FeatureMP",
222222 "mp-extensions">;
223 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
224 AssemblerPredicate<"FeatureTrustZone",
225 "TrustZone">;
223226 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
224227 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
225228 def IsThumb : Predicate<"Subtarget->isThumb()">,
20762079
20772080 // Secure Monitor Call is a system instruction.
20782081 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2079 []> {
2082 []>, Requires<[IsARM, HasTrustZone]> {
20802083 bits<4> opt;
20812084 let Inst{23-4} = 0b01100000000000000111;
20822085 let Inst{3-0} = opt;
34483448
34493449 // Secure Monitor Call is a system instruction.
34503450 // Option = Inst{19-16}
3451 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3451 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3452 []>, Requires<[IsThumb2, HasTrustZone]> {
34523453 let Inst{31-27} = 0b11110;
34533454 let Inst{26-20} = 0b1111111;
34543455 let Inst{15-12} = 0b1000;
9090 HasRAS = false;
9191 HasMPExtension = false;
9292 FPOnlySP = false;
93 HasTrustZone = false;
9394 AllowsUnalignedMem = false;
9495 Thumb2DSP = false;
9596 UseNaClTrap = false;
146146 /// FPOnlySP - If true, the floating point unit only supports single
147147 /// precision.
148148 bool FPOnlySP;
149
150 /// HasTrustZone - if true, processor supports TrustZone security extensions
151 bool HasTrustZone;
149152
150153 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
151154 /// accesses for some types. For details, see
250253 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
251254 bool isFPBrccSlow() const { return SlowFPBrcc; }
252255 bool isFPOnlySP() const { return FPOnlySP; }
256 bool hasTrustZone() const { return HasTrustZone; }
253257 bool prefers32BitThumb() const { return Pref32BitThumb; }
254258 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
255259 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
0 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
1 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
2
3 .syntax unified
4 .globl _func
5
6 @ Check that the assembler processes SMC instructions when TrustZone support is
7 @ active and that it rejects them when this feature is not enabled
8
9 _func:
10 @ CHECK: _func
11
12
13 @------------------------------------------------------------------------------
14 @ SMC
15 @------------------------------------------------------------------------------
16 smc #0xf
17 ite eq
18 smceq #0
19
20 @ NOTZ-NOT: smc #15
21 @ NOTZ-NOT: smceq #0
22 @ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80]
23 @ TZ: ite eq @ encoding: [0x0c,0xbf]
24 @ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80]
0 @ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
1 @ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
2
3 .syntax unified
4 .globl _func
5
6 @ Check that the assembler processes SMC instructions when TrustZone support is
7 @ active and that it rejects them when this feature is not enabled
8
9 _func:
10 @ CHECK: _func
11
12
13 @------------------------------------------------------------------------------
14 @ SMC
15 @------------------------------------------------------------------------------
16 smc #0xf
17 smceq #0
18
19 @ NOTZ-NOT: smc #15
20 @ NOTZ-NOT: smceq #0
21 @ TZ: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1]
22 @ TZ: smceq #0 @ encoding: [0x70,0x00,0x60,0x01]
23
17901790 @ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6]
17911791
17921792 @------------------------------------------------------------------------------
1793 @ SMC
1794 @------------------------------------------------------------------------------
1795 smc #0xf
1796 smceq #0
1797
1798 @ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1]
1799 @ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01]
1800
1801 @------------------------------------------------------------------------------
18021793 @ SMLABB/SMLABT/SMLATB/SMLATT
18031794 @------------------------------------------------------------------------------
18041795 smlabb r3, r1, r9, r0
0 # RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
1 # RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
2
3
4 #------------------------------------------------------------------------------
5 # SMC
6 #------------------------------------------------------------------------------
7
8 0xff 0xf7 0x00 0x80
9 0x0c 0xbf
10 0xf0 0xf7 0x00 0x80
11
12 # NOTZ-NOT: smc #15
13 # NOTZ-NOT: smceq #0
14 # TZ: smc #15
15 # TZ: ite eq
16 # TZ: smceq #0
0 # RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
1 # RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
2
3
4 #------------------------------------------------------------------------------
5 # SMC
6 #------------------------------------------------------------------------------
7
8 0x7f 0x00 0x60 0xe1
9 0x70 0x00 0x60 0x01
10
11 # NOTZ-NOT: smc #15
12 # NOTZ-NOT: smceq #0
13 # TZ: smc #15
14 # TZ: smceq #0
15
14411441 0xf2 0x4f 0x38 0xc6
14421442
14431443 #------------------------------------------------------------------------------
1444 # SMC
1445 #------------------------------------------------------------------------------
1446 # CHECK: smc #15
1447 # CHECK: smceq #0
1448
1449 0x7f 0x00 0x60 0xe1
1450 0x70 0x00 0x60 0x01
1451
1452 #------------------------------------------------------------------------------
14531444 # SMLABB/SMLABT/SMLATB/SMLATT
14541445 #------------------------------------------------------------------------------
14551446 # CHECK: smlabb r3, r1, r9, r0