llvm.org GIT mirror llvm / 8c3fee5
Refactor X86 target to separate MC code from Target code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
13 changed file(s) with 623 addition(s) and 589 deletion(s). Raw diff Collapse all Expand all
2727 #include "llvm/ADT/Statistic.h"
2828 #include "llvm/ADT/StringSwitch.h"
2929
30 #include "../Target/X86/X86FixupKinds.h"
30 #include "../Target/X86/MCTargetDesc/X86FixupKinds.h"
3131 #include "../Target/ARM/MCTargetDesc/ARMFixupKinds.h"
3232
3333 #include
3232
3333 #include "llvm/Support/TimeValue.h"
3434
35 #include "../Target/X86/X86FixupKinds.h"
35 #include "../Target/X86/MCTargetDesc/X86FixupKinds.h"
3636
3737 #include
3838
0 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the X86 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15
16 #ifndef X86BASEINFO_H
17 #define X86BASEINFO_H
18
19 #include "X86MCTargetDesc.h"
20 #include "llvm/Support/DataTypes.h"
21 #include
22
23 namespace llvm {
24
25 namespace X86 {
26 // Enums for memory operand decoding. Each memory operand is represented with
27 // a 5 operand sequence in the form:
28 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
29 // These enums help decode this.
30 enum {
31 AddrBaseReg = 0,
32 AddrScaleAmt = 1,
33 AddrIndexReg = 2,
34 AddrDisp = 3,
35
36 /// AddrSegmentReg - The operand # of the segment in the memory operand.
37 AddrSegmentReg = 4,
38
39 /// AddrNumOperands - Total number of operands in a memory reference.
40 AddrNumOperands = 5
41 };
42 } // end namespace X86;
43
44
45 /// X86II - This namespace holds all of the target specific flags that
46 /// instruction info tracks.
47 ///
48 namespace X86II {
49 /// Target Operand Flag enum.
50 enum TOF {
51 //===------------------------------------------------------------------===//
52 // X86 Specific MachineOperand flags.
53
54 MO_NO_FLAG,
55
56 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
57 /// relocation of:
58 /// SYMBOL_LABEL + [. - PICBASELABEL]
59 MO_GOT_ABSOLUTE_ADDRESS,
60
61 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
62 /// immediate should get the value of the symbol minus the PIC base label:
63 /// SYMBOL_LABEL - PICBASELABEL
64 MO_PIC_BASE_OFFSET,
65
66 /// MO_GOT - On a symbol operand this indicates that the immediate is the
67 /// offset to the GOT entry for the symbol name from the base of the GOT.
68 ///
69 /// See the X86-64 ELF ABI supplement for more details.
70 /// SYMBOL_LABEL @GOT
71 MO_GOT,
72
73 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
74 /// the offset to the location of the symbol name from the base of the GOT.
75 ///
76 /// See the X86-64 ELF ABI supplement for more details.
77 /// SYMBOL_LABEL @GOTOFF
78 MO_GOTOFF,
79
80 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
81 /// offset to the GOT entry for the symbol name from the current code
82 /// location.
83 ///
84 /// See the X86-64 ELF ABI supplement for more details.
85 /// SYMBOL_LABEL @GOTPCREL
86 MO_GOTPCREL,
87
88 /// MO_PLT - On a symbol operand this indicates that the immediate is
89 /// offset to the PLT entry of symbol name from the current code location.
90 ///
91 /// See the X86-64 ELF ABI supplement for more details.
92 /// SYMBOL_LABEL @PLT
93 MO_PLT,
94
95 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
96 /// some TLS offset.
97 ///
98 /// See 'ELF Handling for Thread-Local Storage' for more details.
99 /// SYMBOL_LABEL @TLSGD
100 MO_TLSGD,
101
102 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
103 /// some TLS offset.
104 ///
105 /// See 'ELF Handling for Thread-Local Storage' for more details.
106 /// SYMBOL_LABEL @GOTTPOFF
107 MO_GOTTPOFF,
108
109 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
110 /// some TLS offset.
111 ///
112 /// See 'ELF Handling for Thread-Local Storage' for more details.
113 /// SYMBOL_LABEL @INDNTPOFF
114 MO_INDNTPOFF,
115
116 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
117 /// some TLS offset.
118 ///
119 /// See 'ELF Handling for Thread-Local Storage' for more details.
120 /// SYMBOL_LABEL @TPOFF
121 MO_TPOFF,
122
123 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
124 /// some TLS offset.
125 ///
126 /// See 'ELF Handling for Thread-Local Storage' for more details.
127 /// SYMBOL_LABEL @NTPOFF
128 MO_NTPOFF,
129
130 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
131 /// reference is actually to the "__imp_FOO" symbol. This is used for
132 /// dllimport linkage on windows.
133 MO_DLLIMPORT,
134
135 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
136 /// reference is actually to the "FOO$stub" symbol. This is used for calls
137 /// and jumps to external functions on Tiger and earlier.
138 MO_DARWIN_STUB,
139
140 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
141 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
142 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
143 MO_DARWIN_NONLAZY,
144
145 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
146 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
147 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
148 MO_DARWIN_NONLAZY_PIC_BASE,
149
150 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
151 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
152 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
153 /// stub.
154 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
155
156 /// MO_TLVP - On a symbol operand this indicates that the immediate is
157 /// some TLS offset.
158 ///
159 /// This is the TLS offset for the Darwin TLS mechanism.
160 MO_TLVP,
161
162 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
163 /// is some TLS offset from the picbase.
164 ///
165 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
166 MO_TLVP_PIC_BASE
167 };
168
169 enum {
170 //===------------------------------------------------------------------===//
171 // Instruction encodings. These are the standard/most common forms for X86
172 // instructions.
173 //
174
175 // PseudoFrm - This represents an instruction that is a pseudo instruction
176 // or one that has not been implemented yet. It is illegal to code generate
177 // it, but tolerated for intermediate implementation stages.
178 Pseudo = 0,
179
180 /// Raw - This form is for instructions that don't have any operands, so
181 /// they are just a fixed opcode value, like 'leave'.
182 RawFrm = 1,
183
184 /// AddRegFrm - This form is used for instructions like 'push r32' that have
185 /// their one register operand added to their opcode.
186 AddRegFrm = 2,
187
188 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
189 /// to specify a destination, which in this case is a register.
190 ///
191 MRMDestReg = 3,
192
193 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
194 /// to specify a destination, which in this case is memory.
195 ///
196 MRMDestMem = 4,
197
198 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
199 /// to specify a source, which in this case is a register.
200 ///
201 MRMSrcReg = 5,
202
203 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
204 /// to specify a source, which in this case is memory.
205 ///
206 MRMSrcMem = 6,
207
208 /// MRM[0-7][rm] - These forms are used to represent instructions that use
209 /// a Mod/RM byte, and use the middle field to hold extended opcode
210 /// information. In the intel manual these are represented as /0, /1, ...
211 ///
212
213 // First, instructions that operate on a register r/m operand...
214 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
215 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
216
217 // Next, instructions that operate on a memory r/m operand...
218 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
219 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
220
221 // MRMInitReg - This form is used for instructions whose source and
222 // destinations are the same register.
223 MRMInitReg = 32,
224
225 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
226 MRM_C1 = 33,
227 MRM_C2 = 34,
228 MRM_C3 = 35,
229 MRM_C4 = 36,
230 MRM_C8 = 37,
231 MRM_C9 = 38,
232 MRM_E8 = 39,
233 MRM_F0 = 40,
234 MRM_F8 = 41,
235 MRM_F9 = 42,
236 MRM_D0 = 45,
237 MRM_D1 = 46,
238
239 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
240 /// immediates, the first of which is a 16-bit immediate (specified by
241 /// the imm encoding) and the second is a 8-bit fixed value.
242 RawFrmImm8 = 43,
243
244 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
245 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
246 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
247 /// manual, this operand is described as pntr16:32 and pntr16:16
248 RawFrmImm16 = 44,
249
250 FormMask = 63,
251
252 //===------------------------------------------------------------------===//
253 // Actual flags...
254
255 // OpSize - Set if this instruction requires an operand size prefix (0x66),
256 // which most often indicates that the instruction operates on 16 bit data
257 // instead of 32 bit data.
258 OpSize = 1 << 6,
259
260 // AsSize - Set if this instruction requires an operand size prefix (0x67),
261 // which most often indicates that the instruction address 16 bit address
262 // instead of 32 bit address (or 32 bit address in 64 bit mode).
263 AdSize = 1 << 7,
264
265 //===------------------------------------------------------------------===//
266 // Op0Mask - There are several prefix bytes that are used to form two byte
267 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
268 // used to obtain the setting of this field. If no bits in this field is
269 // set, there is no prefix byte for obtaining a multibyte opcode.
270 //
271 Op0Shift = 8,
272 Op0Mask = 0x1F << Op0Shift,
273
274 // TB - TwoByte - Set if this instruction has a two byte opcode, which
275 // starts with a 0x0F byte before the real opcode.
276 TB = 1 << Op0Shift,
277
278 // REP - The 0xF3 prefix byte indicating repetition of the following
279 // instruction.
280 REP = 2 << Op0Shift,
281
282 // D8-DF - These escape opcodes are used by the floating point unit. These
283 // values must remain sequential.
284 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
285 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
286 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
287 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
288
289 // XS, XD - These prefix codes are for single and double precision scalar
290 // floating point operations performed in the SSE registers.
291 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
292
293 // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
294 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
295 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
296
297 // TF - Prefix before and after 0x0F
298 TF = 17 << Op0Shift,
299
300 //===------------------------------------------------------------------===//
301 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
302 // They are used to specify GPRs and SSE registers, 64-bit operand size,
303 // etc. We only cares about REX.W and REX.R bits and only the former is
304 // statically determined.
305 //
306 REXShift = Op0Shift + 5,
307 REX_W = 1 << REXShift,
308
309 //===------------------------------------------------------------------===//
310 // This three-bit field describes the size of an immediate operand. Zero is
311 // unused so that we can tell if we forgot to set a value.
312 ImmShift = REXShift + 1,
313 ImmMask = 7 << ImmShift,
314 Imm8 = 1 << ImmShift,
315 Imm8PCRel = 2 << ImmShift,
316 Imm16 = 3 << ImmShift,
317 Imm16PCRel = 4 << ImmShift,
318 Imm32 = 5 << ImmShift,
319 Imm32PCRel = 6 << ImmShift,
320 Imm64 = 7 << ImmShift,
321
322 //===------------------------------------------------------------------===//
323 // FP Instruction Classification... Zero is non-fp instruction.
324
325 // FPTypeMask - Mask for all of the FP types...
326 FPTypeShift = ImmShift + 3,
327 FPTypeMask = 7 << FPTypeShift,
328
329 // NotFP - The default, set for instructions that do not use FP registers.
330 NotFP = 0 << FPTypeShift,
331
332 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
333 ZeroArgFP = 1 << FPTypeShift,
334
335 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
336 OneArgFP = 2 << FPTypeShift,
337
338 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
339 // result back to ST(0). For example, fcos, fsqrt, etc.
340 //
341 OneArgFPRW = 3 << FPTypeShift,
342
343 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
344 // explicit argument, storing the result to either ST(0) or the implicit
345 // argument. For example: fadd, fsub, fmul, etc...
346 TwoArgFP = 4 << FPTypeShift,
347
348 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
349 // explicit argument, but have no destination. Example: fucom, fucomi, ...
350 CompareFP = 5 << FPTypeShift,
351
352 // CondMovFP - "2 operand" floating point conditional move instructions.
353 CondMovFP = 6 << FPTypeShift,
354
355 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
356 SpecialFP = 7 << FPTypeShift,
357
358 // Lock prefix
359 LOCKShift = FPTypeShift + 3,
360 LOCK = 1 << LOCKShift,
361
362 // Segment override prefixes. Currently we just need ability to address
363 // stuff in gs and fs segments.
364 SegOvrShift = LOCKShift + 1,
365 SegOvrMask = 3 << SegOvrShift,
366 FS = 1 << SegOvrShift,
367 GS = 2 << SegOvrShift,
368
369 // Execution domain for SSE instructions in bits 23, 24.
370 // 0 in bits 23-24 means normal, non-SSE instruction.
371 SSEDomainShift = SegOvrShift + 2,
372
373 OpcodeShift = SSEDomainShift + 2,
374
375 //===------------------------------------------------------------------===//
376 /// VEX - The opcode prefix used by AVX instructions
377 VEXShift = OpcodeShift + 8,
378 VEX = 1U << 0,
379
380 /// VEX_W - Has a opcode specific functionality, but is used in the same
381 /// way as REX_W is for regular SSE instructions.
382 VEX_W = 1U << 1,
383
384 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
385 /// address instructions in SSE are represented as 3 address ones in AVX
386 /// and the additional register is encoded in VEX_VVVV prefix.
387 VEX_4V = 1U << 2,
388
389 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
390 /// must be encoded in the i8 immediate field. This usually happens in
391 /// instructions with 4 operands.
392 VEX_I8IMM = 1U << 3,
393
394 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
395 /// instruction uses 256-bit wide registers. This is usually auto detected
396 /// if a VR256 register is used, but some AVX instructions also have this
397 /// field marked when using a f256 memory references.
398 VEX_L = 1U << 4,
399
400 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
401 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
402 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
403 /// storing a classifier in the imm8 field. To simplify our implementation,
404 /// we handle this by storeing the classifier in the opcode field and using
405 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
406 Has3DNow0F0FOpcode = 1U << 5
407 };
408
409 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
410 // specified machine instruction.
411 //
412 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
413 return TSFlags >> X86II::OpcodeShift;
414 }
415
416 static inline bool hasImm(uint64_t TSFlags) {
417 return (TSFlags & X86II::ImmMask) != 0;
418 }
419
420 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
421 /// of the specified instruction.
422 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
423 switch (TSFlags & X86II::ImmMask) {
424 default: assert(0 && "Unknown immediate size");
425 case X86II::Imm8:
426 case X86II::Imm8PCRel: return 1;
427 case X86II::Imm16:
428 case X86II::Imm16PCRel: return 2;
429 case X86II::Imm32:
430 case X86II::Imm32PCRel: return 4;
431 case X86II::Imm64: return 8;
432 }
433 }
434
435 /// isImmPCRel - Return true if the immediate of the specified instruction's
436 /// TSFlags indicates that it is pc relative.
437 static inline unsigned isImmPCRel(uint64_t TSFlags) {
438 switch (TSFlags & X86II::ImmMask) {
439 default: assert(0 && "Unknown immediate size");
440 case X86II::Imm8PCRel:
441 case X86II::Imm16PCRel:
442 case X86II::Imm32PCRel:
443 return true;
444 case X86II::Imm8:
445 case X86II::Imm16:
446 case X86II::Imm32:
447 case X86II::Imm64:
448 return false;
449 }
450 }
451
452 /// getMemoryOperandNo - The function returns the MCInst operand # for the
453 /// first field of the memory operand. If the instruction doesn't have a
454 /// memory operand, this returns -1.
455 ///
456 /// Note that this ignores tied operands. If there is a tied register which
457 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
458 /// counted as one operand.
459 ///
460 static inline int getMemoryOperandNo(uint64_t TSFlags) {
461 switch (TSFlags & X86II::FormMask) {
462 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
463 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
464 case X86II::Pseudo:
465 case X86II::RawFrm:
466 case X86II::AddRegFrm:
467 case X86II::MRMDestReg:
468 case X86II::MRMSrcReg:
469 case X86II::RawFrmImm8:
470 case X86II::RawFrmImm16:
471 return -1;
472 case X86II::MRMDestMem:
473 return 0;
474 case X86II::MRMSrcMem: {
475 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
476 unsigned FirstMemOp = 1;
477 if (HasVEX_4V)
478 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
479
480 // FIXME: Maybe lea should have its own form? This is a horrible hack.
481 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
482 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
483 return FirstMemOp;
484 }
485 case X86II::MRM0r: case X86II::MRM1r:
486 case X86II::MRM2r: case X86II::MRM3r:
487 case X86II::MRM4r: case X86II::MRM5r:
488 case X86II::MRM6r: case X86II::MRM7r:
489 return -1;
490 case X86II::MRM0m: case X86II::MRM1m:
491 case X86II::MRM2m: case X86II::MRM3m:
492 case X86II::MRM4m: case X86II::MRM5m:
493 case X86II::MRM6m: case X86II::MRM7m:
494 return 0;
495 case X86II::MRM_C1:
496 case X86II::MRM_C2:
497 case X86II::MRM_C3:
498 case X86II::MRM_C4:
499 case X86II::MRM_C8:
500 case X86II::MRM_C9:
501 case X86II::MRM_E8:
502 case X86II::MRM_F0:
503 case X86II::MRM_F8:
504 case X86II::MRM_F9:
505 case X86II::MRM_D0:
506 case X86II::MRM_D1:
507 return -1;
508 }
509 }
510
511 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
512 /// higher) register? e.g. r8, xmm8, xmm13, etc.
513 static inline bool isX86_64ExtendedReg(unsigned RegNo) {
514 switch (RegNo) {
515 default: break;
516 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
517 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
518 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
519 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
520 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
521 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
522 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
523 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
524 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
525 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
526 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
527 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
528 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
529 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
530 return true;
531 }
532 return false;
533 }
534
535 static inline bool isX86_64NonExtLowByteReg(unsigned reg) {
536 return (reg == X86::SPL || reg == X86::BPL ||
537 reg == X86::SIL || reg == X86::DIL);
538 }
539 }
540
541 } // end namespace llvm;
542
543 #endif
0 //===-- X86/X86FixupKinds.h - X86 Specific Fixup Entries --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_X86_X86FIXUPKINDS_H
10 #define LLVM_X86_X86FIXUPKINDS_H
11
12 #include "llvm/MC/MCFixup.h"
13
14 namespace llvm {
15 namespace X86 {
16 enum Fixups {
17 reloc_riprel_4byte = FirstTargetFixupKind, // 32-bit rip-relative
18 reloc_riprel_4byte_movq_load, // 32-bit rip-relative in movq
19 reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4
20 // this will be sign extended at
21 // runtime.
22 reloc_global_offset_table, // 32-bit, relative to the start
23 // of the instruction. Used only
24 // for _GLOBAL_OFFSET_TABLE_.
25 // Marker
26 LastTargetFixupKind,
27 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
28 };
29 }
30 }
31
32 #endif
1616 #include
1717
1818 namespace llvm {
19 class MCCodeEmitter;
20 class MCContext;
21 class MCInstrInfo;
1922 class MCRegisterInfo;
2023 class MCSubtargetInfo;
2124 class Target;
6265 StringRef FS);
6366 }
6467
68 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
69 const MCSubtargetInfo &STI,
70 MCContext &Ctx);
71
72
6573 } // End llvm namespace
6674
6775
1414 #ifndef TARGET_X86_H
1515 #define TARGET_X86_H
1616
17 #include "MCTargetDesc/X86BaseInfo.h"
1718 #include "MCTargetDesc/X86MCTargetDesc.h"
1819 #include "llvm/Support/DataTypes.h"
1920 #include "llvm/Target/TargetMachine.h"
5960 FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
6061 JITCodeEmitter &JCE);
6162
62 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx);
65
6663 TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
6764 TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
6865
88
99 #include "llvm/MC/TargetAsmBackend.h"
1010 #include "X86.h"
11 #include "X86FixupKinds.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
1212 #include "llvm/ADT/Twine.h"
1313 #include "llvm/MC/MCAssembler.h"
1414 #include "llvm/MC/MCELFObjectWriter.h"
166166 const MachineOperand& MO = MI.getOperand(i);
167167 if (MO.isReg()) {
168168 unsigned Reg = MO.getReg();
169 if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
169 if (X86II::isX86_64NonExtLowByteReg(Reg))
170170 REX |= 0x40;
171171 }
172172 }
+0
-33
lib/Target/X86/X86FixupKinds.h less more
None //===-- X86/X86FixupKinds.h - X86 Specific Fixup Entries --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_X86_X86FIXUPKINDS_H
10 #define LLVM_X86_X86FIXUPKINDS_H
11
12 #include "llvm/MC/MCFixup.h"
13
14 namespace llvm {
15 namespace X86 {
16 enum Fixups {
17 reloc_riprel_4byte = FirstTargetFixupKind, // 32-bit rip-relative
18 reloc_riprel_4byte_movq_load, // 32-bit rip-relative in movq
19 reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4
20 // this will be sign extended at
21 // runtime.
22 reloc_global_offset_table, // 32-bit, relative to the start
23 // of the instruction. Used only
24 // for _GLOBAL_OFFSET_TABLE_.
25 // Marker
26 LastTargetFixupKind,
27 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
28 };
29 }
30 }
31
32 #endif
30123012 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
30133013 }
30143014
3015
3016 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3017 /// register? e.g. r8, xmm8, xmm13, etc.
3018 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3019 switch (RegNo) {
3020 default: break;
3021 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3022 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3023 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3024 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3025 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3026 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3027 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3028 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3029 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3030 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3031 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
3032 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
3033 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
3034 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
3035 return true;
3036 }
3037 return false;
3038 }
3039
30403015 /// getGlobalBaseReg - Return a virtual register initialized with the
30413016 /// the global base register value. Output instructions required to
30423017 /// initialize the register in the function entry block, if necessary.
2626 class X86TargetMachine;
2727
2828 namespace X86 {
29 // Enums for memory operand decoding. Each memory operand is represented with
30 // a 5 operand sequence in the form:
31 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
32 // These enums help decode this.
33 enum {
34 AddrBaseReg = 0,
35 AddrScaleAmt = 1,
36 AddrIndexReg = 2,
37 AddrDisp = 3,
38
39 /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 AddrSegmentReg = 4,
41
42 /// AddrNumOperands - Total number of operands in a memory reference.
43 AddrNumOperands = 5
44 };
45
46
4729 // X86 specific condition code. These correspond to X86_*_COND in
4830 // X86InstrInfo.td. They must be kept in synch.
4931 enum CondCode {
8163 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
8264 /// e.g. turning COND_E to COND_NE.
8365 CondCode GetOppositeBranchCondition(X86::CondCode CC);
84
85 }
86
87 /// X86II - This namespace holds all of the target specific flags that
88 /// instruction info tracks.
89 ///
90 namespace X86II {
91 /// Target Operand Flag enum.
92 enum TOF {
93 //===------------------------------------------------------------------===//
94 // X86 Specific MachineOperand flags.
95
96 MO_NO_FLAG,
97
98 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
99 /// relocation of:
100 /// SYMBOL_LABEL + [. - PICBASELABEL]
101 MO_GOT_ABSOLUTE_ADDRESS,
102
103 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
104 /// immediate should get the value of the symbol minus the PIC base label:
105 /// SYMBOL_LABEL - PICBASELABEL
106 MO_PIC_BASE_OFFSET,
107
108 /// MO_GOT - On a symbol operand this indicates that the immediate is the
109 /// offset to the GOT entry for the symbol name from the base of the GOT.
110 ///
111 /// See the X86-64 ELF ABI supplement for more details.
112 /// SYMBOL_LABEL @GOT
113 MO_GOT,
114
115 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
116 /// the offset to the location of the symbol name from the base of the GOT.
117 ///
118 /// See the X86-64 ELF ABI supplement for more details.
119 /// SYMBOL_LABEL @GOTOFF
120 MO_GOTOFF,
121
122 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
123 /// offset to the GOT entry for the symbol name from the current code
124 /// location.
125 ///
126 /// See the X86-64 ELF ABI supplement for more details.
127 /// SYMBOL_LABEL @GOTPCREL
128 MO_GOTPCREL,
129
130 /// MO_PLT - On a symbol operand this indicates that the immediate is
131 /// offset to the PLT entry of symbol name from the current code location.
132 ///
133 /// See the X86-64 ELF ABI supplement for more details.
134 /// SYMBOL_LABEL @PLT
135 MO_PLT,
136
137 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
138 /// some TLS offset.
139 ///
140 /// See 'ELF Handling for Thread-Local Storage' for more details.
141 /// SYMBOL_LABEL @TLSGD
142 MO_TLSGD,
143
144 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
145 /// some TLS offset.
146 ///
147 /// See 'ELF Handling for Thread-Local Storage' for more details.
148 /// SYMBOL_LABEL @GOTTPOFF
149 MO_GOTTPOFF,
150
151 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
152 /// some TLS offset.
153 ///
154 /// See 'ELF Handling for Thread-Local Storage' for more details.
155 /// SYMBOL_LABEL @INDNTPOFF
156 MO_INDNTPOFF,
157
158 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
159 /// some TLS offset.
160 ///
161 /// See 'ELF Handling for Thread-Local Storage' for more details.
162 /// SYMBOL_LABEL @TPOFF
163 MO_TPOFF,
164
165 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
166 /// some TLS offset.
167 ///
168 /// See 'ELF Handling for Thread-Local Storage' for more details.
169 /// SYMBOL_LABEL @NTPOFF
170 MO_NTPOFF,
171
172 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
173 /// reference is actually to the "__imp_FOO" symbol. This is used for
174 /// dllimport linkage on windows.
175 MO_DLLIMPORT,
176
177 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
178 /// reference is actually to the "FOO$stub" symbol. This is used for calls
179 /// and jumps to external functions on Tiger and earlier.
180 MO_DARWIN_STUB,
181
182 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
183 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
184 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
185 MO_DARWIN_NONLAZY,
186
187 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
188 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
189 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
190 MO_DARWIN_NONLAZY_PIC_BASE,
191
192 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
193 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
194 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
195 /// stub.
196 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
197
198 /// MO_TLVP - On a symbol operand this indicates that the immediate is
199 /// some TLS offset.
200 ///
201 /// This is the TLS offset for the Darwin TLS mechanism.
202 MO_TLVP,
203
204 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
205 /// is some TLS offset from the picbase.
206 ///
207 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
208 MO_TLVP_PIC_BASE
209 };
210 }
66 } // end namespace X86;
67
21168
21269 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
21370 /// a reference to a stub for a global, not the global itself.
23996 return true;
24097 default:
24198 return false;
242 }
243 }
244
245 /// X86II - This namespace holds all of the target specific flags that
246 /// instruction info tracks.
247 ///
248 namespace X86II {
249 enum {
250 //===------------------------------------------------------------------===//
251 // Instruction encodings. These are the standard/most common forms for X86
252 // instructions.
253 //
254
255 // PseudoFrm - This represents an instruction that is a pseudo instruction
256 // or one that has not been implemented yet. It is illegal to code generate
257 // it, but tolerated for intermediate implementation stages.
258 Pseudo = 0,
259
260 /// Raw - This form is for instructions that don't have any operands, so
261 /// they are just a fixed opcode value, like 'leave'.
262 RawFrm = 1,
263
264 /// AddRegFrm - This form is used for instructions like 'push r32' that have
265 /// their one register operand added to their opcode.
266 AddRegFrm = 2,
267
268 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
269 /// to specify a destination, which in this case is a register.
270 ///
271 MRMDestReg = 3,
272
273 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
274 /// to specify a destination, which in this case is memory.
275 ///
276 MRMDestMem = 4,
277
278 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
279 /// to specify a source, which in this case is a register.
280 ///
281 MRMSrcReg = 5,
282
283 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
284 /// to specify a source, which in this case is memory.
285 ///
286 MRMSrcMem = 6,
287
288 /// MRM[0-7][rm] - These forms are used to represent instructions that use
289 /// a Mod/RM byte, and use the middle field to hold extended opcode
290 /// information. In the intel manual these are represented as /0, /1, ...
291 ///
292
293 // First, instructions that operate on a register r/m operand...
294 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
295 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
296
297 // Next, instructions that operate on a memory r/m operand...
298 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
299 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
300
301 // MRMInitReg - This form is used for instructions whose source and
302 // destinations are the same register.
303 MRMInitReg = 32,
304
305 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
306 MRM_C1 = 33,
307 MRM_C2 = 34,
308 MRM_C3 = 35,
309 MRM_C4 = 36,
310 MRM_C8 = 37,
311 MRM_C9 = 38,
312 MRM_E8 = 39,
313 MRM_F0 = 40,
314 MRM_F8 = 41,
315 MRM_F9 = 42,
316 MRM_D0 = 45,
317 MRM_D1 = 46,
318
319 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
320 /// immediates, the first of which is a 16-bit immediate (specified by
321 /// the imm encoding) and the second is a 8-bit fixed value.
322 RawFrmImm8 = 43,
323
324 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
325 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
326 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
327 /// manual, this operand is described as pntr16:32 and pntr16:16
328 RawFrmImm16 = 44,
329
330 FormMask = 63,
331
332 //===------------------------------------------------------------------===//
333 // Actual flags...
334
335 // OpSize - Set if this instruction requires an operand size prefix (0x66),
336 // which most often indicates that the instruction operates on 16 bit data
337 // instead of 32 bit data.
338 OpSize = 1 << 6,
339
340 // AsSize - Set if this instruction requires an operand size prefix (0x67),
341 // which most often indicates that the instruction address 16 bit address
342 // instead of 32 bit address (or 32 bit address in 64 bit mode).
343 AdSize = 1 << 7,
344
345 //===------------------------------------------------------------------===//
346 // Op0Mask - There are several prefix bytes that are used to form two byte
347 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
348 // used to obtain the setting of this field. If no bits in this field is
349 // set, there is no prefix byte for obtaining a multibyte opcode.
350 //
351 Op0Shift = 8,
352 Op0Mask = 0x1F << Op0Shift,
353
354 // TB - TwoByte - Set if this instruction has a two byte opcode, which
355 // starts with a 0x0F byte before the real opcode.
356 TB = 1 << Op0Shift,
357
358 // REP - The 0xF3 prefix byte indicating repetition of the following
359 // instruction.
360 REP = 2 << Op0Shift,
361
362 // D8-DF - These escape opcodes are used by the floating point unit. These
363 // values must remain sequential.
364 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
365 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
366 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
367 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
368
369 // XS, XD - These prefix codes are for single and double precision scalar
370 // floating point operations performed in the SSE registers.
371 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
372
373 // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
374 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
375 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
376
377 // TF - Prefix before and after 0x0F
378 TF = 17 << Op0Shift,
379
380 //===------------------------------------------------------------------===//
381 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
382 // They are used to specify GPRs and SSE registers, 64-bit operand size,
383 // etc. We only cares about REX.W and REX.R bits and only the former is
384 // statically determined.
385 //
386 REXShift = Op0Shift + 5,
387 REX_W = 1 << REXShift,
388
389 //===------------------------------------------------------------------===//
390 // This three-bit field describes the size of an immediate operand. Zero is
391 // unused so that we can tell if we forgot to set a value.
392 ImmShift = REXShift + 1,
393 ImmMask = 7 << ImmShift,
394 Imm8 = 1 << ImmShift,
395 Imm8PCRel = 2 << ImmShift,
396 Imm16 = 3 << ImmShift,
397 Imm16PCRel = 4 << ImmShift,
398 Imm32 = 5 << ImmShift,
399 Imm32PCRel = 6 << ImmShift,
400 Imm64 = 7 << ImmShift,
401
402 //===------------------------------------------------------------------===//
403 // FP Instruction Classification... Zero is non-fp instruction.
404
405 // FPTypeMask - Mask for all of the FP types...
406 FPTypeShift = ImmShift + 3,
407 FPTypeMask = 7 << FPTypeShift,
408
409 // NotFP - The default, set for instructions that do not use FP registers.
410 NotFP = 0 << FPTypeShift,
411
412 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
413 ZeroArgFP = 1 << FPTypeShift,
414
415 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
416 OneArgFP = 2 << FPTypeShift,
417
418 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
419 // result back to ST(0). For example, fcos, fsqrt, etc.
420 //
421 OneArgFPRW = 3 << FPTypeShift,
422
423 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
424 // explicit argument, storing the result to either ST(0) or the implicit
425 // argument. For example: fadd, fsub, fmul, etc...
426 TwoArgFP = 4 << FPTypeShift,
427
428 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
429 // explicit argument, but have no destination. Example: fucom, fucomi, ...
430 CompareFP = 5 << FPTypeShift,
431
432 // CondMovFP - "2 operand" floating point conditional move instructions.
433 CondMovFP = 6 << FPTypeShift,
434
435 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
436 SpecialFP = 7 << FPTypeShift,
437
438 // Lock prefix
439 LOCKShift = FPTypeShift + 3,
440 LOCK = 1 << LOCKShift,
441
442 // Segment override prefixes. Currently we just need ability to address
443 // stuff in gs and fs segments.
444 SegOvrShift = LOCKShift + 1,
445 SegOvrMask = 3 << SegOvrShift,
446 FS = 1 << SegOvrShift,
447 GS = 2 << SegOvrShift,
448
449 // Execution domain for SSE instructions in bits 23, 24.
450 // 0 in bits 23-24 means normal, non-SSE instruction.
451 SSEDomainShift = SegOvrShift + 2,
452
453 OpcodeShift = SSEDomainShift + 2,
454
455 //===------------------------------------------------------------------===//
456 /// VEX - The opcode prefix used by AVX instructions
457 VEXShift = OpcodeShift + 8,
458 VEX = 1U << 0,
459
460 /// VEX_W - Has a opcode specific functionality, but is used in the same
461 /// way as REX_W is for regular SSE instructions.
462 VEX_W = 1U << 1,
463
464 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
465 /// address instructions in SSE are represented as 3 address ones in AVX
466 /// and the additional register is encoded in VEX_VVVV prefix.
467 VEX_4V = 1U << 2,
468
469 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
470 /// must be encoded in the i8 immediate field. This usually happens in
471 /// instructions with 4 operands.
472 VEX_I8IMM = 1U << 3,
473
474 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
475 /// instruction uses 256-bit wide registers. This is usually auto detected
476 /// if a VR256 register is used, but some AVX instructions also have this
477 /// field marked when using a f256 memory references.
478 VEX_L = 1U << 4,
479
480 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
481 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
482 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
483 /// storing a classifier in the imm8 field. To simplify our implementation,
484 /// we handle this by storeing the classifier in the opcode field and using
485 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
486 Has3DNow0F0FOpcode = 1U << 5
487 };
488
489 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
490 // specified machine instruction.
491 //
492 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
493 return TSFlags >> X86II::OpcodeShift;
494 }
495
496 static inline bool hasImm(uint64_t TSFlags) {
497 return (TSFlags & X86II::ImmMask) != 0;
498 }
499
500 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
501 /// of the specified instruction.
502 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
503 switch (TSFlags & X86II::ImmMask) {
504 default: assert(0 && "Unknown immediate size");
505 case X86II::Imm8:
506 case X86II::Imm8PCRel: return 1;
507 case X86II::Imm16:
508 case X86II::Imm16PCRel: return 2;
509 case X86II::Imm32:
510 case X86II::Imm32PCRel: return 4;
511 case X86II::Imm64: return 8;
512 }
513 }
514
515 /// isImmPCRel - Return true if the immediate of the specified instruction's
516 /// TSFlags indicates that it is pc relative.
517 static inline unsigned isImmPCRel(uint64_t TSFlags) {
518 switch (TSFlags & X86II::ImmMask) {
519 default: assert(0 && "Unknown immediate size");
520 case X86II::Imm8PCRel:
521 case X86II::Imm16PCRel:
522 case X86II::Imm32PCRel:
523 return true;
524 case X86II::Imm8:
525 case X86II::Imm16:
526 case X86II::Imm32:
527 case X86II::Imm64:
528 return false;
529 }
530 }
531
532 /// getMemoryOperandNo - The function returns the MCInst operand # for the
533 /// first field of the memory operand. If the instruction doesn't have a
534 /// memory operand, this returns -1.
535 ///
536 /// Note that this ignores tied operands. If there is a tied register which
537 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
538 /// counted as one operand.
539 ///
540 static inline int getMemoryOperandNo(uint64_t TSFlags) {
541 switch (TSFlags & X86II::FormMask) {
542 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
543 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
544 case X86II::Pseudo:
545 case X86II::RawFrm:
546 case X86II::AddRegFrm:
547 case X86II::MRMDestReg:
548 case X86II::MRMSrcReg:
549 case X86II::RawFrmImm8:
550 case X86II::RawFrmImm16:
551 return -1;
552 case X86II::MRMDestMem:
553 return 0;
554 case X86II::MRMSrcMem: {
555 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
556 unsigned FirstMemOp = 1;
557 if (HasVEX_4V)
558 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
559
560 // FIXME: Maybe lea should have its own form? This is a horrible hack.
561 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
562 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
563 return FirstMemOp;
564 }
565 case X86II::MRM0r: case X86II::MRM1r:
566 case X86II::MRM2r: case X86II::MRM3r:
567 case X86II::MRM4r: case X86II::MRM5r:
568 case X86II::MRM6r: case X86II::MRM7r:
569 return -1;
570 case X86II::MRM0m: case X86II::MRM1m:
571 case X86II::MRM2m: case X86II::MRM3m:
572 case X86II::MRM4m: case X86II::MRM5m:
573 case X86II::MRM6m: case X86II::MRM7m:
574 return 0;
575 case X86II::MRM_C1:
576 case X86II::MRM_C2:
577 case X86II::MRM_C3:
578 case X86II::MRM_C4:
579 case X86II::MRM_C8:
580 case X86II::MRM_C9:
581 case X86II::MRM_E8:
582 case X86II::MRM_F0:
583 case X86II::MRM_F8:
584 case X86II::MRM_F9:
585 case X86II::MRM_D0:
586 case X86II::MRM_D1:
587 return -1;
588 }
58999 }
590100 }
591101
828338 /// instruction that defines the specified register class.
829339 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
830340
831 static bool isX86_64NonExtLowByteReg(unsigned reg) {
832 return (reg == X86::SPL || reg == X86::BPL ||
833 reg == X86::SIL || reg == X86::DIL);
834 }
835
836341 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
837342 if (!MO.isReg()) return false;
838 return isX86_64ExtendedReg(MO.getReg());
343 return X86II::isX86_64ExtendedReg(MO.getReg());
839344 }
840
841 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
842 /// higher) register? e.g. r8, xmm8, xmm13, etc.
843 static bool isX86_64ExtendedReg(unsigned RegNo);
844345
845346 /// getGlobalBaseReg - Return a virtual register initialized with the
846347 /// the global base register value. Output instructions required to
1111 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "mccodeemitter"
14 #include "X86.h"
15 #include "X86InstrInfo.h"
16 #include "X86FixupKinds.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86FixupKinds.h"
1717 #include "llvm/MC/MCCodeEmitter.h"
1818 #include "llvm/MC/MCExpr.h"
1919 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
2022 #include "llvm/MC/MCSubtargetInfo.h"
2123 #include "llvm/MC/MCSymbol.h"
2224 #include "llvm/Support/raw_ostream.h"
152154 return MCFixup::getKindForSize(Size, isPCRel);
153155 }
154156
157 namespace llvm {
158 // FIXME: TableGen this?
159 extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc.
160 }
161
155162 /// Is32BitMemOperand - Return true if the specified instruction with a memory
156163 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
157164 /// memory operand. Op specifies the operand # of the memoperand.
159166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
160167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
161168
162 if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) ||
163 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
171 (IndexReg.getReg() != 0 &&
172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
164173 return true;
165174 return false;
166175 }
505514 case X86II::MRMSrcMem:
506515 case X86II::MRMSrcReg:
507516 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
508 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
517 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
509518 VEX_R = 0x0;
510519 CurOp++;
511520
526535
527536 for (; CurOp != NumOps; ++CurOp) {
528537 const MCOperand &MO = MI.getOperand(CurOp);
529 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
538 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
530539 VEX_B = 0x0;
531540 if (!VEX_B && MO.isReg() &&
532541 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
533 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
542 X86II::isX86_64ExtendedReg(MO.getReg()))
534543 VEX_X = 0x0;
535544 }
536545 break;
539548 break;
540549
541550 if (MI.getOperand(CurOp).isReg() &&
542 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
551 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
543552 VEX_B = 0;
544553
545554 if (HasVEX_4V)
549558 for (; CurOp != NumOps; ++CurOp) {
550559 const MCOperand &MO = MI.getOperand(CurOp);
551560 if (MO.isReg() && !HasVEX_4V &&
552 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
561 X86II::isX86_64ExtendedReg(MO.getReg()))
553562 VEX_R = 0x0;
554563 }
555564 break;
605614 const MCOperand &MO = MI.getOperand(i);
606615 if (!MO.isReg()) continue;
607616 unsigned Reg = MO.getReg();
608 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
617 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
609618 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
610619 // that returns non-zero.
611620 REX |= 0x40; // REX fixed encoding prefix
616625 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
617626 case X86II::MRMSrcReg:
618627 if (MI.getOperand(0).isReg() &&
619 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
628 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
620629 REX |= 1 << 2; // set REX.R
621630 i = isTwoAddr ? 2 : 1;
622631 for (; i != NumOps; ++i) {
623632 const MCOperand &MO = MI.getOperand(i);
624 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
633 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
625634 REX |= 1 << 0; // set REX.B
626635 }
627636 break;
628637 case X86II::MRMSrcMem: {
629638 if (MI.getOperand(0).isReg() &&
630 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
639 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
631640 REX |= 1 << 2; // set REX.R
632641 unsigned Bit = 0;
633642 i = isTwoAddr ? 2 : 1;
634643 for (; i != NumOps; ++i) {
635644 const MCOperand &MO = MI.getOperand(i);
636645 if (MO.isReg()) {
637 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
646 if (X86II::isX86_64ExtendedReg(MO.getReg()))
638647 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
639648 Bit++;
640649 }
649658 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
650659 i = isTwoAddr ? 1 : 0;
651660 if (NumOps > e && MI.getOperand(e).isReg() &&
652 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
661 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
653662 REX |= 1 << 2; // set REX.R
654663 unsigned Bit = 0;
655664 for (; i != e; ++i) {
656665 const MCOperand &MO = MI.getOperand(i);
657666 if (MO.isReg()) {
658 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
667 if (X86II::isX86_64ExtendedReg(MO.getReg()))
659668 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
660669 Bit++;
661670 }
664673 }
665674 default:
666675 if (MI.getOperand(0).isReg() &&
667 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
676 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
668677 REX |= 1 << 0; // set REX.B
669678 i = isTwoAddr ? 2 : 1;
670679 for (unsigned e = NumOps; i != e; ++i) {
671680 const MCOperand &MO = MI.getOperand(i);
672 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
681 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
673682 REX |= 1 << 2; // set REX.R
674683 }
675684 break;
10081017 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
10091018 const MCOperand &MO = MI.getOperand(CurOp++);
10101019 bool IsExtReg =
1011 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
1020 X86II::isX86_64ExtendedReg(MO.getReg());
10121021 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
10131022 RegNum |= GetX86RegNum(MO) << 4;
10141023 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
77 //===----------------------------------------------------------------------===//
88
99 #include "X86.h"
10 #include "X86FixupKinds.h"
10 #include "MCTargetDesc/X86FixupKinds.h"
1111 #include "llvm/ADT/Twine.h"
1212 #include "llvm/MC/MCAssembler.h"
1313 #include "llvm/MC/MCAsmLayout.h"