llvm.org GIT mirror llvm / 8c3d5ad
Merging r226596: ------------------------------------------------------------------------ r226596 | thomas.stellard | 2015-01-20 14:33:02 -0500 (Tue, 20 Jan 2015) | 2 lines R600/SI: Fix simple-loop.ll test ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@226727 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
3 changed file(s) with 9 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
9898 ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
9999 BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
100100 .addReg(ScratchOffsetPreloadReg)
101 .addFrameIndex(ScratchOffsetFI);
101 .addFrameIndex(ScratchOffsetFI)
102 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
103 .addReg(AMDGPU::SGPR0, RegState::Undef);
102104 }
103105
104106
115117 MachineBasicBlock &MBB = *BI;
116118 // Add the scratch offset reg as a live-in so that the register scavenger
117119 // doesn't re-use it.
118 if (!MBB.isLiveIn(ScratchOffsetReg))
120 if (!MBB.isLiveIn(ScratchOffsetReg) &&
121 ScratchOffsetReg != AMDGPU::NoRegister)
119122 MBB.addLiveIn(ScratchOffsetReg);
120123 RS.enterBasicBlock(&MBB);
121124
172175 BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
173176 ScratchOffsetReg)
174177 .addFrameIndex(ScratchOffsetFI)
175 .addReg(AMDGPU::NoRegister)
176 .addReg(AMDGPU::NoRegister);
178 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
179 .addReg(AMDGPU::SGPR0, RegState::Undef);
177180 } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
178181 MBB.addLiveIn(ScratchOffsetReg);
179182 }
190193 MI.getOperand(2).setIsUndef(false);
191194 MI.getOperand(3).setReg(ScratchOffsetReg);
192195 MI.getOperand(3).setIsUndef(false);
196 MI.getOperand(3).setIsKill(false);
193197 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
194198 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
195199 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
141141 .addReg(SubReg, getDefRegState(IsLoad))
142142 .addReg(ScratchRsrcReg, getKillRegState(IsKill))
143143 .addImm(Offset)
144 .addReg(SOffset, getKillRegState(IsKill))
144 .addReg(SOffset)
145145 .addImm(0) // glc
146146 .addImm(0) // slc
147147 .addImm(0) // tfe
None ; XFAIL: *
1 ; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
21
32 ; CHECK-LABEL: {{^}}test_loop: