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[X86] Don't randomly encode %rip where illegal Differential Revision: https://reviews.llvm.org/D25112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283326 91177308-0d34-0410-b5e6-96231b3b80d8 Douglas Katzman 4 years ago
4 changed file(s) with 40 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
839839 // If we have both a base register and an index register make sure they are
840840 // both 64-bit or 32-bit registers.
841841 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
842
843 if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
844 ErrMsg = "invalid base+index expression";
845 return true;
846 }
842847 if (BaseReg != 0 && IndexReg != 0) {
843848 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
844849 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
17801785 !ParseRegister(RegNo, Start, End)) {
17811786 // If this is a segment register followed by a ':', then this is the start
17821787 // of a segment override, otherwise this is a normal register reference.
1783 // In case it is a normal register and there is ptr in the operand this
1788 // In case it is a normal register and there is ptr in the operand this
17841789 // is an error
1785 if (getLexer().isNot(AsmToken::Colon)){
1786 if (PtrInOperand){
1790 if (RegNo == X86::RIP)
1791 return ErrorOperand(Start, "rip can only be used as a base register");
1792 if (getLexer().isNot(AsmToken::Colon)) {
1793 if (PtrInOperand) {
17871794 return ErrorOperand(Start, "expected memory operand after "
17881795 "'ptr', found register operand instead");
17891796 }
18611868 if (ParseRegister(RegNo, Start, End)) return nullptr;
18621869 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
18631870 Error(Start, "%eiz and %riz can only be used as index registers",
1871 SMRange(Start, End));
1872 return nullptr;
1873 }
1874 if (RegNo == X86::RIP) {
1875 Error(Start, "%rip can only be used as a base register",
18641876 SMRange(Start, End));
18651877 return nullptr;
18661878 }
20432055 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
20442056 if (getLexer().is(AsmToken::Percent)) {
20452057 SMLoc L;
2046 if (ParseRegister(IndexReg, L, L)) return nullptr;
2058 if (ParseRegister(IndexReg, L, L))
2059 return nullptr;
2060 if (BaseReg == X86::RIP) {
2061 Error(IndexLoc, "%rip as base register can not have an index register");
2062 return nullptr;
2063 }
2064 if (IndexReg == X86::RIP) {
2065 Error(IndexLoc, "%rip is not allowed as an index register");
2066 return nullptr;
2067 }
20472068
20482069 if (getLexer().isNot(AsmToken::RParen)) {
20492070 // Parse the scale amount:
344344 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
345345 // RIP isn't really a register and it can't be used anywhere except in an
346346 // address, but it doesn't cause trouble.
347 // FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
348 // tests because of the inclusion of RIP in this register class.
347349 def GR64 : RegisterClass<"X86", [i64], 64,
348350 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
349351 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
2323 mov eax, DWORD PTR arr[esi*4]
2424 //CHECK: error: cannot use more than one symbol in memory operand
2525 mov eax, DWORD PTR arr[i]
26 //CHECK: error: rip can only be used as a base register
27 .code64
28 mov rax, rip
29 //CHECK: error: invalid base+index expression
30 mov rbx, [rax+rip]
7373
7474 // 32: error: register %dr8 is only available in 64-bit mode
7575 movl %edx, %dr8
76
77 // 32: error: register %rip is only available in 64-bit mode
78 // 64: error: %rip can only be used as a base register
79 mov %rip, %rax
80
81 // 32: error: register %rax is only available in 64-bit mode
82 // 64: error: %rip is not allowed as an index register
83 mov (%rax,%rip), %rbx