llvm.org GIT mirror llvm / 8ba165a
DAGCombiner: Turn extract of bitcasted integer into truncate This reduces the number of bitcast nodes and generally cleans up the DAG when bitcasting between integers and vectors everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262358 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
3 changed file(s) with 37 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
1217912179 // converts.
1218012180 }
1218112181
12182 // extract_vector_elt (v2i32 (bitcast i64:x)), 0 -> i32 (trunc i64:x)
12183 if (ConstEltNo && InVec.getOpcode() == ISD::BITCAST && InVec.hasOneUse() &&
12184 ConstEltNo->isNullValue()) {
12185 SDValue BCSrc = InVec.getOperand(0);
12186 if (BCSrc.getValueType().isScalarInteger())
12187 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, BCSrc);
12188 }
12189
1218212190 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
1218312191 // We only perform this optimization before the op legalization phase because
1218412192 // we may introduce new vector instructions which are not backed by TD
2484924849 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
2485024850 N->getValueType(0) == MVT::i32 &&
2485124851 InputVector.getValueType() == MVT::v2i32) {
24852
24853 // The bitcast source is a direct mmx result.
2485424852 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
24855 if (MMXSrc.getValueType() == MVT::x86mmx)
24856 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
24857 N->getValueType(0),
24858 InputVector.getNode()->getOperand(0));
2485924853
2486024854 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
2486124855 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
2793927933
2794027934 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
2794127935 const X86Subtarget &Subtarget) {
27936
27937 SDValue Src = N->getOperand(0);
27938
2794227939 // Try to detect AVG pattern first.
27943 if (SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
27940 if (SDValue Avg = detectAVGPattern(Src, N->getValueType(0), DAG,
2794427941 Subtarget, SDLoc(N)))
2794527942 return Avg;
27943
27944 // The bitcast source is a direct mmx result.
27945 // Detect bitcasts between i32 to x86mmx
27946 if (Src.getOpcode() == ISD::BITCAST && N->getValueType(0) == MVT::i32) {
27947 SDValue BCSrc = Src.getOperand(0);
27948 if (BCSrc.getValueType() == MVT::x86mmx)
27949 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(N), MVT::i32, BCSrc);
27950 }
2794627951
2794727952 return combineVectorTruncation(N, DAG, Subtarget);
2794827953 }
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
1
2 ; Make sure the add and load are reduced to 32-bits even with the
3 ; bitcast to vector.
4 ; GCN-LABEL: {{^}}bitcast_int_to_vector_extract_0:
5 ; GCN-DAG: s_load_dword [[B:s[0-9]+]]
6 ; GCN-DAG: buffer_load_dword [[A:v[0-9]+]]
7 ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, [[B]], [[A]]
8 ; GCN: buffer_store_dword [[ADD]]
9 define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) {
10 %a = load i64, i64 addrspace(1)* %in
11 %add = add i64 %a, %b
12 %val.bc = bitcast i64 %add to <2 x i32>
13 %extract = extractelement <2 x i32> %val.bc, i32 0
14 store i32 %extract, i32 addrspace(1)* %out
15 ret void
16 }