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[SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently. This is largely a mechanical transformation from KnownZero to Known.Zero. Differential Revision: https://reviews.llvm.org/D32569 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301620 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
31 changed file(s) with 701 addition(s) and 771 deletion(s). Raw diff Collapse all Expand all
2424 #include "llvm/CodeGen/MachineBasicBlock.h"
2525 #include "llvm/IR/InlineAsm.h"
2626 #include "llvm/IR/Instructions.h"
27 #include "llvm/Support/KnownBits.h"
2728 #include "llvm/Target/TargetRegisterInfo.h"
2829 #include
2930
170171 struct LiveOutInfo {
171172 unsigned NumSignBits : 31;
172173 unsigned IsValid : 1;
173 APInt KnownOne, KnownZero;
174 LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
175 KnownZero(1, 0) {}
174 KnownBits Known;
175 LiveOutInfo() : NumSignBits(0), IsValid(true), Known(1) {}
176176 };
177177
178178 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
246246
247247 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
248248 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
249 const APInt &KnownZero, const APInt &KnownOne) {
249 const KnownBits &Known) {
250250 // Only install this information if it tells us something.
251 if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
251 if (NumSignBits == 1 && Known.Zero == 0 && Known.One == 0)
252252 return;
253253
254254 LiveOutRegInfo.grow(Reg);
255255 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
256256 LOI.NumSignBits = NumSignBits;
257 LOI.KnownOne = KnownOne;
258 LOI.KnownZero = KnownZero;
257 LOI.Known.One = Known.One;
258 LOI.Known.Zero = Known.Zero;
259259 }
260260
261261 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
3232
3333 namespace llvm {
3434
35 struct KnownBits;
3536 class MachineConstantPoolValue;
3637 class MachineFunction;
3738 class MDNode;
12821283 const;
12831284
12841285 /// Determine which bits of Op are known to be either zero or one and return
1285 /// them in the KnownZero/KnownOne bitsets. For vectors, the known bits are
1286 /// those that are shared by every vector element.
1286 /// them in Known. For vectors, the known bits are those that are shared by
1287 /// every vector element.
12871288 /// Targets can implement the computeKnownBitsForTargetNode method in the
12881289 /// TargetLowering class to allow target nodes to be understood.
1289 void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne,
1290 unsigned Depth = 0) const;
1290 void computeKnownBits(SDValue Op, KnownBits &Known, unsigned Depth = 0) const;
12911291
12921292 /// Determine which bits of Op are known to be either zero or one and return
1293 /// them in the KnownZero/KnownOne bitsets. The DemandedElts argument allows
1294 /// us to only collect the known bits that are shared by the requested vector
1295 /// elements.
1293 /// them in Known. The DemandedElts argument allows us to only collect the
1294 /// known bits that are shared by the requested vector elements.
12961295 /// Targets can implement the computeKnownBitsForTargetNode method in the
12971296 /// TargetLowering class to allow target nodes to be understood.
1298 void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne,
1299 const APInt &DemandedElts, unsigned Depth = 0) const;
1297 void computeKnownBits(SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1298 unsigned Depth = 0) const;
13001299
13011300 /// Used to represent the possible overflow behavior of an operation.
13021301 /// Never: the operation cannot overflow.
6868 class FastISel;
6969 class FunctionLoweringInfo;
7070 class IntrinsicInst;
71 struct KnownBits;
7172 class MachineBasicBlock;
7273 class MachineFunction;
7374 class MachineInstr;
24412442 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
24422443 /// has multiple uses.
24432444 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2444 APInt &KnownZero, APInt &KnownOne,
2445 KnownBits &Known,
24452446 TargetLoweringOpt &TLO,
24462447 unsigned Depth = 0,
24472448 bool AssumeSingleUse = false) const;
24552456 /// argument allows us to only collect the known bits that are shared by the
24562457 /// requested vector elements.
24572458 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2458 APInt &KnownZero,
2459 APInt &KnownOne,
2459 KnownBits &Known,
24602460 const APInt &DemandedElts,
24612461 const SelectionDAG &DAG,
24622462 unsigned Depth = 0) const;
3232 #include "llvm/Support/CommandLine.h"
3333 #include "llvm/Support/Debug.h"
3434 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/KnownBits.h"
3536 #include "llvm/Support/MathExtras.h"
3637 #include "llvm/Support/raw_ostream.h"
3738 #include "llvm/Target/TargetLowering.h"
964965 /// things it uses can be simplified by bit propagation. If so, return true.
965966 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
966967 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
967 APInt KnownZero, KnownOne;
968 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
968 KnownBits Known;
969 if (!TLI.SimplifyDemandedBits(Op, Demanded, Known, TLO))
969970 return false;
970971
971972 // Revisit the node.
56965697 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
56975698 if (N1C && N0.getOpcode() == ISD::CTLZ &&
56985699 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
5699 APInt KnownZero, KnownOne;
5700 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
5700 KnownBits Known;
5701 DAG.computeKnownBits(N0.getOperand(0), Known);
57015702
57025703 // If any of the input bits are KnownOne, then the input couldn't be all
57035704 // zeros, thus the result of the srl will always be zero.
5704 if (KnownOne.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
5705 if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
57055706
57065707 // If all of the bits input the to ctlz node are known to be zero, then
57075708 // the result of the ctlz is "32" and the result of the shift is one.
5708 APInt UnknownBits = ~KnownZero;
5709 APInt UnknownBits = ~Known.Zero;
57095710 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
57105711
57115712 // Otherwise, check to see if there is exactly one bit input to the ctlz.
71327133 }
71337134
71347135 // isTruncateOf - If N is a truncate of some other value, return true, record
7135 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
7136 // This function computes KnownZero to avoid a duplicated call to
7136 // the value being truncated in Op and which of Op's bits are zero/one in Known.
7137 // This function computes KnownBits to avoid a duplicated call to
71377138 // computeKnownBits in the caller.
71387139 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
7139 APInt &KnownZero) {
7140 APInt KnownOne;
7140 KnownBits &Known) {
71417141 if (N->getOpcode() == ISD::TRUNCATE) {
71427142 Op = N->getOperand(0);
7143 DAG.computeKnownBits(Op, KnownZero, KnownOne);
7143 DAG.computeKnownBits(Op, Known);
71447144 return true;
71457145 }
71467146
71597159 else
71607160 return false;
71617161
7162 DAG.computeKnownBits(Op, KnownZero, KnownOne);
7163
7164 if (!(KnownZero | 1).isAllOnesValue())
7162 DAG.computeKnownBits(Op, Known);
7163
7164 if (!(Known.Zero | 1).isAllOnesValue())
71657165 return false;
71667166
71677167 return true;
71867186 // This is valid when the truncated bits of x are already zero.
71877187 // FIXME: We should extend this to work for vectors too.
71887188 SDValue Op;
7189 APInt KnownZero;
7190 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
7189 KnownBits Known;
7190 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, Known)) {
71917191 APInt TruncatedBits =
71927192 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
71937193 APInt(Op.getValueSizeInBits(), 0) :
71957195 N0.getValueSizeInBits(),
71967196 std::min(Op.getValueSizeInBits(),
71977197 VT.getSizeInBits()));
7198 if (TruncatedBits.isSubsetOf(KnownZero)) {
7198 if (TruncatedBits.isSubsetOf(Known.Zero)) {
71997199 if (VT.bitsGT(Op.getValueType()))
72007200 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
72017201 if (VT.bitsLT(Op.getValueType()))
399399 if (!LOI->IsValid)
400400 return nullptr;
401401
402 if (BitWidth > LOI->KnownZero.getBitWidth()) {
402 if (BitWidth > LOI->Known.getBitWidth()) {
403403 LOI->NumSignBits = 1;
404 LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
405 LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
404 LOI->Known.Zero = LOI->Known.Zero.zextOrTrunc(BitWidth);
405 LOI->Known.One = LOI->Known.One.zextOrTrunc(BitWidth);
406406 }
407407
408408 return LOI;
435435 Value *V = PN->getIncomingValue(0);
436436 if (isa(V) || isa(V)) {
437437 DestLOI.NumSignBits = 1;
438 APInt Zero(BitWidth, 0);
439 DestLOI.KnownZero = Zero;
440 DestLOI.KnownOne = Zero;
438 DestLOI.Known = KnownBits(BitWidth);
441439 return;
442440 }
443441
444442 if (ConstantInt *CI = dyn_cast(V)) {
445443 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
446444 DestLOI.NumSignBits = Val.getNumSignBits();
447 DestLOI.KnownZero = ~Val;
448 DestLOI.KnownOne = Val;
445 DestLOI.Known.Zero = ~Val;
446 DestLOI.Known.One = Val;
449447 } else {
450448 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
451449 "CopyToReg node was created.");
462460 DestLOI = *SrcLOI;
463461 }
464462
465 assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
466 DestLOI.KnownOne.getBitWidth() == BitWidth &&
463 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
464 DestLOI.Known.One.getBitWidth() == BitWidth &&
467465 "Masks should have the same bit width as the type.");
468466
469467 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
470468 Value *V = PN->getIncomingValue(i);
471469 if (isa(V) || isa(V)) {
472470 DestLOI.NumSignBits = 1;
473 APInt Zero(BitWidth, 0);
474 DestLOI.KnownZero = Zero;
475 DestLOI.KnownOne = Zero;
471 DestLOI.Known = KnownBits(BitWidth);
476472 return;
477473 }
478474
479475 if (ConstantInt *CI = dyn_cast(V)) {
480476 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
481477 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
482 DestLOI.KnownZero &= ~Val;
483 DestLOI.KnownOne &= Val;
478 DestLOI.Known.Zero &= ~Val;
479 DestLOI.Known.One &= Val;
484480 continue;
485481 }
486482
497493 return;
498494 }
499495 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
500 DestLOI.KnownZero &= SrcLOI->KnownZero;
501 DestLOI.KnownOne &= SrcLOI->KnownOne;
496 DestLOI.Known.Zero &= SrcLOI->Known.Zero;
497 DestLOI.Known.One &= SrcLOI->Known.One;
502498 }
503499 }
504500
2020 #include "LegalizeTypes.h"
2121 #include "llvm/IR/DerivedTypes.h"
2222 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/KnownBits.h"
2324 #include "llvm/Support/raw_ostream.h"
2425 using namespace llvm;
2526
15241525 SDLoc dl(N);
15251526
15261527 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1527 APInt KnownZero, KnownOne;
1528 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1528 KnownBits Known;
1529 DAG.computeKnownBits(N->getOperand(1), Known);
15291530
15301531 // If we don't know anything about the high bits, exit.
1531 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1532 if (((Known.Zero|Known.One) & HighBitMask) == 0)
15321533 return false;
15331534
15341535 // Get the incoming operand to be shifted.
15371538
15381539 // If we know that any of the high bits of the shift amount are one, then we
15391540 // can do this as a couple of simple shifts.
1540 if (KnownOne.intersects(HighBitMask)) {
1541 if (Known.One.intersects(HighBitMask)) {
15411542 // Mask out the high bit, which we know is set.
15421543 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
15431544 DAG.getConstant(~HighBitMask, dl, ShTy));
15621563
15631564 // If we know that all of the high bits of the shift amount are zero, then we
15641565 // can do this as a couple of simple shifts.
1565 if (HighBitMask.isSubsetOf(KnownZero)) {
1566 if (HighBitMask.isSubsetOf(Known.Zero)) {
15661567 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
15671568 // shift if x is zero. We can use XOR here because x is known to be smaller
15681569 // than 32.
19661966 /// for bits that V cannot have.
19671967 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
19681968 unsigned Depth) const {
1969 APInt KnownZero, KnownOne;
1970 computeKnownBits(Op, KnownZero, KnownOne, Depth);
1971 return Mask.isSubsetOf(KnownZero);
1969 KnownBits Known;
1970 computeKnownBits(Op, Known, Depth);
1971 return Mask.isSubsetOf(Known.Zero);
19721972 }
19731973
19741974 /// If a SHL/SRA/SRL node has a constant or splat constant shift amount that
19841984 }
19851985
19861986 /// Determine which bits of Op are known to be either zero or one and return
1987 /// them in the KnownZero/KnownOne bitsets. For vectors, the known bits are
1988 /// those that are shared by every vector element.
1989 void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
1990 APInt &KnownOne, unsigned Depth) const {
1987 /// them in Known. For vectors, the known bits are those that are shared by
1988 /// every vector element.
1989 void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
1990 unsigned Depth) const {
19911991 EVT VT = Op.getValueType();
19921992 APInt DemandedElts = VT.isVector()
19931993 ? APInt::getAllOnesValue(VT.getVectorNumElements())
19941994 : APInt(1, 1);
1995 computeKnownBits(Op, KnownZero, KnownOne, DemandedElts, Depth);
1995 computeKnownBits(Op, Known, DemandedElts, Depth);
19961996 }
19971997
19981998 /// Determine which bits of Op are known to be either zero or one and return
1999 /// them in the KnownZero/KnownOne bitsets. The DemandedElts argument allows
2000 /// us to only collect the known bits that are shared by the requested vector
2001 /// elements.
2002 void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
2003 APInt &KnownOne, const APInt &DemandedElts,
1999 /// them in Known. The DemandedElts argument allows us to only collect the known
2000 /// bits that are shared by the requested vector elements.
2001 void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
2002 const APInt &DemandedElts,
20042003 unsigned Depth) const {
20052004 unsigned BitWidth = Op.getScalarValueSizeInBits();
20062005
2007 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
2006 Known = KnownBits(BitWidth); // Don't know anything.
20082007 if (Depth == 6)
20092008 return; // Limit search depth.
20102009
2011 APInt KnownZero2, KnownOne2;
2010 KnownBits Known2;
20122011 unsigned NumElts = DemandedElts.getBitWidth();
20132012
20142013 if (!DemandedElts)
20182017 switch (Opcode) {
20192018 case ISD::Constant:
20202019 // We know all of the bits for a constant!
2021 KnownOne = cast(Op)->getAPIntValue();
2022 KnownZero = ~KnownOne;
2020 Known.One = cast(Op)->getAPIntValue();
2021 Known.Zero = ~Known.One;
20232022 break;
20242023 case ISD::BUILD_VECTOR:
20252024 // Collect the known bits that are shared by every demanded vector element.
20262025 assert(NumElts == Op.getValueType().getVectorNumElements() &&
20272026 "Unexpected vector size");
2028 KnownZero.setAllBits(); KnownOne.setAllBits();
2027 Known.Zero.setAllBits(); Known.One.setAllBits();
20292028 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
20302029 if (!DemandedElts[i])
20312030 continue;
20322031
20332032 SDValue SrcOp = Op.getOperand(i);
2034 computeKnownBits(SrcOp, KnownZero2, KnownOne2, Depth + 1);
2033 computeKnownBits(SrcOp, Known2, Depth + 1);
20352034
20362035 // BUILD_VECTOR can implicitly truncate sources, we must handle this.
20372036 if (SrcOp.getValueSizeInBits() != BitWidth) {
20382037 assert(SrcOp.getValueSizeInBits() > BitWidth &&
20392038 "Expected BUILD_VECTOR implicit truncation");
2040 KnownOne2 = KnownOne2.trunc(BitWidth);
2041 KnownZero2 = KnownZero2.trunc(BitWidth);
2039 Known2.One = Known2.One.trunc(BitWidth);
2040 Known2.Zero = Known2.Zero.trunc(BitWidth);
20422041 }
20432042
20442043 // Known bits are the values that are shared by every demanded element.
2045 KnownOne &= KnownOne2;
2046 KnownZero &= KnownZero2;
2044 Known.One &= Known2.One;
2045 Known.Zero &= Known2.Zero;
20472046
20482047 // If we don't know any bits, early out.
2049 if (!KnownOne && !KnownZero)
2048 if (!Known.One && !Known.Zero)
20502049 break;
20512050 }
20522051 break;
20542053 // Collect the known bits that are shared by every vector element referenced
20552054 // by the shuffle.
20562055 APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0);
2057 KnownZero.setAllBits(); KnownOne.setAllBits();
2056 Known.Zero.setAllBits(); Known.One.setAllBits();
20582057 const ShuffleVectorSDNode *SVN = cast(Op);
20592058 assert(NumElts == SVN->getMask().size() && "Unexpected vector size");
20602059 for (unsigned i = 0; i != NumElts; ++i) {
20652064 if (M < 0) {
20662065 // For UNDEF elements, we don't know anything about the common state of
20672066 // the shuffle result.
2068 KnownOne.clearAllBits();
2069 KnownZero.clearAllBits();
2067 Known.One.clearAllBits();
2068 Known.Zero.clearAllBits();
20702069 DemandedLHS.clearAllBits();
20712070 DemandedRHS.clearAllBits();
20722071 break;
20802079 // Known bits are the values that are shared by every demanded element.
20812080 if (!!DemandedLHS) {
20822081 SDValue LHS = Op.getOperand(0);
2083 computeKnownBits(LHS, KnownZero2, KnownOne2, DemandedLHS, Depth + 1);
2084 KnownOne &= KnownOne2;
2085 KnownZero &= KnownZero2;
2082 computeKnownBits(LHS, Known2, DemandedLHS, Depth + 1);
2083 Known.One &= Known2.One;
2084 Known.Zero &= Known2.Zero;
20862085 }
20872086 // If we don't know any bits, early out.
2088 if (!KnownOne && !KnownZero)
2087 if (!Known.One && !Known.Zero)
20892088 break;
20902089 if (!!DemandedRHS) {
20912090 SDValue RHS = Op.getOperand(1);
2092 computeKnownBits(RHS, KnownZero2, KnownOne2, DemandedRHS, Depth + 1);
2093 KnownOne &= KnownOne2;
2094 KnownZero &= KnownZero2;
2091 computeKnownBits(RHS, Known2, DemandedRHS, Depth + 1);
2092 Known.One &= Known2.One;
2093 Known.Zero &= Known2.Zero;
20952094 }
20962095 break;
20972096 }
20982097 case ISD::CONCAT_VECTORS: {
20992098 // Split DemandedElts and test each of the demanded subvectors.
2100 KnownZero.setAllBits(); KnownOne.setAllBits();
2099 Known.Zero.setAllBits(); Known.One.setAllBits();
21012100 EVT SubVectorVT = Op.getOperand(0).getValueType();
21022101 unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
21032102 unsigned NumSubVectors = Op.getNumOperands();
21062105 DemandedSub = DemandedSub.trunc(NumSubVectorElts);
21072106 if (!!DemandedSub) {
21082107 SDValue Sub = Op.getOperand(i);
2109 computeKnownBits(Sub, KnownZero2, KnownOne2, DemandedSub, Depth + 1);
2110 KnownOne &= KnownOne2;
2111 KnownZero &= KnownZero2;
2108 computeKnownBits(Sub, Known2, DemandedSub, Depth + 1);
2109 Known.One &= Known2.One;
2110 Known.Zero &= Known2.Zero;
21122111 }
21132112 // If we don't know any bits, early out.
2114 if (!KnownOne && !KnownZero)
2113 if (!Known.One && !Known.Zero)
21152114 break;
21162115 }
21172116 break;
21262125 // Offset the demanded elts by the subvector index.
21272126 uint64_t Idx = SubIdx->getZExtValue();
21282127 APInt DemandedSrc = DemandedElts.zext(NumSrcElts).shl(Idx);
2129 computeKnownBits(Src, KnownZero, KnownOne, DemandedSrc, Depth + 1);
2128 computeKnownBits(Src, Known, DemandedSrc, Depth + 1);
21302129 } else {
2131 computeKnownBits(Src, KnownZero, KnownOne, Depth + 1);
2130 computeKnownBits(Src, Known, Depth + 1);
21322131 }
21332132 break;
21342133 }
21422141
21432142 // Fast handling of 'identity' bitcasts.
21442143 if (BitWidth == SubBitWidth) {
2145 computeKnownBits(N0, KnownZero, KnownOne, DemandedElts, Depth + 1);
2144 computeKnownBits(N0, Known, DemandedElts, Depth + 1);
21462145 break;
21472146 }
21482147
21662165 SubDemandedElts.setBit(i * SubScale);
21672166
21682167 for (unsigned i = 0; i != SubScale; ++i) {
2169 computeKnownBits(N0, KnownZero2, KnownOne2, SubDemandedElts.shl(i),
2168 computeKnownBits(N0, Known2, SubDemandedElts.shl(i),
21702169 Depth + 1);
2171 KnownOne |= KnownOne2.zext(BitWidth).shl(SubBitWidth * i);
2172 KnownZero |= KnownZero2.zext(BitWidth).shl(SubBitWidth * i);
2170 Known.One |= Known2.One.zext(BitWidth).shl(SubBitWidth * i);
2171 Known.Zero |= Known2.Zero.zext(BitWidth).shl(SubBitWidth * i);
21732172 }
21742173 }
21752174
21862185 if (DemandedElts[i])
21872186 SubDemandedElts.setBit(i / SubScale);
21882187
2189 computeKnownBits(N0, KnownZero2, KnownOne2, SubDemandedElts, Depth + 1);
2190
2191 KnownZero.setAllBits(); KnownOne.setAllBits();
2188 computeKnownBits(N0, Known2, SubDemandedElts, Depth + 1);
2189
2190 Known.Zero.setAllBits(); Known.One.setAllBits();
21922191 for (unsigned i = 0; i != NumElts; ++i)
21932192 if (DemandedElts[i]) {
21942193 unsigned Offset = (i % SubScale) * BitWidth;
2195 KnownOne &= KnownOne2.lshr(Offset).trunc(BitWidth);
2196 KnownZero &= KnownZero2.lshr(Offset).trunc(BitWidth);
2194 Known.One &= Known2.One.lshr(Offset).trunc(BitWidth);
2195 Known.Zero &= Known2.Zero.lshr(Offset).trunc(BitWidth);
21972196 // If we don't know any bits, early out.
2198 if (!KnownOne && !KnownZero)
2197 if (!Known.One && !Known.Zero)
21992198 break;
22002199 }
22012200 }
22032202 }
22042203 case ISD::AND:
22052204 // If either the LHS or the RHS are Zero, the result is zero.
2206 computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts,
2207 Depth + 1);
2208 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2209 Depth + 1);
2205 computeKnownBits(Op.getOperand(1), Known, DemandedElts, Depth + 1);
2206 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
22102207
22112208 // Output known-1 bits are only known if set in both the LHS & RHS.
2212 KnownOne &= KnownOne2;
2209 Known.One &= Known2.One;
22132210 // Output known-0 are known to be clear if zero in either the LHS | RHS.
2214 KnownZero |= KnownZero2;
2211 Known.Zero |= Known2.Zero;
22152212 break;
22162213 case ISD::OR:
2217 computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts,
2218 Depth + 1);
2219 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2220 Depth + 1);
2214 computeKnownBits(Op.getOperand(1), Known, DemandedElts, Depth + 1);
2215 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
22212216
22222217 // Output known-0 bits are only known if clear in both the LHS & RHS.
2223 KnownZero &= KnownZero2;
2218 Known.Zero &= Known2.Zero;
22242219 // Output known-1 are known to be set if set in either the LHS | RHS.
2225 KnownOne |= KnownOne2;
2220 Known.One |= Known2.One;
22262221 break;
22272222 case ISD::XOR: {
2228 computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts,
2229 Depth + 1);
2230 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2231 Depth + 1);
2223 computeKnownBits(Op.getOperand(1), Known, DemandedElts, Depth + 1);
2224 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
22322225
22332226 // Output known-0 bits are known if clear or set in both the LHS & RHS.
2234 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
2227 APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
22352228 // Output known-1 are known to be set if set in only one of the LHS, RHS.
2236 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
2237 KnownZero = KnownZeroOut;
2229 Known.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
2230 Known.Zero = KnownZeroOut;
22382231 break;
22392232 }
22402233 case ISD::MUL: {
2241 computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts,
2242 Depth + 1);
2243 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2244 Depth + 1);
2234 computeKnownBits(Op.getOperand(1), Known, DemandedElts, Depth + 1);
2235 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
22452236
22462237 // If low bits are zero in either operand, output low known-0 bits.
22472238 // Also compute a conservative estimate for high known-0 bits.
22482239 // More trickiness is possible, but this is sufficient for the
22492240 // interesting case of alignment computation.
2250 KnownOne.clearAllBits();
2251 unsigned TrailZ = KnownZero.countTrailingOnes() +
2252 KnownZero2.countTrailingOnes();
2253 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() +
2254 KnownZero2.countLeadingOnes(),
2241 Known.One.clearAllBits();
2242 unsigned TrailZ = Known.Zero.countTrailingOnes() +
2243 Known2.Zero.countTrailingOnes();
2244 unsigned LeadZ = std::max(Known.Zero.countLeadingOnes() +
2245 Known2.Zero.countLeadingOnes(),
22552246 BitWidth) - BitWidth;
22562247
2257 KnownZero.clearAllBits();
2258 KnownZero.setLowBits(std::min(TrailZ, BitWidth));
2259 KnownZero.setHighBits(std::min(LeadZ, BitWidth));
2248 Known.Zero.clearAllBits();
2249 Known.Zero.setLowBits(std::min(TrailZ, BitWidth));
2250 Known.Zero.setHighBits(std::min(LeadZ, BitWidth));
22602251 break;
22612252 }
22622253 case ISD::UDIV: {
22632254 // For the purposes of computing leading zeros we can conservatively
22642255 // treat a udiv as a logical right shift by the power of 2 known to
22652256 // be less than the denominator.
2266 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2267 Depth + 1);
2268 unsigned LeadZ = KnownZero2.countLeadingOnes();
2269
2270 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2271 Depth + 1);
2272 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
2257 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
2258 unsigned LeadZ = Known2.Zero.countLeadingOnes();
2259
2260 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
2261 unsigned RHSUnknownLeadingOnes = Known2.One.countLeadingZeros();
22732262 if (RHSUnknownLeadingOnes != BitWidth)
22742263 LeadZ = std::min(BitWidth,
22752264 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
22762265
2277 KnownZero.setHighBits(LeadZ);
2266 Known.Zero.setHighBits(LeadZ);
22782267 break;
22792268 }
22802269 case ISD::SELECT:
2281 computeKnownBits(Op.getOperand(2), KnownZero, KnownOne, Depth+1);
2270 computeKnownBits(Op.getOperand(2), Known, Depth+1);
22822271 // If we don't know any bits, early out.
2283 if (!KnownOne && !KnownZero)
2272 if (!Known.One && !Known.Zero)
22842273 break;
2285 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
2274 computeKnownBits(Op.getOperand(1), Known2, Depth+1);
22862275
22872276 // Only known if known in both the LHS and RHS.
2288 KnownOne &= KnownOne2;
2289 KnownZero &= KnownZero2;
2277 Known.One &= Known2.One;
2278 Known.Zero &= Known2.Zero;
22902279 break;
22912280 case ISD::SELECT_CC:
2292 computeKnownBits(Op.getOperand(3), KnownZero, KnownOne, Depth+1);
2281 computeKnownBits(Op.getOperand(3), Known, Depth+1);
22932282 // If we don't know any bits, early out.
2294 if (!KnownOne && !KnownZero)
2283 if (!Known.One && !Known.Zero)
22952284 break;
2296 computeKnownBits(Op.getOperand(2), KnownZero2, KnownOne2, Depth+1);
2285 computeKnownBits(Op.getOperand(2), Known2, Depth+1);
22972286
22982287 // Only known if known in both the LHS and RHS.
2299 KnownOne &= KnownOne2;
2300 KnownZero &= KnownZero2;
2288 Known.One &= Known2.One;
2289 Known.Zero &= Known2.Zero;
23012290 break;
23022291 case ISD::SMULO:
23032292 case ISD::UMULO:
23102299 if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
23112300 TargetLowering::ZeroOrOneBooleanContent &&
23122301 BitWidth > 1)
2313 KnownZero.setBitsFrom(1);
2302 Known.Zero.setBitsFrom(1);
23142303 break;
23152304 case ISD::SETCC:
23162305 // If we know the result of a setcc has the top bits zero, use this info.
23172306 if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
23182307 TargetLowering::ZeroOrOneBooleanContent &&
23192308 BitWidth > 1)
2320 KnownZero.setBitsFrom(1);
2309 Known.Zero.setBitsFrom(1);
23212310 break;
23222311 case ISD::SHL:
23232312 if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
2324 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2325 Depth + 1);
2326 KnownZero <<= *ShAmt;
2327 KnownOne <<= *ShAmt;
2313 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2314 Known.Zero <<= *ShAmt;
2315 Known.One <<= *ShAmt;
23282316 // Low bits are known zero.
2329 KnownZero.setLowBits(ShAmt->getZExtValue());
2317 Known.Zero.setLowBits(ShAmt->getZExtValue());
23302318 }
23312319 break;
23322320 case ISD::SRL:
23332321 if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
2334 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2335 Depth + 1);
2336 KnownZero.lshrInPlace(*ShAmt);
2337 KnownOne.lshrInPlace(*ShAmt);
2322 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2323 Known.Zero.lshrInPlace(*ShAmt);
2324 Known.One.lshrInPlace(*ShAmt);
23382325 // High bits are known zero.
2339 KnownZero.setHighBits(ShAmt->getZExtValue());
2326 Known.Zero.setHighBits(ShAmt->getZExtValue());
23402327 }
23412328 break;
23422329 case ISD::SRA:
23432330 if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
2344 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2345 Depth + 1);
2346 KnownZero.lshrInPlace(*ShAmt);
2347 KnownOne.lshrInPlace(*ShAmt);
2331 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2332 Known.Zero.lshrInPlace(*ShAmt);
2333 Known.One.lshrInPlace(*ShAmt);
23482334 // If we know the value of the sign bit, then we know it is copied across
23492335 // the high bits by the shift amount.
23502336 APInt SignMask = APInt::getSignMask(BitWidth);
23512337 SignMask.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask.
2352 if (KnownZero.intersects(SignMask)) {
2353 KnownZero.setHighBits(ShAmt->getZExtValue());// New bits are known zero.
2354 } else if (KnownOne.intersects(SignMask)) {
2355 KnownOne.setHighBits(ShAmt->getZExtValue()); // New bits are known one.
2338 if (Known.Zero.intersects(SignMask)) {
2339 Known.Zero.setHighBits(ShAmt->getZExtValue());// New bits are known zero.
2340 } else if (Known.One.intersects(SignMask)) {
2341 Known.One.setHighBits(ShAmt->getZExtValue()); // New bits are known one.
23562342 }
23572343 }
23582344 break;
23732359 if (NewBits.getBoolValue())
23742360 InputDemandedBits |= InSignMask;
23752361
2376 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2377 Depth + 1);
2378 KnownOne &= InputDemandedBits;
2379 KnownZero &= InputDemandedBits;
2362 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2363 Known.One &= InputDemandedBits;
2364 Known.Zero &= InputDemandedBits;
23802365
23812366 // If the sign bit of the input is known set or clear, then we know the
23822367 // top bits of the result.
2383 if (KnownZero.intersects(InSignMask)) { // Input sign bit known clear
2384 KnownZero |= NewBits;
2385 KnownOne &= ~NewBits;
2386 } else if (KnownOne.intersects(InSignMask)) { // Input sign bit known set
2387 KnownOne |= NewBits;
2388 KnownZero &= ~NewBits;
2368 if (Known.Zero.intersects(InSignMask)) { // Input sign bit known clear
2369 Known.Zero |= NewBits;
2370 Known.One &= ~NewBits;
2371 } else if (Known.One.intersects(InSignMask)) { // Input sign bit known set
2372 Known.One |= NewBits;
2373 Known.Zero &= ~NewBits;
23892374 } else { // Input sign bit unknown
2390 KnownZero &= ~NewBits;
2391 KnownOne &= ~NewBits;
2375 Known.Zero &= ~NewBits;
2376 Known.One &= ~NewBits;
23922377 }
23932378 break;
23942379 }
23972382 case ISD::CTLZ:
23982383 case ISD::CTLZ_ZERO_UNDEF:
23992384 case ISD::CTPOP: {
2400 KnownZero.setBitsFrom(Log2_32(BitWidth)+1);
2385 Known.Zero.setBitsFrom(Log2_32(BitWidth)+1);
24012386 break;
24022387 }
24032388 case ISD::LOAD: {
24062391 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) {
24072392 EVT VT = LD->getMemoryVT();
24082393 unsigned MemBits = VT.getScalarSizeInBits();
2409 KnownZero.setBitsFrom(MemBits);
2394 Known.Zero.setBitsFrom(MemBits);
24102395 } else if (const MDNode *Ranges = LD->getRanges()) {
24112396 if (LD->getExtensionType() == ISD::NON_EXTLOAD)
2412 computeKnownBitsFromRangeMetadata(*Ranges, KnownZero, KnownOne);
2397 computeKnownBitsFromRangeMetadata(*Ranges, Known.Zero, Known.One);
24132398 }
24142399 break;
24152400 }
24162401 case ISD::ZERO_EXTEND_VECTOR_INREG: {
24172402 EVT InVT = Op.getOperand(0).getValueType();
24182403 unsigned InBits = InVT.getScalarSizeInBits();
2419 KnownZero = KnownZero.trunc(InBits);
2420 KnownOne = KnownOne.trunc(InBits);
2421 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne,
2404 Known.Zero = Known.Zero.trunc(InBits);
2405 Known.One = Known.One.trunc(InBits);
2406 computeKnownBits(Op.getOperand(0), Known,
24222407 DemandedElts.zext(InVT.getVectorNumElements()),
24232408 Depth + 1);
2424 KnownZero = KnownZero.zext(BitWidth);
2425 KnownOne = KnownOne.zext(BitWidth);
2426 KnownZero.setBitsFrom(InBits);
2409 Known.Zero = Known.Zero.zext(BitWidth);
2410 Known.One = Known.One.zext(BitWidth);
2411 Known.Zero.setBitsFrom(InBits);
24272412 break;
24282413 }
24292414 case ISD::ZERO_EXTEND: {
24302415 EVT InVT = Op.getOperand(0).getValueType();
24312416 unsigned InBits = InVT.getScalarSizeInBits();
2432 KnownZero = KnownZero.trunc(InBits);
2433 KnownOne = KnownOne.trunc(InBits);
2434 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2435 Depth + 1);
2436 KnownZero = KnownZero.zext(BitWidth);
2437 KnownOne = KnownOne.zext(BitWidth);
2438 KnownZero.setBitsFrom(InBits);
2417 Known.Zero = Known.Zero.trunc(InBits);
2418 Known.One = Known.One.trunc(InBits);
2419 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2420 Known.Zero = Known.Zero.zext(BitWidth);
2421 Known.One = Known.One.zext(BitWidth);
2422 Known.Zero.setBitsFrom(InBits);
24392423 break;
24402424 }
24412425 // TODO ISD::SIGN_EXTEND_VECTOR_INREG
24432427 EVT InVT = Op.getOperand(0).getValueType();
24442428 unsigned InBits = InVT.getScalarSizeInBits();
24452429
2446 KnownZero = KnownZero.trunc(InBits);
2447 KnownOne = KnownOne.trunc(InBits);
2448 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2449 Depth + 1);
2430 Known.Zero = Known.Zero.trunc(InBits);
2431 Known.One = Known.One.trunc(InBits);
2432 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
24502433
24512434 // If the sign bit is known to be zero or one, then sext will extend
24522435 // it to the top bits, else it will just zext.
2453 KnownZero = KnownZero.sext(BitWidth);
2454 KnownOne = KnownOne.sext(BitWidth);
2436 Known.Zero = Known.Zero.sext(BitWidth);
2437 Known.One = Known.One.sext(BitWidth);
24552438 break;
24562439 }
24572440 case ISD::ANY_EXTEND: {
24582441 EVT InVT = Op.getOperand(0).getValueType();
24592442 unsigned InBits = InVT.getScalarSizeInBits();
2460 KnownZero = KnownZero.trunc(InBits);
2461 KnownOne = KnownOne.trunc(InBits);
2462 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
2463 KnownZero = KnownZero.zext(BitWidth);
2464 KnownOne = KnownOne.zext(BitWidth);
2443 Known.Zero = Known.Zero.trunc(InBits);
2444 Known.One = Known.One.trunc(InBits);
2445 computeKnownBits(Op.getOperand(0), Known, Depth+1);
2446 Known.Zero = Known.Zero.zext(BitWidth);
2447 Known.One = Known.One.zext(BitWidth);
24652448 break;
24662449 }
24672450 case ISD::TRUNCATE: {
24682451 EVT InVT = Op.getOperand(0).getValueType();
24692452 unsigned InBits = InVT.getScalarSizeInBits();
2470 KnownZero = KnownZero.zext(InBits);
2471 KnownOne = KnownOne.zext(InBits);
2472 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2473 Depth + 1);
2474 KnownZero = KnownZero.trunc(BitWidth);
2475 KnownOne = KnownOne.trunc(BitWidth);
2453 Known.Zero = Known.Zero.zext(InBits);
2454 Known.One = Known.One.zext(InBits);
2455 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2456 Known.Zero = Known.Zero.trunc(BitWidth);
2457 Known.One = Known.One.trunc(BitWidth);
24762458 break;
24772459 }
24782460 case ISD::AssertZext: {
24792461 EVT VT = cast(Op.getOperand(1))->getVT();
24802462 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
2481 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
2482 KnownZero |= (~InMask);
2483 KnownOne &= (~KnownZero);
2463 computeKnownBits(Op.getOperand(0), Known, Depth+1);
2464 Known.Zero |= (~InMask);
2465 Known.One &= (~Known.Zero);
24842466 break;
24852467 }
24862468 case ISD::FGETSIGN:
24872469 // All bits are zero except the low bit.
2488 KnownZero.setBitsFrom(1);
2470 Known.Zero.setBitsFrom(1);
24892471 break;
24902472 case ISD::USUBO:
24912473 case ISD::SSUBO:
24942476 if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
24952477 TargetLowering::ZeroOrOneBooleanContent &&
24962478 BitWidth > 1)
2497 KnownZero.setBitsFrom(1);
2479 Known.Zero.setBitsFrom(1);
24982480 break;
24992481 }
25002482 LLVM_FALLTHROUGH;
25082490 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
25092491 // NLZ can't be BitWidth with no sign bit
25102492 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
2511 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2493 computeKnownBits(Op.getOperand(1), Known2, DemandedElts,
25122494 Depth + 1);
25132495
25142496 // If all of the MaskV bits are known to be zero, then we know the
25152497 // output top bits are zero, because we now know that the output is
25162498 // from [0-C].
2517 if ((KnownZero2 & MaskV) == MaskV) {
2499 if ((Known2.Zero & MaskV) == MaskV) {
25182500 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros();
25192501 // Top bits known zero.
2520 KnownZero.setHighBits(NLZ2);
2502 Known.Zero.setHighBits(NLZ2);
25212503 }
25222504 }
25232505 }
25252507 // If low bits are know to be zero in both operands, then we know they are
25262508 // going to be 0 in the result. Both addition and complement operations
25272509 // preserve the low zero bits.
2528 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2529 Depth + 1);
2530 unsigned KnownZeroLow = KnownZero2.countTrailingOnes();
2510 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
2511 unsigned KnownZeroLow = Known2.Zero.countTrailingOnes();
25312512 if (KnownZeroLow == 0)
25322513 break;
25332514
2534 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2535 Depth + 1);
2515 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
25362516 KnownZeroLow = std::min(KnownZeroLow,
2537 KnownZero2.countTrailingOnes());
2538 KnownZero.setBits(0, KnownZeroLow);
2517 Known2.Zero.countTrailingOnes());
2518 Known.Zero.setBits(0, KnownZeroLow);
25392519 break;
25402520 }
25412521 case ISD::UADDO:
25452525 if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
25462526 TargetLowering::ZeroOrOneBooleanContent &&
25472527 BitWidth > 1)
2548 KnownZero.setBitsFrom(1);
2528 Known.Zero.setBitsFrom(1);
25492529 break;
25502530 }
25512531 LLVM_FALLTHROUGH;
25592539 // known to be clear. For example, if one input has the top 10 bits clear
25602540 // and the other has the top 8 bits clear, we know the top 7 bits of the
25612541 // output must be clear.
2562 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2563 Depth + 1);
2564 unsigned KnownZeroHigh = KnownZero2.countLeadingOnes();
2565 unsigned KnownZeroLow = KnownZero2.countTrailingOnes();
2566
2567 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2542 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
2543 unsigned KnownZeroHigh = Known2.Zero.countLeadingOnes();
2544 unsigned KnownZeroLow = Known2.Zero.countTrailingOnes();
2545
2546 computeKnownBits(Op.getOperand(1), Known2, DemandedElts,
25682547 Depth + 1);
25692548 KnownZeroHigh = std::min(KnownZeroHigh,
2570 KnownZero2.countLeadingOnes());
2549 Known2.Zero.countLeadingOnes());
25712550 KnownZeroLow = std::min(KnownZeroLow,
2572 KnownZero2.countTrailingOnes());
2551 Known2.Zero.countTrailingOnes());
25732552
25742553 if (Opcode == ISD::ADDE) {
25752554 // With ADDE, a carry bit may be added in, so we can only use this
25772556 // We then return to the caller that the low bit is unknown but that
25782557 // other bits are known zero.
25792558 if (KnownZeroLow >= 2)
2580 KnownZero.setBits(1, KnownZeroLow);
2559 Known.Zero.setBits(1, KnownZeroLow);
25812560 break;
25822561 }
25832562
2584 KnownZero.setLowBits(KnownZeroLow);
2563 Known.Zero.setLowBits(KnownZeroLow);
25852564 if (KnownZeroHigh > 1)
2586 KnownZero.setHighBits(KnownZeroHigh - 1);
2565 Known.Zero.setHighBits(KnownZeroHigh - 1);
25872566 break;
25882567 }
25892568 case ISD::SREM:
25912570 const APInt &RA = Rem->getAPIntValue().abs();
25922571 if (RA.isPowerOf2()) {
25932572 APInt LowBits = RA - 1;
2594 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2595 Depth + 1);
2573 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
25962574
25972575 // The low bits of the first operand are unchanged by the srem.
2598 KnownZero = KnownZero2 & LowBits;
2599 KnownOne = KnownOne2 & LowBits;
2576 Known.Zero = Known2.Zero & LowBits;
2577 Known.One = Known2.One & LowBits;
26002578
26012579 // If the first operand is non-negative or has all low bits zero, then
26022580 // the upper bits are all zero.
2603 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
2604 KnownZero |= ~LowBits;
2581 if (Known2.Zero[BitWidth-1] || ((Known2.Zero & LowBits) == LowBits))
2582 Known.Zero |= ~LowBits;
26052583
26062584 // If the first operand is negative and not all low bits are zero, then
26072585 // the upper bits are all one.
2608 if (KnownOne2[BitWidth-1] && ((KnownOne2 & LowBits) != 0))
2609 KnownOne |= ~LowBits;
2610 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
2586 if (Known2.One[BitWidth-1] && ((Known2.One & LowBits) != 0))
2587 Known.One |= ~LowBits;
2588 assert((Known.Zero & Known.One) == 0&&"Bits known to be one AND zero?");
26112589 }
26122590 }
26132591 break;
26162594 const APInt &RA = Rem->getAPIntValue();
26172595 if (RA.isPowerOf2()) {
26182596 APInt LowBits = (RA - 1);
2619 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2620 Depth + 1);
2597 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
26212598
26222599 // The upper bits are all zero, the lower ones are unchanged.
2623 KnownZero = KnownZero2 | ~LowBits;
2624 KnownOne = KnownOne2 & LowBits;
2600 Known.Zero = Known2.Zero | ~LowBits;
2601 Known.One = Known2.One & LowBits;
26252602 break;
26262603 }
26272604 }
26282605
26292606 // Since the result is less than or equal to either operand, any leading
26302607 // zero bits in either operand must also exist in the result.
2631 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2632 Depth + 1);
2633 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2634 Depth + 1);
2635
2636 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
2637 KnownZero2.countLeadingOnes());
2638 KnownOne.clearAllBits();
2639 KnownZero.clearAllBits();
2640 KnownZero.setHighBits(Leaders);
2608 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2609 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
2610
2611 uint32_t Leaders = std::max(Known.Zero.countLeadingOnes(),
2612 Known2.Zero.countLeadingOnes());
2613 Known.One.clearAllBits();
2614 Known.Zero.clearAllBits();
2615 Known.Zero.setHighBits(Leaders);
26412616 break;
26422617 }
26432618 case ISD::EXTRACT_ELEMENT: {
2644 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
2619 computeKnownBits(Op.getOperand(0), Known, Depth+1);
26452620 const unsigned Index = Op.getConstantOperandVal(1);
26462621 const unsigned BitWidth = Op.getValueSizeInBits();
26472622
26482623 // Remove low part of known bits mask
2649 KnownZero = KnownZero.getHiBits(KnownZero.getBitWidth() - Index * BitWidth);
2650 KnownOne = KnownOne.getHiBits(KnownOne.getBitWidth() - Index * BitWidth);
2624 Known.Zero = Known.Zero.getHiBits(Known.Zero.getBitWidth() - Index * BitWidth);
2625 Known.One = Known.One.getHiBits(Known.One.getBitWidth() - Index * BitWidth);
26512626
26522627 // Remove high part of known bit mask
2653 KnownZero = KnownZero.trunc(BitWidth);
2654 KnownOne = KnownOne.trunc(BitWidth);
2628 Known.Zero = Known.Zero.trunc(BitWidth);
2629 Known.One = Known.One.trunc(BitWidth);
26552630 break;
26562631 }
26572632 case ISD::EXTRACT_VECTOR_ELT: {
26642639 // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
26652640 // anything about the extended bits.
26662641 if (BitWidth > EltBitWidth) {
2667 KnownZero = KnownZero.trunc(EltBitWidth);
2668 KnownOne = KnownOne.trunc(EltBitWidth);
2642 Known.Zero = Known.Zero.trunc(EltBitWidth);
2643 Known.One = Known.One.trunc(EltBitWidth);
26692644 }
26702645 ConstantSDNode *ConstEltNo = dyn_cast(EltNo);
26712646 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts)) {
26722647 // If we know the element index, just demand that vector element.
26732648 unsigned Idx = ConstEltNo->getZExtValue();
26742649 APInt DemandedElt = APInt::getOneBitSet(NumSrcElts, Idx);
2675 computeKnownBits(InVec, KnownZero, KnownOne, DemandedElt, Depth + 1);
2650 computeKnownBits(InVec, Known, DemandedElt, Depth + 1);
26762651 } else {
26772652 // Unknown element index, so ignore DemandedElts and demand them all.
2678 computeKnownBits(InVec, KnownZero, KnownOne, Depth + 1);
2653 computeKnownBits(InVec, Known, Depth + 1);
26792654 }
26802655 if (BitWidth > EltBitWidth) {
2681 KnownZero = KnownZero.zext(BitWidth);
2682 KnownOne = KnownOne.zext(BitWidth);
2656 Known.Zero = Known.Zero.zext(BitWidth);
2657 Known.One = Known.One.zext(BitWidth);
26832658 }
26842659 break;
26852660 }
26922667 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
26932668 // If we know the element index, split the demand between the
26942669 // source vector and the inserted element.
2695 KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
2670 Known.Zero = Known.One = APInt::getAllOnesValue(BitWidth);
26962671 unsigned EltIdx = CEltNo->getZExtValue();
26972672
26982673 // If we demand the inserted element then add its common known bits.
26992674 if (DemandedElts[EltIdx]) {
2700 computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
2701 KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
2702 KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
2675 computeKnownBits(InVal, Known2, Depth + 1);
2676 Known.One &= Known2.One.zextOrTrunc(Known.One.getBitWidth());
2677 Known.Zero &= Known2.Zero.zextOrTrunc(Known.Zero.getBitWidth());;
27032678 }
27042679
27052680 // If we demand the source vector then add its common known bits, ensuring
27062681 // that we don't demand the inserted element.
27072682 APInt VectorElts = DemandedElts & ~(APInt::getOneBitSet(NumElts, EltIdx));
27082683 if (!!VectorElts) {
2709 computeKnownBits(InVec, KnownZero2, KnownOne2, VectorElts, Depth + 1);
2710 KnownOne &= KnownOne2;
2711 KnownZero &= KnownZero2;
2684 computeKnownBits(InVec, Known2, VectorElts, Depth + 1);
2685 Known.One &= Known2.One;
2686 Known.Zero &= Known2.Zero;
27122687 }
27132688 } else {
27142689 // Unknown element index, so ignore DemandedElts and demand them all.
2715 computeKnownBits(InVec, KnownZero, KnownOne, Depth + 1);
2716 computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
2717 KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
2718 KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
2690 computeKnownBits(InVec, Known, Depth + 1);
2691 computeKnownBits(InVal, Known2, Depth + 1);
2692 Known.One &= Known2.One.zextOrTrunc(Known.One.getBitWidth());
2693 Known.Zero &= Known2.Zero.zextOrTrunc(Known.Zero.getBitWidth());;
27192694 }
27202695 break;
27212696 }
27222697 case ISD::BITREVERSE: {
2723 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2724 Depth + 1);
2725 KnownZero = KnownZero2.reverseBits();
2726 KnownOne = KnownOne2.reverseBits();
2698 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
2699 Known.Zero = Known2.Zero.reverseBits();
2700 Known.One = Known2.One.reverseBits();
27272701 break;
27282702 }
27292703 case ISD::BSWAP: {
2730 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2731 Depth + 1);
2732 KnownZero = KnownZero2.byteSwap();
2733 KnownOne = KnownOne2.byteSwap();
2704 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
2705 Known.Zero = Known2.Zero.byteSwap();
2706 Known.One = Known2.One.byteSwap();
27342707 break;
27352708 }
27362709 case ISD::ABS: {
2737 computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
2738 Depth + 1);
2710 computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
27392711
27402712 // If the source's MSB is zero then we know the rest of the bits already.
2741 if (KnownZero2[BitWidth - 1]) {
2742 KnownZero = KnownZero2;
2743 KnownOne = KnownOne2;
2713 if (Known2.Zero[BitWidth - 1]) {
2714 Known.Zero = Known2.Zero;
2715 Known.One = Known2.One;
27442716 break;
27452717 }
27462718
27472719 // We only know that the absolute values's MSB will be zero iff there is
27482720 // a set bit that isn't the sign bit (otherwise it could be INT_MIN).
2749 KnownOne2.clearBit(BitWidth - 1);
2750 if (KnownOne2.getBoolValue()) {
2751 KnownZero = APInt::getSignMask(BitWidth);
2721 Known2.One.clearBit(BitWidth - 1);
2722 if (Known2.One.getBoolValue()) {
2723 Known.Zero = APInt::getSignMask(BitWidth);
27522724 break;
27532725 }
27542726 break;
27552727 }
27562728 case ISD::UMIN: {
2757 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2758 Depth + 1);
2759 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2760 Depth + 1);
2729 computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
2730 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
27612731
27622732 // UMIN - we know that the result will have the maximum of the
27632733 // known zero leading bits of the inputs.
2764 unsigned LeadZero = KnownZero.countLeadingOnes();
2765 LeadZero = std::max(LeadZero, KnownZero2.countLeadingOnes());
2766
2767 KnownZero &= KnownZero2;
2768 KnownOne &= KnownOne2;
2769 KnownZero.setHighBits(LeadZero);
2734 unsigned LeadZero = Known.Zero.countLeadingOnes();
2735 LeadZero = std::max(LeadZero, Known2.Zero.countLeadingOnes());
2736
2737 Known.Zero &= Known2.Zero;
2738 Known.One &= Known2.One;
2739 Known.Zero.setHighBits(LeadZero);
27702740 break;
27712741 }
27722742 case ISD::UMAX: {
2773 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2743 computeKnownBits(Op.getOperand(0), Known, DemandedElts,
27742744 Depth + 1);
2775 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2776 Depth + 1);
2745 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
27772746
27782747 // UMAX - we know that the result will have the maximum of the
27792748 // known one leading bits of the inputs.
2780 unsigned LeadOne = KnownOne.countLeadingOnes();
2781 LeadOne = std::max(LeadOne, KnownOne2.countLeadingOnes());
2782
2783 KnownZero &= KnownZero2;
2784 KnownOne &= KnownOne2;
2785 KnownOne.setHighBits(LeadOne);
2749 unsigned LeadOne = Known.One.countLeadingOnes();
2750 LeadOne = std::max(LeadOne, Known2.One.countLeadingOnes());
2751
2752 Known.Zero &= Known2.Zero;
2753 Known.One &= Known2.One;
2754 Known.One.setHighBits(LeadOne);
27862755 break;
27872756 }
27882757 case ISD::SMIN:
27892758 case ISD::SMAX: {
2790 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
2759 computeKnownBits(Op.getOperand(0), Known, DemandedElts,
27912760 Depth + 1);
27922761 // If we don't know any bits, early out.
2793 if (!KnownOne && !KnownZero)
2762 if (!Known.One && !Known.Zero)
27942763 break;
2795 computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, DemandedElts,
2796 Depth + 1);
2797 KnownZero &= KnownZero2;
2798 KnownOne &= KnownOne2;
2764 computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
2765 Known.Zero &= Known2.Zero;
2766 Known.One &= Known2.One;
27992767 break;
28002768 }
28012769 case ISD::FrameIndex:
28022770 case ISD::TargetFrameIndex:
28032771 if (unsigned Align = InferPtrAlignment(Op)) {
28042772 // The low bits are known zero if the pointer is aligned.
2805 KnownZero.setLowBits(Log2_32(Align));
2773 Known.Zero.setLowBits(Log2_32(Align));
28062774 break;
28072775 }
28082776 break;
28152783 case ISD::INTRINSIC_W_CHAIN:
28162784 case ISD::INTRINSIC_VOID:
28172785 // Allow the target to implement this method for its nodes.
2818 TLI->computeKnownBitsForTargetNode(Op, KnownZero, KnownOne, DemandedElts,
2819 *this, Depth);
2820 break;
2821 }
2822
2823 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
2786 TLI->computeKnownBitsForTargetNode(Op, Known, DemandedElts, *this, Depth);
2787 break;
2788 }
2789
2790 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
28242791 }
28252792
28262793 SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind(SDValue N0,
28292796 if (isNullConstant(N1))
28302797 return OFK_Never;
28312798
2832 APInt N1Zero, N1One;
2833 computeKnownBits(N1, N1Zero, N1One);
2834 if (N1Zero.getBoolValue()) {
2835 APInt N0Zero, N0One;
2836 computeKnownBits(N0, N0Zero, N0One);
2799 KnownBits N1Known;
2800 computeKnownBits(N1, N1Known);
2801 if (N1Known.Zero.getBoolValue()) {
2802 KnownBits N0Known;
2803 computeKnownBits(N0, N0Known);
28372804
28382805 bool overflow;
2839 (void)(~N0Zero).uadd_ov(~N1Zero, overflow);
2806 (void)(~N0Known.Zero).uadd_ov(~N1Known.Zero, overflow);
28402807 if (!overflow)
28412808 return OFK_Never;
28422809 }
28432810
28442811 // mulhi + 1 never overflow
28452812 if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 &&
2846 (~N1Zero & 0x01) == ~N1Zero)
2813 (~N1Known.Zero & 0x01) == ~N1Known.Zero)
28472814 return OFK_Never;
28482815
28492816 if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) {
2850 APInt N0Zero, N0One;
2851 computeKnownBits(N0, N0Zero, N0One);
2852
2853 if ((~N0Zero & 0x01) == ~N0Zero)
2817 KnownBits N0Known;
2818 computeKnownBits(N0, N0Known);
2819
2820 if ((~N0Known.Zero & 0x01) == ~N0Known.Zero)
28542821 return OFK_Never;
28552822 }
28562823
28942861 // to handle some common cases.
28952862
28962863 // Fall back to computeKnownBits to catch other known cases.
2897 APInt KnownZero, KnownOne;
2898 computeKnownBits(Val, KnownZero, KnownOne);
2899 return (KnownZero.countPopulation() == BitWidth - 1) &&
2900 (KnownOne.countPopulation() == 1);
2864 KnownBits Known;
2865 computeKnownBits(Val, Known);
2866 return (Known.Zero.countPopulation() == BitWidth - 1) &&
2867 (Known.One.countPopulation() == 1);
29012868 }
29022869
29032870 unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
30673034 // Special case decrementing a value (ADD X, -1):
30683035 if (ConstantSDNode *CRHS = dyn_cast(Op.getOperand(1)))
30693036 if (CRHS->isAllOnesValue()) {
3070 APInt KnownZero, KnownOne;
3071 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
3037 KnownBits Known;
3038 computeKnownBits(Op.getOperand(0), Known, Depth+1);
30723039
30733040 // If the input is known to be 0 or 1, the output is 0/-1, which is all
30743041 // sign bits set.
3075 if ((KnownZero | 1).isAllOnesValue())
3042 if ((Known.Zero | 1).isAllOnesValue())
30763043 return VTBits;
30773044
30783045 // If we are subtracting one from a positive number, there is no carry
30793046 // out of the result.
3080 if (KnownZero.isNegative())
3047 if (Known.Zero.isNegative())
30813048 return Tmp;
30823049 }
30833050
30923059 // Handle NEG.
30933060 if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0)))
30943061 if (CLHS->isNullValue()) {
3095 APInt KnownZero, KnownOne;
3096 computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
3062 KnownBits Known;
3063 computeKnownBits(Op.getOperand(1), Known, Depth+1);
30973064 // If the input is known to be 0 or 1, the output is 0/-1, which is all
30983065 // sign bits set.
3099 if ((KnownZero | 1).isAllOnesValue())
3066 if ((Known.Zero | 1).isAllOnesValue())
31003067 return VTBits;
31013068
31023069 // If the input is known to be positive (the sign bit is known clear),
31033070 // the output of the NEG has the same number of sign bits as the input.
3104 if (KnownZero.isNegative())
3071 if (Known.Zero.isNegative())
31053072 return Tmp2;
31063073
31073074 // Otherwise, we treat this like a SUB.
31983165
31993166 // Finally, if we can prove that the top bits of the result are 0's or 1's,
32003167 // use this information.
3201 APInt KnownZero, KnownOne;
3202 computeKnownBits(Op, KnownZero, KnownOne, DemandedElts, Depth);
3168 KnownBits Known;
3169 computeKnownBits(Op, Known, DemandedElts, Depth);
32033170
32043171 APInt Mask;
3205 if (KnownZero.isNegative()) { // sign bit is 0
3206 Mask = KnownZero;
3207 } else if (KnownOne.isNegative()) { // sign bit is 1;
3208 Mask = KnownOne;
3172 if (Known.Zero.isNegative()) { // sign bit is 0
3173 Mask = Known.Zero;
3174 } else if (Known.One.isNegative()) { // sign bit is 1;
3175 Mask = Known.One;
32093176 } else {
32103177 // Nothing known.
32113178 return FirstAnswer;
32833250 bool SelectionDAG::haveNoCommonBitsSet(SDValue A, SDValue B) const {
32843251 assert(A.getValueType() == B.getValueType() &&
32853252 "Values must have the same type");
3286 APInt AZero, AOne;
3287 APInt BZero, BOne;
3288 computeKnownBits(A, AZero, AOne);
3289 computeKnownBits(B, BZero, BOne);
3290 return (AZero | BZero).isAllOnesValue();
3253 KnownBits AKnown, BKnown;
3254 computeKnownBits(A, AKnown);
3255 computeKnownBits(B, BKnown);
3256 return (AKnown.Zero | BKnown.Zero).isAllOnesValue();
32913257 }
32923258
32933259 static SDValue FoldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
674674
675675 unsigned RegSize = RegisterVT.getSizeInBits();
676676 unsigned NumSignBits = LOI->NumSignBits;
677 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
677 unsigned NumZeroBits = LOI->Known.Zero.countLeadingOnes();
678678
679679 if (NumZeroBits == RegSize) {
680680 // The current value is a zero.
7272 #include "llvm/Support/Compiler.h"
7373 #include "llvm/Support/Debug.h"
7474 #include "llvm/Support/ErrorHandling.h"
75 #include "llvm/Support/KnownBits.h"
7576 #include "llvm/Support/Timer.h"
7677 #include "llvm/Support/raw_ostream.h"
7778 #include "llvm/Target/TargetInstrInfo.h"
649650
650651 Worklist.push_back(CurDAG->getRoot().getNode());
651652
652 APInt KnownZero;
653 APInt KnownOne;
653 KnownBits Known;
654654
655655 do {
656656 SDNode *N = Worklist.pop_back_val();
679679 continue;
680680
681681 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
682 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
683 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
682 CurDAG->computeKnownBits(Src, Known);
683 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, Known);
684684 } while (!Worklist.empty());
685685 }
686686
19291929 // either already zero or is not demanded. Check for known zero input bits.
19301930 APInt NeededMask = DesiredMask & ~ActualMask;
19311931
1932 APInt KnownZero, KnownOne;
1933 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1932 KnownBits Known;
1933 CurDAG->computeKnownBits(LHS, Known);
19341934
19351935 // If all the missing bits in the or are already known to be set, match!
1936 if (NeededMask.isSubsetOf(KnownOne))
1936 if (NeededMask.isSubsetOf(Known.One))
19371937 return true;
19381938
19391939 // TODO: check to see if missing bits are just not demanded.
2626 #include "llvm/MC/MCAsmInfo.h"
2727 #include "llvm/MC/MCExpr.h"
2828 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/KnownBits.h"
2930 #include "llvm/Support/MathExtras.h"
3031 #include "llvm/Target/TargetLoweringObjectFile.h"
3132 #include "llvm/Target/TargetMachine.h"
436437 DAGCombinerInfo &DCI,
437438 TargetLoweringOpt &TLO) const {
438439 SDValue Op = User->getOperand(OpIdx);
439 APInt KnownZero, KnownOne;
440
441 if (!SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne,
442 TLO, 0, true))
440 KnownBits Known;
441
442 if (!SimplifyDemandedBits(Op, Demanded, Known, TLO, 0, true))
443443 return false;
444444
445445
487487 SelectionDAG &DAG = DCI.DAG;
488488 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
489489 !DCI.isBeforeLegalizeOps());
490 APInt KnownZero, KnownOne;
491
492 bool Simplified = SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne,
493 TLO);
490 KnownBits Known;
491
492 bool Simplified = SimplifyDemandedBits(Op, DemandedMask, Known, TLO);
494493 if (Simplified)
495494 DCI.CommitTargetLoweringOpt(TLO);
496495 return Simplified;
500499 /// result of Op are ever used downstream. If we can use this information to
501500 /// simplify Op, create a new simplified DAG node and return true, returning the
502501 /// original and new nodes in Old and New. Otherwise, analyze the expression and
503 /// return a mask of KnownOne and KnownZero bits for the expression (used to
504 /// simplify the caller). The KnownZero/One bits may only be accurate for those
505 /// bits in the DemandedMask.
502 /// return a mask of Known bits for the expression (used to simplify the
503 /// caller). The Known bits may only be accurate for those bits in the
504 /// DemandedMask.
506505 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
507506 const APInt &DemandedMask,
508 APInt &KnownZero,
509 APInt &KnownOne,
507 KnownBits &Known,
510508 TargetLoweringOpt &TLO,
511509 unsigned Depth,
512510 bool AssumeSingleUse) const {
518516 auto &DL = TLO.DAG.getDataLayout();
519517
520518 // Don't know anything.
521 KnownZero = KnownOne = APInt(BitWidth, 0);
519 Known = KnownBits(BitWidth);
522520
523521 // Other users may use these bits.
524522 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
525523 if (Depth != 0) {
526 // If not at the root, Just compute the KnownZero/KnownOne bits to
524 // If not at the root, Just compute the Known bits to
527525 // simplify things downstream.
528 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
526 TLO.DAG.computeKnownBits(Op, Known, Depth);
529527 return false;
530528 }
531529 // If this is the root being simplified, allow it to have multiple uses,
540538 return false;
541539 }
542540
543 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
541 KnownBits Known2, KnownOut;
544542 switch (Op.getOpcode()) {
545543 case ISD::Constant:
546544 // We know all of the bits for a constant!
547 KnownOne = cast(Op)->getAPIntValue();
548 KnownZero = ~KnownOne;
545 Known.One = cast(Op)->getAPIntValue();
546 Known.Zero = ~Known.One;
549547 return false; // Don't fall through, will infinitely loop.
550548 case ISD::BUILD_VECTOR:
551549 // Collect the known bits that are shared by every constant vector element.
552 KnownZero.setAllBits(); KnownOne.setAllBits();
550 Known.Zero.setAllBits(); Known.One.setAllBits();
553551 for (SDValue SrcOp : Op->ops()) {
554552 if (!isa(SrcOp)) {
555553 // We can only handle all constant values - bail out with no known bits.
556 KnownZero = KnownOne = APInt(BitWidth, 0);
554 Known = KnownBits(BitWidth);
557555 return false;
558556 }
559 KnownOne2 = cast(SrcOp)->getAPIntValue();
560 KnownZero2 = ~KnownOne2;
557 Known2.One = cast(SrcOp)->getAPIntValue();
558 Known2.Zero = ~Known2.One;
561559
562560 // BUILD_VECTOR can implicitly truncate sources, we must handle this.
563 if (KnownOne2.getBitWidth() != BitWidth) {
564 assert(KnownOne2.getBitWidth() > BitWidth &&
565 KnownZero2.getBitWidth() > BitWidth &&
561 if (Known2.One.getBitWidth() != BitWidth) {
562 assert(Known2.getBitWidth() > BitWidth &&
566563 "Expected BUILD_VECTOR implicit truncation");
567 KnownOne2 = KnownOne2.trunc(BitWidth);
568 KnownZero2 = KnownZero2.trunc(BitWidth);
564 Known2.One = Known2.One.trunc(BitWidth);
565 Known2.Zero = Known2.Zero.trunc(BitWidth);
569566 }
570567
571568 // Known bits are the values that are shared by every element.
572569 // TODO: support per-element known bits.
573 KnownOne &= KnownOne2;
574 KnownZero &= KnownZero2;
570 Known.One &= Known2.One;
571 Known.Zero &= Known2.Zero;
575572 }
576573 return false; // Don't fall through, will infinitely loop.
577574 case ISD::AND:
581578 // the RHS.
582579 if (ConstantSDNode *RHSC = isConstOrConstSplat(Op.getOperand(1))) {
583580 SDValue Op0 = Op.getOperand(0);
584 APInt LHSZero, LHSOne;
581 KnownBits LHSKnown;
585582 // Do not increment Depth here; that can cause an infinite loop.
586 TLO.DAG.computeKnownBits(Op0, LHSZero, LHSOne, Depth);
583 TLO.DAG.computeKnownBits(Op0, LHSKnown, Depth);
587584 // If the LHS already has zeros where RHSC does, this and is dead.
588 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
585 if ((LHSKnown.Zero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
589586 return TLO.CombineTo(Op, Op0);
590587
591588 // If any of the set bits in the RHS are known zero on the LHS, shrink
592589 // the constant.
593 if (ShrinkDemandedConstant(Op, ~LHSZero & NewMask, TLO))
590 if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & NewMask, TLO))
594591 return true;
595592
596593 // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
599596 // the xor. For example, for a 32-bit X:
600597 // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
601598 if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
602 LHSOne == ~RHSC->getAPIntValue()) {
599 LHSKnown.One == ~RHSC->getAPIntValue()) {
603600 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, Op.getValueType(),
604601 Op0.getOperand(0), Op.getOperand(1));
605602 return TLO.CombineTo(Op, Xor);
606603 }
607604 }
608605
609 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
610 KnownOne, TLO, Depth+1))
606 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
611607 return true;
612 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
613 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
614 KnownZero2, KnownOne2, TLO, Depth+1))
608 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
609 if (SimplifyDemandedBits(Op.getOperand(0), ~Known.Zero & NewMask,
610 Known2, TLO, Depth+1))
615611 return true;
616 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
612 assert((Known2.Zero & Known2.One) == 0 && "Bits known to be one AND zero?");
617613
618614 // If all of the demanded bits are known one on one side, return the other.
619615 // These bits cannot contribute to the result of the 'and'.
620 if (NewMask.isSubsetOf(KnownZero2 | KnownOne))
616 if (NewMask.isSubsetOf(Known2.Zero | Known.One))
621617 return TLO.CombineTo(Op, Op.getOperand(0));
622 if (NewMask.isSubsetOf(KnownZero | KnownOne2))
618 if (NewMask.isSubsetOf(Known.Zero | Known2.One))
623619 return TLO.CombineTo(Op, Op.getOperand(1));
624620 // If all of the demanded bits in the inputs are known zeros, return zero.
625 if (NewMask.isSubsetOf(KnownZero | KnownZero2))
621 if (NewMask.isSubsetOf(Known.Zero | Known2.Zero))
626622 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
627623 // If the RHS is a constant, see if we can simplify it.
628 if (ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask, TLO))
624 if (ShrinkDemandedConstant(Op, ~Known2.Zero & NewMask, TLO))
629625 return true;
630626 // If the operation can be done in a smaller type, do so.
631627 if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
632628 return true;
633629
634630 // Output known-1 bits are only known if set in both the LHS & RHS.
635 KnownOne &= KnownOne2;
631 Known.One &= Known2.One;
636632 // Output known-0 are known to be clear if zero in either the LHS | RHS.
637 KnownZero |= KnownZero2;
633 Known.Zero |= Known2.Zero;
638634 break;
639635 case ISD::OR:
640 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
641 KnownOne, TLO, Depth+1))
636 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
642637 return true;
643 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
644 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
645 KnownZero2, KnownOne2, TLO, Depth+1))
638 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
639 if (SimplifyDemandedBits(Op.getOperand(0), ~Known.One & NewMask,
640 Known2, TLO, Depth+1))
646641 return true;
647 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
642 assert((Known2.Zero & Known2.One) == 0 && "Bits known to be one AND zero?");
648643
649644 // If all of the demanded bits are known zero on one side, return the other.
650645 // These bits cannot contribute to the result of the 'or'.
651 if (NewMask.isSubsetOf(KnownOne2 | KnownZero))
646 if (NewMask.isSubsetOf(Known2.One | Known.Zero))
652647 return TLO.CombineTo(Op, Op.getOperand(0));
653 if (NewMask.isSubsetOf(KnownOne | KnownZero2))
648 if (NewMask.isSubsetOf(Known.One | Known2.Zero))
654649 return TLO.CombineTo(Op, Op.getOperand(1));
655650 // If the RHS is a constant, see if we can simplify it.
656651 if (ShrinkDemandedConstant(Op, NewMask, TLO))
660655 return true;
661656
662657 // Output known-0 bits are only known if clear in both the LHS & RHS.
663 KnownZero &= KnownZero2;
658 Known.Zero &= Known2.Zero;
664659 // Output known-1 are known to be set if set in either the LHS | RHS.
665 KnownOne |= KnownOne2;
660 Known.One |= Known2.One;
666661 break;
667662 case ISD::XOR:
668 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
669 KnownOne, TLO, Depth+1))
663 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
670664 return true;
671 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
672 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
673 KnownOne2, TLO, Depth+1))
665 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
666 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, Known2, TLO, Depth+1))
674667 return true;
675 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
668 assert((Known2.Zero & Known2.One) == 0 && "Bits known to be one AND zero?");
676669
677670 // If all of the demanded bits are known zero on one side, return the other.
678671 // These bits cannot contribute to the result of the 'xor'.
679 if (NewMask.isSubsetOf(KnownZero))
672 if (NewMask.isSubsetOf(Known.Zero))
680673 return TLO.CombineTo(Op, Op.getOperand(0));
681 if (NewMask.isSubsetOf(KnownZero2))
674 if (NewMask.isSubsetOf(Known2.Zero))
682675 return TLO.CombineTo(Op, Op.getOperand(1));
683676 // If the operation can be done in a smaller type, do so.
684677 if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
687680 // If all of the unknown bits are known to be zero on one side or the other
688681 // (but not both) turn this into an *inclusive* or.
689682 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
690 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
683 if ((NewMask & ~Known.Zero & ~Known2.Zero) == 0)
691684 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
692685 Op.getOperand(0),
693686 Op.getOperand(1)));
694687
695688 // Output known-0 bits are known if clear or set in both the LHS & RHS.
696 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
689 KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
697690 // Output known-1 are known to be set if set in only one of the LHS, RHS.
698 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
691 KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
699692
700693 // If all of the demanded bits on one side are known, and all of the set
701694 // bits on that side are also known to be set on the other side, turn this
702695 // into an AND, as we know the bits will be cleared.
703696 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
704697 // NB: it is okay if more bits are known than are requested
705 if (NewMask.isSubsetOf(KnownZero|KnownOne)) { // all known on one side
706 if (KnownOne == KnownOne2) { // set bits are the same on both sides
698 if (NewMask.isSubsetOf(Known.Zero|Known.One)) { // all known on one side
699 if (Known.One == Known2.One) { // set bits are the same on both sides
707700 EVT VT = Op.getValueType();
708 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
701 SDValue ANDC = TLO.DAG.getConstant(~Known.One & NewMask, dl, VT);
709702 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
710703 Op.getOperand(0), ANDC));
711704 }
731724 }
732725 }
733726
734 KnownZero = std::move(KnownZeroOut);
735 KnownOne = std::move(KnownOneOut);
727 Known = std::move(KnownOut);
736728 break;
737729 case ISD::SELECT:
738 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
739 KnownOne, TLO, Depth+1))
730 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known, TLO, Depth+1))
740731 return true;
741 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
742 KnownOne2, TLO, Depth+1))
732 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known2, TLO, Depth+1))
743733 return true;
744 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
745 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
734 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
735 assert((Known2.Zero & Known2.One) == 0 && "Bits known to be one AND zero?");
746736
747737 // If the operands are constants, see if we can simplify them.
748738 if (ShrinkDemandedConstant(Op, NewMask, TLO))
749739 return true;
750740
751741 // Only known if known in both the LHS and RHS.
752 KnownOne &= KnownOne2;
753 KnownZero &= KnownZero2;
742 Known.One &= Known2.One;
743 Known.Zero &= Known2.Zero;
754744 break;
755745 case ISD::SELECT_CC:
756 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
757 KnownOne, TLO, Depth+1))
746 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, Known, TLO, Depth+1))
758747 return true;
759 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
760 KnownOne2, TLO, Depth+1))
748 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known2, TLO, Depth+1))
761749 return true;
762 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
750 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
751 assert((Known2.Zero & Known2.One) == 0 && "Bits known to be one AND zero?");
764752
765753 // If the operands are constants, see if we can simplify them.
766754 if (ShrinkDemandedConstant(Op, NewMask, TLO))
767755 return true;
768756
769757 // Only known if known in both the LHS and RHS.
770 KnownOne &= KnownOne2;
771 KnownZero &= KnownZero2;
758 Known.One &= Known2.One;
759 Known.Zero &= Known2.Zero;
772760 break;
773761 case ISD::SETCC: {
774762 SDValue Op0 = Op.getOperand(0);
794782 if (getBooleanContents(Op0.getValueType()) ==
795783 TargetLowering::ZeroOrOneBooleanContent &&
796784 BitWidth > 1)
797 KnownZero.setBitsFrom(1);
785 Known.Zero.setBitsFrom(1);
798786 break;
799787 }
800788 case ISD::SHL:
828816 }
829817 }
830818
831 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
832 KnownZero, KnownOne, TLO, Depth+1))
819 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), Known, TLO, Depth+1))
833820 return true;
834821
835822 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
878865 }
879866 }
880867
881 KnownZero <<= SA->getZExtValue();
882 KnownOne <<= SA->getZExtValue();
868 Known.Zero <<= SA->getZExtValue();
869 Known.One <<= SA->getZExtValue();
883870 // low bits known zero.
884 KnownZero.setLowBits(SA->getZExtValue());
871 Known.Zero.setLowBits(SA->getZExtValue());
885872 }
886873 break;
887874 case ISD::SRL:
924911 }
925912
926913 // Compute the new bits that are at the top now.
927 if (SimplifyDemandedBits(InOp, InDemandedMask,
928 KnownZero, KnownOne, TLO, Depth+1))
914 if (SimplifyDemandedBits(InOp, InDemandedMask, Known, TLO, Depth+1))
929915 return true;
930 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
931 KnownZero.lshrInPlace(ShAmt);
932 KnownOne.lshrInPlace(ShAmt);
933
934 KnownZero.setHighBits(ShAmt); // High bits known zero.
916 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
917 Known.Zero.lshrInPlace(ShAmt);
918 Known.One.lshrInPlace(ShAmt);
919
920 Known.Zero.setHighBits(ShAmt); // High bits known zero.
935921 }
936922 break;
937923 case ISD::SRA:
964950 if (NewMask.countLeadingZeros() < ShAmt)
965951 InDemandedMask.setSignBit();
966952
967 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
968 KnownZero, KnownOne, TLO, Depth+1))
953 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, Known, TLO,
954 Depth+1))
969955 return true;
970 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
971 KnownZero.lshrInPlace(ShAmt);
972 KnownOne.lshrInPlace(ShAmt);
956 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
957 Known.Zero.lshrInPlace(ShAmt);
958 Known.One.lshrInPlace(ShAmt);
973959
974960 // If the input sign bit is known to be zero, or if none of the top bits
975961 // are demanded, turn this into an unsigned shift right.
976 if (KnownZero[BitWidth - ShAmt - 1] ||
962 if (Known.Zero[BitWidth - ShAmt - 1] ||
977963 NewMask.countLeadingZeros() >= ShAmt) {
978964 SDNodeFlags Flags;
979965 Flags.setExact(cast(Op)->Flags.hasExact());
992978 Op.getOperand(0), NewSA));
993979 }
994980
995 if (KnownOne[BitWidth - ShAmt - 1])
981 if (Known.One[BitWidth - ShAmt - 1])
996982 // New bits are known one.
997 KnownOne.setHighBits(ShAmt);
983 Known.One.setHighBits(ShAmt);
998984 }
999985 break;
1000986 case ISD::SIGN_EXTEND_INREG: {
10471033 InputDemandedBits |= InSignBit;
10481034
10491035 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1050 KnownZero, KnownOne, TLO, Depth+1))
1036 Known, TLO, Depth+1))
10511037 return true;
1052 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1038 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
10531039
10541040 // If the sign bit of the input is known set or clear, then we know the
10551041 // top bits of the result.
10561042
10571043 // If the input sign bit is known zero, convert this into a zero extension.
1058 if (KnownZero.intersects(InSignBit))
1044 if (Known.Zero.intersects(InSignBit))
10591045 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(
10601046 Op.getOperand(0), dl, ExVT.getScalarType()));
10611047
1062 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1063 KnownOne |= NewBits;
1064 KnownZero &= ~NewBits;
1048 if (Known.One.intersects(InSignBit)) { // Input sign bit known set
1049 Known.One |= NewBits;
1050 Known.Zero &= ~NewBits;
10651051 } else { // Input sign bit unknown
1066 KnownZero &= ~NewBits;
1067 KnownOne &= ~NewBits;
1052 Known.Zero &= ~NewBits;
1053 Known.One &= ~NewBits;
10681054 }
10691055 break;
10701056 }
10751061 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
10761062 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
10771063
1078 APInt KnownZeroLo, KnownOneLo;
1079 APInt KnownZeroHi, KnownOneHi;
1080
1081 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
1082 KnownOneLo, TLO, Depth + 1))
1064 KnownBits KnownLo, KnownHi;
1065
1066 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
10831067 return true;
10841068
1085 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
1086 KnownOneHi, TLO, Depth + 1))
1069 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
10871070 return true;
10881071
1089 KnownZero = KnownZeroLo.zext(BitWidth) |
1090 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
1091
1092 KnownOne = KnownOneLo.zext(BitWidth) |
1093 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
1072 Known.Zero = KnownLo.Zero.zext(BitWidth) |
1073 KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1074
1075 Known.One = KnownLo.One.zext(BitWidth) |
1076 KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
10941077 break;
10951078 }
10961079 case ISD::ZERO_EXTEND: {
11051088 Op.getValueType(),
11061089 Op.getOperand(0)));
11071090
1108 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1109 KnownZero, KnownOne, TLO, Depth+1))
1091 if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
11101092 return true;
1111 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1112 KnownZero = KnownZero.zext(BitWidth);
1113 KnownOne = KnownOne.zext(BitWidth);
1114 KnownZero |= NewBits;
1093 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
1094 Known.Zero = Known.Zero.zext(BitWidth);
1095 Known.One = Known.One.zext(BitWidth);
1096 Known.Zero |= NewBits;
11151097 break;
11161098 }
11171099 case ISD::SIGN_EXTEND: {
11331115 InDemandedBits |= InSignBit;
11341116 InDemandedBits = InDemandedBits.trunc(InBits);
11351117
1136 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1137 KnownOne, TLO, Depth+1))
1118 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, Known, TLO,
1119 Depth+1))
11381120 return true;
1139 KnownZero = KnownZero.zext(BitWidth);
1140 KnownOne = KnownOne.zext(BitWidth);
1121 Known.Zero = Known.Zero.zext(BitWidth);
1122 Known.One = Known.One.zext(BitWidth);
11411123
11421124 // If the sign bit is known zero, convert this to a zero extend.
1143 if (KnownZero.intersects(InSignBit))
1125 if (Known.Zero.intersects(InSignBit))
11441126 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
11451127 Op.getValueType(),
11461128 Op.getOperand(0)));
11471129
11481130 // If the sign bit is known one, the top bits match.
1149 if (KnownOne.intersects(InSignBit)) {
1150 KnownOne |= NewBits;
1151 assert((KnownZero & NewBits) == 0);
1131 if (Known.One.intersects(InSignBit)) {
1132 Known.One |= NewBits;
1133 assert((Known.Zero & NewBits) == 0);
11521134 } else { // Otherwise, top bits aren't known.
1153 assert((KnownOne & NewBits) == 0);
1154 assert((KnownZero & NewBits) == 0);
1135 assert((Known.One & NewBits) == 0);
1136 assert((Known.Zero & NewBits) == 0);
11551137 }
11561138 break;
11571139 }
11581140 case ISD::ANY_EXTEND: {
11591141 unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
11601142 APInt InMask = NewMask.trunc(OperandBitWidth);
1161 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1162 KnownZero, KnownOne, TLO, Depth+1))
1143 if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
11631144 return true;
1164 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1165 KnownZero = KnownZero.zext(BitWidth);
1166 KnownOne = KnownOne.zext(BitWidth);
1145 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
1146 Known.Zero = Known.Zero.zext(BitWidth);
1147 Known.One = Known.One.zext(BitWidth);
11671148 break;
11681149 }
11691150 case ISD::TRUNCATE: {
11711152 // zero/one bits live out.
11721153 unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
11731154 APInt TruncMask = NewMask.zext(OperandBitWidth);
1174 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1175 KnownZero, KnownOne, TLO, Depth+1))
1155 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, Known, TLO, Depth+1))
11761156 return true;
1177 KnownZero = KnownZero.trunc(BitWidth);
1178 KnownOne = KnownOne.trunc(BitWidth);
1157 Known.Zero = Known.Zero.trunc(BitWidth);
1158 Known.One = Known.One.trunc(BitWidth);
11791159
11801160 // If the input is only used by this truncate, see if we can shrink it based
11811161 // on the known demanded bits.
12231203 }
12241204 }
12251205
1226 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1206 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
12271207 break;
12281208 }
12291209 case ISD::AssertZext: {
12331213 APInt InMask = APInt::getLowBitsSet(BitWidth,
12341214 VT.getSizeInBits());
12351215 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1236 KnownZero, KnownOne, TLO, Depth+1))
1216 Known, TLO, Depth+1))
12371217 return true;
1238 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1239
1240 KnownZero |= ~InMask;
1218 assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
1219
1220 Known.Zero |= ~InMask;
12411221 break;
12421222 }
12431223 case ISD::BITCAST:
12751255 // of the highest bit demanded of them.
12761256 APInt LoMask = APInt::getLowBitsSet(BitWidth,
12771257 BitWidth - NewMask.countLeadingZeros());
1278 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1279 KnownOne2, TLO, Depth+1) ||
1280 SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1281 KnownOne2, TLO, Depth+1) ||
1258 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, Known2, TLO, Depth+1) ||
1259 SimplifyDemandedBits(Op.getOperand(1), LoMask, Known2, TLO, Depth+1) ||
12821260 // See if the operation should be performed at a smaller bit width.
12831261 ShrinkDemandedOp(Op, BitWidth, NewMask, TLO)) {
12841262 const SDNodeFlags *Flags = Op.getNode()->getFlags();
12991277 }
13001278 default:
13011279 // Just use computeKnownBits to compute output bits.
1302 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1280 TLO.DAG.computeKnownBits(Op, Known, Depth);
13031281 break;
13041282 }
13051283
13061284 // If we know the value of all of the demanded bits, return this as a
13071285 // constant.
1308 if (NewMask.isSubsetOf(KnownZero|KnownOne)) {
1286 if (NewMask.isSubsetOf(Known.Zero|Known.One)) {
13091287 // Avoid folding to a constant if any OpaqueConstant is involved.
13101288 const SDNode *N = Op.getNode();
13111289 for (SDNodeIterator I = SDNodeIterator::begin(N),
13161294 return false;
13171295 }
13181296 return TLO.CombineTo(Op,
1319 TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1297 TLO.DAG.getConstant(Known.One, dl, Op.getValueType()));
13201298 }
13211299
13221300 return false;
13231301 }
13241302
13251303 /// Determine which of the bits specified in Mask are known to be either zero or
1326 /// one and return them in the KnownZero/KnownOne bitsets.
1304 /// one and return them in the Known.
13271305 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1328 APInt &KnownZero,
1329 APInt &KnownOne,
1306 KnownBits &Known,
13301307 const APInt &DemandedElts,
13311308 const SelectionDAG &DAG,
13321309 unsigned Depth) const {
13361313 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
13371314 "Should use MaskedValueIsZero if you don't know whether Op"
13381315 " is a target node!");
1339 KnownZero.clearAllBits(); KnownOne.clearAllBits();
1316 Known.Zero.clearAllBits(); Known.One.clearAllBits();
13401317 }
13411318
13421319 /// This method can be implemented by targets that want to expose additional
1919 #include "llvm/IR/Intrinsics.h"
2020 #include "llvm/Support/Debug.h"
2121 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/KnownBits.h"
2223 #include "llvm/Support/MathExtras.h"
2324 #include "llvm/Support/raw_ostream.h"
2425
20772078 (void)BitWidth;
20782079 assert(BitWidth == 32 || BitWidth == 64);
20792080
2080 APInt KnownZero, KnownOne;
2081 CurDAG->computeKnownBits(Op, KnownZero, KnownOne);
2081 KnownBits Known;
2082 CurDAG->computeKnownBits(Op, Known);
20822083
20832084 // Non-zero in the sense that they're not provably zero, which is the key
20842085 // point if we want to use this value
2085 uint64_t NonZeroBits = (~KnownZero).getZExtValue();
2086 uint64_t NonZeroBits = (~Known.Zero).getZExtValue();
20862087
20872088 // Discard a constant AND mask if present. It's safe because the node will
20882089 // already have been factored into the computeKnownBits calculation above.
20892090 uint64_t AndImm;
20902091 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
2091 assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
2092 assert((~APInt(BitWidth, AndImm) & ~Known.Zero) == 0);
20922093 Op = Op.getOperand(0);
20932094 }
20942095
21572158
21582159 // Compute the Known Zero for the AND as this allows us to catch more general
21592160 // cases than just looking for AND with imm.
2160 APInt KnownZero, KnownOne;
2161 CurDAG->computeKnownBits(And, KnownZero, KnownOne);
2161 KnownBits Known;
2162 CurDAG->computeKnownBits(And, Known);
21622163
21632164 // Non-zero in the sense that they're not provably zero, which is the key
21642165 // point if we want to use this value.
2165 uint64_t NotKnownZero = (~KnownZero).getZExtValue();
2166 uint64_t NotKnownZero = (~Known.Zero).getZExtValue();
21662167
21672168 // The KnownZero mask must be a shifted mask (e.g., 1110..011, 11100..00).
2168 if (!isShiftedMask(KnownZero.getZExtValue(), VT))
2169 if (!isShiftedMask(Known.Zero.getZExtValue(), VT))
21692170 return false;
21702171
21712172 // The bits being inserted must only set those bits that are known to be zero.
22992300 // This allows to catch more general case than just looking for
23002301 // AND with imm. Indeed, simplify-demanded-bits may have removed
23012302 // the AND instruction because it proves it was useless.
2302 APInt KnownZero, KnownOne;
2303 CurDAG->computeKnownBits(OrOpd1Val, KnownZero, KnownOne);
2303 KnownBits Known;
2304 CurDAG->computeKnownBits(OrOpd1Val, Known);
23042305
23052306 // Check if there is enough room for the second operand to appear
23062307 // in the first one
23072308 APInt BitsToBeInserted =
2308 APInt::getBitsSet(KnownZero.getBitWidth(), DstLSB, DstLSB + Width);
2309
2310 if ((BitsToBeInserted & ~KnownZero) != 0)
2309 APInt::getBitsSet(Known.getBitWidth(), DstLSB, DstLSB + Width);
2310
2311 if ((BitsToBeInserted & ~Known.Zero) != 0)
23112312 continue;
23122313
23132314 // Set the first operand
6666 #include "llvm/Support/Compiler.h"
6767 #include "llvm/Support/Debug.h"
6868 #include "llvm/Support/ErrorHandling.h"
69 #include "llvm/Support/KnownBits.h"
6970 #include "llvm/Support/MathExtras.h"
7071 #include "llvm/Support/raw_ostream.h"
7172 #include "llvm/Target/TargetCallingConv.h"
928929 }
929930
930931 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
931 /// Mask are known to be either zero or one and return them in the
932 /// KnownZero/KnownOne bitsets.
932 /// Mask are known to be either zero or one and return them Known.
933933 void AArch64TargetLowering::computeKnownBitsForTargetNode(
934 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
934 const SDValue Op, KnownBits &Known,
935935 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
936936 switch (Op.getOpcode()) {
937937 default:
938938 break;
939939 case AArch64ISD::CSEL: {
940 APInt KnownZero2, KnownOne2;
941 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
942 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
943 KnownZero &= KnownZero2;
944 KnownOne &= KnownOne2;
940 KnownBits Known2;
941 DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
942 DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
943 Known.Zero &= Known2.Zero;
944 Known.One &= Known2.One;
945945 break;
946946 }
947947 case ISD::INTRINSIC_W_CHAIN: {
951951 default: return;
952952 case Intrinsic::aarch64_ldaxr:
953953 case Intrinsic::aarch64_ldxr: {
954 unsigned BitWidth = KnownOne.getBitWidth();
954 unsigned BitWidth = Known.getBitWidth();
955955 EVT VT = cast(Op)->getMemoryVT();
956956 unsigned MemBits = VT.getScalarSizeInBits();
957 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
957 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
958958 return;
959959 }
960960 }
973973 // bits larger than the element datatype. 32-bit or larget doesn't need
974974 // this as those are legal types and will be handled by isel directly.
975975 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
976 unsigned BitWidth = KnownZero.getBitWidth();
976 unsigned BitWidth = Known.getBitWidth();
977977 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
978978 assert(BitWidth >= 8 && "Unexpected width!");
979979 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
980 KnownZero |= Mask;
980 Known.Zero |= Mask;
981981 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
982982 assert(BitWidth >= 16 && "Unexpected width!");
983983 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
984 KnownZero |= Mask;
984 Known.Zero |= Mask;
985985 }
986986 break;
987987 } break;
94609460 TargetLowering::DAGCombinerInfo &DCI,
94619461 SelectionDAG &DAG) {
94629462 APInt DemandedMask = APInt::getLowBitsSet(64, 56);
9463 APInt KnownZero, KnownOne;
9463 KnownBits Known;
94649464 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
94659465 DCI.isBeforeLegalizeOps());
94669466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9467 if (TLI.SimplifyDemandedBits(Addr, DemandedMask, KnownZero, KnownOne, TLO)) {
9467 if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) {
94689468 DCI.CommitTargetLoweringOpt(TLO);
94699469 return true;
94709470 }
249249
250250 /// Determine which of the bits specified in Mask are known to be either zero
251251 /// or one and return them in the KnownZero/KnownOne bitsets.
252 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
253 APInt &KnownOne, const APInt &DemandedElts,
252 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
253 const APInt &DemandedElts,
254254 const SelectionDAG &DAG,
255255 unsigned Depth = 0) const override;
256256
2828 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
2929 #include "llvm/IR/DataLayout.h"
3030 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/Support/KnownBits.h"
3132 #include "SIInstrInfo.h"
3233 using namespace llvm;
3334
22922293 //===----------------------------------------------------------------------===//
22932294
22942295 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2295 APInt KnownZero, KnownOne;
2296 KnownBits Known;
22962297 EVT VT = Op.getValueType();
2297 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2298
2299 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2298 DAG.computeKnownBits(Op, Known);
2299
2300 return (VT.getSizeInBits() - Known.Zero.countLeadingOnes()) <= 24;
23002301 }
23012302
23022303 static bool isI24(SDValue Op, SelectionDAG &DAG) {
33573358 OffsetVal,
33583359 OffsetVal + WidthVal);
33593360
3360 APInt KnownZero, KnownOne;
3361 KnownBits Known;
33613362 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
33623363 !DCI.isBeforeLegalizeOps());
33633364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
33643365 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
3365 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
3366 KnownZero, KnownOne, TLO)) {
3366 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
33673367 DCI.CommitTargetLoweringOpt(TLO);
33683368 }
33693369 }
35733573 }
35743574
35753575 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
3576 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
3576 const SDValue Op, KnownBits &Known,
35773577 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
35783578
3579 unsigned BitWidth = KnownZero.getBitWidth();
3580 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
3581
3582 APInt KnownZero2;
3583 APInt KnownOne2;
3579 Known.Zero.clearAllBits(); Known.One.clearAllBits(); // Don't know anything.
3580
3581 KnownBits Known2;
35843582 unsigned Opc = Op.getOpcode();
35853583
35863584 switch (Opc) {
35883586 break;
35893587 case AMDGPUISD::CARRY:
35903588 case AMDGPUISD::BORROW: {
3591 KnownZero = APInt::getHighBitsSet(32, 31);
3589 Known.Zero = APInt::getHighBitsSet(32, 31);
35923590 break;
35933591 }
35943592
36013599 uint32_t Width = CWidth->getZExtValue() & 0x1f;
36023600
36033601 if (Opc == AMDGPUISD::BFE_U32)
3604 KnownZero = APInt::getHighBitsSet(32, 32 - Width);
3602 Known.Zero = APInt::getHighBitsSet(32, 32 - Width);
36053603
36063604 break;
36073605 }
36083606 case AMDGPUISD::FP_TO_FP16:
36093607 case AMDGPUISD::FP16_ZEXT: {
3610 unsigned BitWidth = KnownZero.getBitWidth();
3608 unsigned BitWidth = Known.getBitWidth();
36113609
36123610 // High bits are zero.
3613 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
3611 Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
36143612 break;
36153613 }
36163614 }
198198 /// either zero or one and return them in the \p KnownZero and \p KnownOne
199199 /// bitsets.
200200 void computeKnownBitsForTargetNode(const SDValue Op,
201 APInt &KnownZero,
202 APInt &KnownOne,
201 KnownBits &Known,
203202 const APInt &DemandedElts,
204203 const SelectionDAG &DAG,
205204 unsigned Depth = 0) const override;
6767 #include "llvm/Support/CommandLine.h"
6868 #include "llvm/Support/Compiler.h"
6969 #include "llvm/Support/ErrorHandling.h"
70 #include "llvm/Support/KnownBits.h"
7071 #include "llvm/Support/MathExtras.h"
7172 #include "llvm/Target/TargetCallingConv.h"
7273 #include "llvm/Target/TargetOptions.h"
47054706
47064707 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
47074708
4708 APInt KnownZero, KnownOne;
4709 KnownBits Known;
47094710 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
47104711 !DCI.isBeforeLegalizeOps());
47114712 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
47124713 if (TLI.ShrinkDemandedConstant(Src, Demanded, TLO) ||
4713 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
4714 TLI.SimplifyDemandedBits(Src, Demanded, Known, TLO)) {
47144715 DCI.CommitTargetLoweringOpt(TLO);
47154716 }
47164717
9090 #include "llvm/Support/Compiler.h"
9191 #include "llvm/Support/Debug.h"
9292 #include "llvm/Support/ErrorHandling.h"
93 #include "llvm/Support/KnownBits.h"
9394 #include "llvm/Support/MathExtras.h"
9495 #include "llvm/Support/raw_ostream.h"
9596 #include "llvm/Target/TargetInstrInfo.h"
1175711758
1175811759 // Lastly, can we determine that the bits defined by OrCI
1175911760 // are zero in Y?
11760 APInt KnownZero, KnownOne;
11761 DAG.computeKnownBits(Y, KnownZero, KnownOne);
11762 if ((OrCI & KnownZero) != OrCI)
11761 KnownBits Known;
11762 DAG.computeKnownBits(Y, Known);
11763 if ((OrCI & Known.Zero) != OrCI)
1176311764 return SDValue();
1176411765
1176511766 // OK, we can do the combine.
1189711898 }
1189811899
1189911900 if (Res.getNode()) {
11900 APInt KnownZero, KnownOne;
11901 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
11901 KnownBits Known;
11902 DAG.computeKnownBits(SDValue(N,0), Known);
1190211903 // Capture demanded bits information that would be otherwise lost.
11903 if (KnownZero == 0xfffffffe)
11904 if (Known.Zero == 0xfffffffe)
1190411905 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
1190511906 DAG.getValueType(MVT::i1));
11906 else if (KnownZero == 0xffffff00)
11907 else if (Known.Zero == 0xffffff00)
1190711908 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
1190811909 DAG.getValueType(MVT::i8));
11909 else if (KnownZero == 0xffff0000)
11910 else if (Known.Zero == 0xffff0000)
1191011911 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
1191111912 DAG.getValueType(MVT::i16));
1191211913 }
1259512596 }
1259612597
1259712598 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
12598 APInt &KnownZero,
12599 APInt &KnownOne,
12599 KnownBits &Known,
1260012600 const APInt &DemandedElts,
1260112601 const SelectionDAG &DAG,
1260212602 unsigned Depth) const {
12603 unsigned BitWidth = KnownOne.getBitWidth();
12604 KnownZero = KnownOne = APInt(BitWidth, 0);
12603 unsigned BitWidth = Known.getBitWidth();
12604 Known.Zero.clearAllBits(); Known.One.clearAllBits();
1260512605 switch (Op.getOpcode()) {
1260612606 default: break;
1260712607 case ARMISD::ADDC:
1261112611 // These nodes' second result is a boolean
1261212612 if (Op.getResNo() == 0)
1261312613 break;
12614 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12614 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
1261512615 break;
1261612616 case ARMISD::CMOV: {
1261712617 // Bits are known zero/one if known on the LHS and RHS.
12618 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
12619 if (KnownZero == 0 && KnownOne == 0) return;
12620
12621 APInt KnownZeroRHS, KnownOneRHS;
12622 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
12623 KnownZero &= KnownZeroRHS;
12624 KnownOne &= KnownOneRHS;
12618 DAG.computeKnownBits(Op.getOperand(0), Known, Depth+1);
12619 if (Known.Zero == 0 && Known.One == 0) return;
12620
12621 KnownBits KnownRHS;
12622 DAG.computeKnownBits(Op.getOperand(1), KnownRHS, Depth+1);
12623 Known.Zero &= KnownRHS.Zero;
12624 Known.One &= KnownRHS.One;
1262512625 return;
1262612626 }
1262712627 case ISD::INTRINSIC_W_CHAIN: {
1263312633 case Intrinsic::arm_ldrex: {
1263412634 EVT VT = cast(Op)->getMemoryVT();
1263512635 unsigned MemBits = VT.getScalarSizeInBits();
12636 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
12636 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
1263712637 return;
1263812638 }
1263912639 }
1264112641 case ARMISD::BFI: {
1264212642 // Conservatively, we can recurse down the first operand
1264312643 // and just mask out all affected bits.
12644 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
12644 DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);
1264512645
1264612646 // The operand to BFI is already a mask suitable for removing the bits it
1264712647 // sets.
1264812648 ConstantSDNode *CI = cast(Op.getOperand(2));
1264912649 const APInt &Mask = CI->getAPIntValue();
12650 KnownZero &= Mask;
12651 KnownOne &= Mask;
12650 Known.Zero &= Mask;
12651 Known.One &= Mask;
1265212652 return;
1265312653 }
1265412654 }
349349 SDValue &Offset, ISD::MemIndexedMode &AM,
350350 SelectionDAG &DAG) const override;
351351
352 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
353 APInt &KnownOne,
352 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
354353 const APInt &DemandedElts,
355354 const SelectionDAG &DAG,
356355 unsigned Depth) const override;
4848 #include "llvm/Support/Compiler.h"
4949 #include "llvm/Support/Debug.h"
5050 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/KnownBits.h"
5152 #include "llvm/Support/MathExtras.h"
5253 #include "llvm/Support/raw_ostream.h"
5354 #include "llvm/Target/TargetInstrInfo.h"
541542 SDValue Op1 = N->getOperand(1);
542543 SDLoc dl(N);
543544
544 APInt LKZ, LKO, RKZ, RKO;
545 CurDAG->computeKnownBits(Op0, LKZ, LKO);
546 CurDAG->computeKnownBits(Op1, RKZ, RKO);
547
548 unsigned TargetMask = LKZ.getZExtValue();
549 unsigned InsertMask = RKZ.getZExtValue();
545 KnownBits LKnown, RKnown;
546 CurDAG->computeKnownBits(Op0, LKnown);
547 CurDAG->computeKnownBits(Op1, RKnown);
548
549 unsigned TargetMask = LKnown.Zero.getZExtValue();
550 unsigned InsertMask = RKnown.Zero.getZExtValue();
550551
551552 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
552553 unsigned Op0Opc = Op0.getOpcode();
589590 // The AND mask might not be a constant, and we need to make sure that
590591 // if we're going to fold the masking with the insert, all bits not
591592 // know to be zero in the mask are known to be one.
592 APInt MKZ, MKO;
593 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
594 bool CanFoldMask = InsertMask == MKO.getZExtValue();
593 KnownBits MKnown;
594 CurDAG->computeKnownBits(Op1.getOperand(1), MKnown);
595 bool CanFoldMask = InsertMask == MKnown.One.getZExtValue();
595596
596597 unsigned SHOpc = Op1.getOperand(0).getOpcode();
597598 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
27712772 short Imm;
27722773 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
27732774 isIntS16Immediate(N->getOperand(1), Imm)) {
2774 APInt LHSKnownZero, LHSKnownOne;
2775 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2775 KnownBits LHSKnown;
2776 CurDAG->computeKnownBits(N->getOperand(0), LHSKnown);
27762777
27772778 // If this is equivalent to an add, then we can fold it with the
27782779 // FrameIndex calculation.
2779 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
2780 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
27802781 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
27812782 return;
27822783 }
7878 #include "llvm/Support/Debug.h"
7979 #include "llvm/Support/ErrorHandling.h"
8080 #include "llvm/Support/Format.h"
81 #include "llvm/Support/KnownBits.h"
8182 #include "llvm/Support/MathExtras.h"
8283 #include "llvm/Support/raw_ostream.h"
8384 #include "llvm/Target/TargetInstrInfo.h"
18461847 // If this is an or of disjoint bitfields, we can codegen this as an add
18471848 // (for better address arithmetic) if the LHS and RHS of the OR are provably
18481849 // disjoint.
1849 APInt LHSKnownZero, LHSKnownOne;
1850 APInt RHSKnownZero, RHSKnownOne;
1851 DAG.computeKnownBits(N.getOperand(0),
1852 LHSKnownZero, LHSKnownOne);
1853
1854 if (LHSKnownZero.getBoolValue()) {
1855 DAG.computeKnownBits(N.getOperand(1),
1856 RHSKnownZero, RHSKnownOne);
1850 KnownBits LHSKnown, RHSKnown;
1851 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
1852
1853 if (LHSKnown.Zero.getBoolValue()) {
1854 DAG.computeKnownBits(N.getOperand(1), RHSKnown);
18571855 // If all of the bits are known zero on the LHS or RHS, the add won't
18581856 // carry.
1859 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1857 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
18601858 Base = N.getOperand(0);
18611859 Index = N.getOperand(1);
18621860 return true;
19521950 // If this is an or of disjoint bitfields, we can codegen this as an add
19531951 // (for better address arithmetic) if the LHS and RHS of the OR are
19541952 // provably disjoint.
1955 APInt LHSKnownZero, LHSKnownOne;
1956 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1957
1958 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1953 KnownBits LHSKnown;
1954 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
1955
1956 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
19591957 // If all of the bits are known zero on the LHS or RHS, the add won't
19601958 // carry.
19611959 if (FrameIndexSDNode *FI =
1031710315 } else {
1031810316 // This is neither a signed nor an unsigned comparison, just make sure
1031910317 // that the high bits are equal.
10320 APInt Op1Zero, Op1One;
10321 APInt Op2Zero, Op2One;
10322 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
10323 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
10318 KnownBits Op1Known, Op2Known;
10319 DAG.computeKnownBits(N->getOperand(0), Op1Known);
10320 DAG.computeKnownBits(N->getOperand(1), Op2Known);
1032410321
1032510322 // We don't really care about what is known about the first bit (if
1032610323 // anything), so clear it in all masks prior to comparing them.
10327 Op1Zero.clearBit(0); Op1One.clearBit(0);
10328 Op2Zero.clearBit(0); Op2One.clearBit(0);
10329
10330 if (Op1Zero != Op2Zero || Op1One != Op2One)
10324 Op1Known.Zero.clearBit(0); Op1Known.One.clearBit(0);
10325 Op2Known.Zero.clearBit(0); Op2Known.One.clearBit(0);
10326
10327 if (Op1Known.Zero != Op2Known.Zero || Op1Known.One != Op2Known.One)
1033110328 return SDValue();
1033210329 }
1033310330 }
1201412011 //===----------------------------------------------------------------------===//
1201512012
1201612013 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
12017 APInt &KnownZero,
12018 APInt &KnownOne,
12014 KnownBits &Known,
1201912015 const APInt &DemandedElts,
1202012016 const SelectionDAG &DAG,
1202112017 unsigned Depth) const {
12022 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
12018 Known.Zero.clearAllBits(); Known.One.clearAllBits();
1202312019 switch (Op.getOpcode()) {
1202412020 default: break;
1202512021 case PPCISD::LBRX: {
1202612022 // lhbrx is known to have the top bits cleared out.
1202712023 if (cast(Op.getOperand(2))->getVT() == MVT::i16)
12028 KnownZero = 0xFFFF0000;
12024 Known.Zero = 0xFFFF0000;
1202912025 break;
1203012026 }
1203112027 case ISD::INTRINSIC_WO_CHAIN: {
1204712043 case Intrinsic::ppc_altivec_vcmpgtuh_p:
1204812044 case Intrinsic::ppc_altivec_vcmpgtuw_p:
1204912045 case Intrinsic::ppc_altivec_vcmpgtud_p:
12050 KnownZero = ~1U; // All bits but the low one are known to be zero.
12046 Known.Zero = ~1U; // All bits but the low one are known to be zero.
1205112047 break;
1205212048 }
1205312049 }
605605 SelectionDAG &DAG) const override;
606606
607607 void computeKnownBitsForTargetNode(const SDValue Op,
608 APInt &KnownZero,
609 APInt &KnownOne,
608 KnownBits &Known,
610609 const APInt &DemandedElts,
611610 const SelectionDAG &DAG,
612611 unsigned Depth = 0) const override;
2929 #include "llvm/IR/Function.h"
3030 #include "llvm/IR/Module.h"
3131 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/KnownBits.h"
3233 using namespace llvm;
3334
3435
18741875 /// combiner.
18751876 void SparcTargetLowering::computeKnownBitsForTargetNode
18761877 (const SDValue Op,
1877 APInt &KnownZero,
1878 APInt &KnownOne,
1878 KnownBits &Known,
18791879 const APInt &DemandedElts,
18801880 const SelectionDAG &DAG,
18811881 unsigned Depth) const {
1882 APInt KnownZero2, KnownOne2;
1883 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1882 KnownBits Known2;
1883 Known.Zero.clearAllBits(); Known.One.clearAllBits();
18841884
18851885 switch (Op.getOpcode()) {
18861886 default: break;
18871887 case SPISD::SELECT_ICC:
18881888 case SPISD::SELECT_XCC:
18891889 case SPISD::SELECT_FCC:
1890 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1891 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1890 DAG.computeKnownBits(Op.getOperand(1), Known, Depth+1);
1891 DAG.computeKnownBits(Op.getOperand(0), Known2, Depth+1);
18921892
18931893 // Only known if known in both the LHS and RHS.
1894 KnownOne &= KnownOne2;
1895 KnownZero &= KnownZero2;
1894 Known.One &= Known2.One;
1895 Known.Zero &= Known2.Zero;
18961896 break;
18971897 }
18981898 }
6565 /// in Mask are known to be either zero or one and return them in the
6666 /// KnownZero/KnownOne bitsets.
6767 void computeKnownBitsForTargetNode(const SDValue Op,
68 APInt &KnownZero,
69 APInt &KnownOne,
68 KnownBits &Known,
7069 const APInt &DemandedElts,
7170 const SelectionDAG &DAG,
7271 unsigned Depth = 0) const override;
1414 #include "llvm/Analysis/AliasAnalysis.h"
1515 #include "llvm/CodeGen/SelectionDAGISel.h"
1616 #include "llvm/Support/Debug.h"
17 #include "llvm/Support/KnownBits.h"
1718 #include "llvm/Support/raw_ostream.h"
1819
1920 using namespace llvm;
710711 // The inner check covers all cases but is more expensive.
711712 uint64_t Used = allOnes(Op.getValueSizeInBits());
712713 if (Used != (AndMask | InsertMask)) {
713 APInt KnownZero, KnownOne;
714 CurDAG->computeKnownBits(Op.getOperand(0), KnownZero, KnownOne);
715 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
714 KnownBits Known;
715 CurDAG->computeKnownBits(Op.getOperand(0), Known);
716 if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue()))
716717 return false;
717718 }
718719
769770 // If some bits of Input are already known zeros, those bits will have
770771 // been removed from the mask. See if adding them back in makes the
771772 // mask suitable.
772 APInt KnownZero, KnownOne;
773 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
774 Mask |= KnownZero.getZExtValue();
773 KnownBits Known;
774 CurDAG->computeKnownBits(Input, Known);
775 Mask |= Known.Zero.getZExtValue();
775776 if (!refineRxSBGMask(RxSBG, Mask))
776777 return false;
777778 }
793794 // If some bits of Input are already known ones, those bits will have
794795 // been removed from the mask. See if adding them back in makes the
795796 // mask suitable.
796 APInt KnownZero, KnownOne;
797 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
798 Mask &= ~KnownOne.getZExtValue();
797 KnownBits Known;
798 CurDAG->computeKnownBits(Input, Known);
799 Mask &= ~Known.One.getZExtValue();
799800 if (!refineRxSBGMask(RxSBG, Mask))
800801 return false;
801802 }
1919 #include "llvm/CodeGen/MachineInstrBuilder.h"
2020 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/IR/Intrinsics.h"
2223 #include "llvm/Support/CommandLine.h"
23 #include "llvm/IR/Intrinsics.h"
24 #include "llvm/Support/KnownBits.h"
2425 #include
2526
2627 using namespace llvm;
30653066
30663067 // Get the known-zero masks for each operand.
30673068 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3068 APInt KnownZero[2], KnownOne[2];
3069 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
3070 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
3069 KnownBits Known[2];
3070 DAG.computeKnownBits(Ops[0], Known[0]);
3071 DAG.computeKnownBits(Ops[1], Known[1]);
30713072
30723073 // See if the upper 32 bits of one operand and the lower 32 bits of the
30733074 // other are known zero. They are the low and high operands respectively.
3074 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
3075 KnownZero[1].getZExtValue() };
3075 uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
3076 Known[1].Zero.getZExtValue() };
30763077 unsigned High, Low;
30773078 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
30783079 High = 1, Low = 0;
31573158 }
31583159
31593160 // Get the known-zero mask for the operand.
3160 APInt KnownZero, KnownOne;
3161 DAG.computeKnownBits(Op, KnownZero, KnownOne);
3162 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
3161 KnownBits Known;
3162 DAG.computeKnownBits(Op, Known);
3163 unsigned NumSignificantBits = (~Known.Zero).getActiveBits();
31633164 if (NumSignificantBits == 0)
31643165 return DAG.getConstant(0, DL, VT);
31653166
3030 #include "llvm/IR/Type.h"
3131 #include "llvm/Support/Debug.h"
3232 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/KnownBits.h"
3334 #include "llvm/Support/MathExtras.h"
3435 #include "llvm/Support/raw_ostream.h"
3536 #include "llvm/Target/TargetMachine.h"
10691070 }
10701071 APInt MaskedHighBits =
10711072 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
1072 APInt KnownZero, KnownOne;
1073 DAG.computeKnownBits(X, KnownZero, KnownOne);
1074 if (MaskedHighBits != KnownZero) return true;
1073 KnownBits Known;
1074 DAG.computeKnownBits(X, Known);
1075 if (MaskedHighBits != Known.Zero) return true;
10751076
10761077 // We've identified a pattern that can be transformed into a single shift
10771078 // and an addressing mode. Make it so.
5151 #include "llvm/Support/CommandLine.h"
5252 #include "llvm/Support/Debug.h"
5353 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/KnownBits.h"
5455 #include "llvm/Support/MathExtras.h"
5556 #include "llvm/Target/TargetLowering.h"
5657 #include "llvm/Target/TargetOptions.h"
1679816799 unsigned BitWidth = Op0.getValueSizeInBits();
1679916800 unsigned AndBitWidth = And.getValueSizeInBits();
1680016801 if (BitWidth > AndBitWidth) {
16801 APInt Zeros, Ones;
16802 DAG.computeKnownBits(Op0, Zeros, Ones);
16803 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
16802 KnownBits Known;
16803 DAG.computeKnownBits(Op0, Known);
16804 if (Known.Zero.countLeadingOnes() < BitWidth - AndBitWidth)
1680416805 return SDValue();
1680516806 }
1680616807 LHS = Op1;
2666626667 //===----------------------------------------------------------------------===//
2666726668
2666826669 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
26669 APInt &KnownZero,
26670 APInt &KnownOne,
26670 KnownBits &Known,
2667126671 const APInt &DemandedElts,
2667226672 const SelectionDAG &DAG,
2667326673 unsigned Depth) const {
26674 unsigned BitWidth = KnownZero.getBitWidth();
26674 unsigned BitWidth = Known.getBitWidth();
2667526675 unsigned Opc = Op.getOpcode();
2667626676 EVT VT = Op.getValueType();
2667726677 assert((Opc >= ISD::BUILTIN_OP_END ||
2668126681 "Should use MaskedValueIsZero if you don't know whether Op"
2668226682 " is a target node!");
2668326683
26684 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
26684 Known = KnownBits(BitWidth); // Don't know anything.
2668526685 switch (Opc) {
2668626686 default: break;
2668726687 case X86ISD::ADD:
2670026700 break;
2670126701 LLVM_FALLTHROUGH;
2670226702 case X86ISD::SETCC:
26703 KnownZero.setBits(1, BitWidth);
26703 Known.Zero.setBits(1, BitWidth);
2670426704 break;
2670526705 case X86ISD::MOVMSK: {
2670626706 unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();
26707 KnownZero.setBits(NumLoBits, BitWidth);
26707 Known.Zero.setBits(NumLoBits, BitWidth);
2670826708 break;
2670926709 }
2671026710 case X86ISD::VSHLI:
2671126711 case X86ISD::VSRLI: {
2671226712 if (auto *ShiftImm = dyn_cast(Op.getOperand(1))) {
2671326713 if (ShiftImm->getAPIntValue().uge(VT.getScalarSizeInBits())) {
26714 KnownZero.setAllBits();
26714 Known.Zero.setAllBits();
2671526715 break;
2671626716 }
2671726717
26718 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
26718 DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);
2671926719 unsigned ShAmt = ShiftImm->getZExtValue();
2672026720 if (Opc == X86ISD::VSHLI) {
26721 KnownZero <<= ShAmt;
26722 KnownOne <<= ShAmt;
26721 Known.Zero <<= ShAmt;
26722 Known.One <<= ShAmt;
2672326723 // Low bits are known zero.
26724 KnownZero.setLowBits(ShAmt);
26724 Known.Zero.setLowBits(ShAmt);
2672526725 } else {
26726 KnownZero.lshrInPlace(ShAmt);
26727 KnownOne.lshrInPlace(ShAmt);
26726 Known.Zero.lshrInPlace(ShAmt);
26727 Known.One.lshrInPlace(ShAmt);
2672826728 // High bits are known zero.
26729 KnownZero.setHighBits(ShAmt);
26729 Known.Zero.setHighBits(ShAmt);
2673026730 }
2673126731 }
2673226732 break;
2674026740 unsigned InBitWidth = SrcVT.getScalarSizeInBits();
2674126741 assert(InNumElts >= NumElts && "Illegal VZEXT input");
2674226742
26743 KnownZero = KnownOne = APInt(InBitWidth, 0);
26743 Known = KnownBits(InBitWidth);
2674426744 APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);
26745 DAG.computeKnownBits(N0, KnownZero, KnownOne, DemandedSrcElts, Depth + 1);
26746 KnownOne = KnownOne.zext(BitWidth);
26747 KnownZero = KnownZero.zext(BitWidth);
26748 KnownZero.setBits(InBitWidth, BitWidth);
26745 DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);
26746 Known.One = Known.One.zext(BitWidth);
26747 Known.Zero = Known.Zero.zext(BitWidth);
26748 Known.Zero.setBits(InBitWidth, BitWidth);
2674926749 break;
2675026750 }
2675126751 }
3020530205
3020630206 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
3020730207 APInt DemandedMask(APInt::getSignMask(BitWidth));
30208 APInt KnownZero, KnownOne;
30208 KnownBits Known;
3020930209 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
3021030210 DCI.isBeforeLegalizeOps());
3021130211 if (TLI.ShrinkDemandedConstant(Cond, DemandedMask, TLO) ||
30212 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
30213 TLO)) {
30212 TLI.SimplifyDemandedBits(Cond, DemandedMask, Known, TLO)) {
3021430213 // If we changed the computation somewhere in the DAG, this change will
3021530214 // affect all users of Cond. Make sure it is fine and update all the nodes
3021630215 // so that we do not use the generic VSELECT anymore. Otherwise, we may
3377333772 if (Op1.hasOneUse()) {
3377433773 unsigned BitWidth = Op1.getValueSizeInBits();
3377533774 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
33776 APInt KnownZero, KnownOne;
33775 KnownBits Known;
3377733776 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
3377833777 !DCI.isBeforeLegalizeOps());
3377933778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3378033779 if (TLI.ShrinkDemandedConstant(Op1, DemandedMask, TLO) ||
33781 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
33780 TLI.SimplifyDemandedBits(Op1, DemandedMask, Known, TLO))
3378233781 DCI.CommitTargetLoweringOpt(TLO);
3378333782 }
3378433783 return SDValue();
827827 /// Determine which of the bits specified in Mask are known to be either
828828 /// zero or one and return them in the KnownZero/KnownOne bitsets.
829829 void computeKnownBitsForTargetNode(const SDValue Op,
830 APInt &KnownZero,
831 APInt &KnownOne,
830 KnownBits &Known,
832831 const APInt &DemandedElts,
833832 const SelectionDAG &DAG,
834833 unsigned Depth = 0) const override;
12701270 if (ConstantSDNode *CN = dyn_cast(N->getOperand(1)))
12711271 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
12721272
1273 APInt KnownZero0, KnownOne0;
1274 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1275 APInt KnownZero1, KnownOne1;
1276 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1277 return (~KnownZero0 & ~KnownZero1) == 0;
1273 KnownBits Known0;
1274 CurDAG->computeKnownBits(N->getOperand(0), Known0, 0);
1275 KnownBits Known1;
1276 CurDAG->computeKnownBits(N->getOperand(1), Known1, 0);
1277 return (~Known0.Zero & ~Known1.Zero) == 0;
12781278 }]>;
12791279
12801280
3333 #include "llvm/IR/Intrinsics.h"
3434 #include "llvm/Support/Debug.h"
3535 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/KnownBits.h"
3637 #include "llvm/Support/raw_ostream.h"
3738 #include
3839
405406
406407 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
407408 {
408 APInt KnownZero, KnownOne;
409 DAG.computeKnownBits(Value, KnownZero, KnownOne);
410 return KnownZero.countTrailingOnes() >= 2;
409 KnownBits Known;
410 DAG.computeKnownBits(Value, Known);
411 return Known.Zero.countTrailingOnes() >= 2;
411412 }
412413
413414 SDValue XCoreTargetLowering::
16001601 if (OutVal.hasOneUse()) {
16011602 unsigned BitWidth = OutVal.getValueSizeInBits();
16021603 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
1603 APInt KnownZero, KnownOne;
1604 KnownBits Known;
16041605 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16051606 !DCI.isBeforeLegalizeOps());
16061607 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16071608 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) ||
1608 TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne,
1609 TLO))
1609 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO))
16101610 DCI.CommitTargetLoweringOpt(TLO);
16111611 }
16121612 break;
16171617 if (Time.hasOneUse()) {
16181618 unsigned BitWidth = Time.getValueSizeInBits();
16191619 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
1620 APInt KnownZero, KnownOne;
1620 KnownBits Known;
16211621 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16221622 !DCI.isBeforeLegalizeOps());
16231623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16241624 if (TLI.ShrinkDemandedConstant(Time, DemandedMask, TLO) ||
1625 TLI.SimplifyDemandedBits(Time, DemandedMask, KnownZero, KnownOne,
1626 TLO))
1625 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO))
16271626 DCI.CommitTargetLoweringOpt(TLO);
16281627 }
16291628 break;
16541653 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
16551654 // low bit set
16561655 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1657 APInt KnownZero, KnownOne;
1656 KnownBits Known;
16581657 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
16591658 VT.getSizeInBits() - 1);
1660 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1661 if ((KnownZero & Mask) == Mask) {
1659 DAG.computeKnownBits(N2, Known);
1660 if ((Known.Zero & Mask) == Mask) {
16621661 SDValue Carry = DAG.getConstant(0, dl, VT);
16631662 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
16641663 SDValue Ops[] = { Result, Carry };
16771676
16781677 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
16791678 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1680 APInt KnownZero, KnownOne;
1679 KnownBits Known;
16811680 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
16821681 VT.getSizeInBits() - 1);
1683 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1684 if ((KnownZero & Mask) == Mask) {
1682 DAG.computeKnownBits(N2, Known);
1683 if ((Known.Zero & Mask) == Mask) {
16851684 SDValue Borrow = N2;
16861685 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
16871686 DAG.getConstant(0, dl, VT), N2);
16931692 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1