llvm.org GIT mirror llvm / 8b2b8a1
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8 Stephen Lin 6 years ago
937 changed file(s) with 9063 addition(s) and 9063 deletion(s). Raw diff Collapse all Expand all
88
99 ; Add pure 12-bit immediates:
1010 define void @add_small() {
11 ; CHECK: add_small:
11 ; CHECK-LABEL: add_small:
1212
1313 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
1414 %val32 = load i32* @var_i32
2525
2626 ; Add 12-bit immediates, shifted left by 12 bits
2727 define void @add_med() {
28 ; CHECK: add_med:
28 ; CHECK-LABEL: add_med:
2929
3030 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
3131 %val32 = load i32* @var_i32
4242
4343 ; Subtract 12-bit immediates
4444 define void @sub_small() {
45 ; CHECK: sub_small:
45 ; CHECK-LABEL: sub_small:
4646
4747 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
4848 %val32 = load i32* @var_i32
5959
6060 ; Subtract 12-bit immediates, shifted left by 12 bits
6161 define void @sub_med() {
62 ; CHECK: sub_med:
62 ; CHECK-LABEL: sub_med:
6363
6464 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
6565 %val32 = load i32* @var_i32
55 @var64 = global i64 0
66
77 define void @addsub_i8rhs() {
8 ; CHECK: addsub_i8rhs:
8 ; CHECK-LABEL: addsub_i8rhs:
99 %val8_tmp = load i8* @var8
1010 %lhs32 = load i32* @var32
1111 %lhs64 = load i64* @var64
8080 }
8181
8282 define void @addsub_i16rhs() {
83 ; CHECK: addsub_i16rhs:
83 ; CHECK-LABEL: addsub_i16rhs:
8484 %val16_tmp = load i16* @var16
8585 %lhs32 = load i32* @var32
8686 %lhs64 = load i64* @var64
158158 ; example), but the remaining instructions are probably not idiomatic
159159 ; in the face of "add/sub (shifted register)" so I don't intend to.
160160 define void @addsub_i32rhs() {
161 ; CHECK: addsub_i32rhs:
161 ; CHECK-LABEL: addsub_i32rhs:
162162 %val32_tmp = load i32* @var32
163163 %lhs64 = load i64* @var64
164164
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
11
22 define i32 @foo(i32* %var, i1 %cond) {
3 ; CHECK: foo:
3 ; CHECK-LABEL: foo:
44 br i1 %cond, label %atomic_ver, label %simple_ver
55 simple_ver:
66 %oldval = load i32* %var
55 ; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
66
77 define i32 @get_globalvar() {
8 ; CHECK: get_globalvar:
8 ; CHECK-LABEL: get_globalvar:
99
1010 %val = load i32* @var
1111 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
1818 }
1919
2020 define i32* @get_globalvaraddr() {
21 ; CHECK: get_globalvaraddr:
21 ; CHECK-LABEL: get_globalvaraddr:
2222
2323 %val = load i32* @var
2424 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
3232 @hiddenvar = hidden global i32 0
3333
3434 define i32 @get_hiddenvar() {
35 ; CHECK: get_hiddenvar:
35 ; CHECK-LABEL: get_hiddenvar:
3636
3737 %val = load i32* @hiddenvar
3838 ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
4444 }
4545
4646 define i32* @get_hiddenvaraddr() {
47 ; CHECK: get_hiddenvaraddr:
47 ; CHECK-LABEL: get_hiddenvaraddr:
4848
4949 %val = load i32* @hiddenvar
5050 ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
5656 }
5757
5858 define void()* @get_func() {
59 ; CHECK: get_func:
59 ; CHECK-LABEL: get_func:
6060
6161 ret void()* bitcast(void()*()* @get_func to void()*)
6262 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
55 %struct.foo = type { i8, [2 x i8], i8 }
66
77 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
8 ; CHECK: from_clang:
8 ; CHECK-LABEL: from_clang:
99 ; CHECK: bfi w0, w1, #3, #4
1010 ; CHECK-NEXT: ret
1111
22 @stored_label = global i8* null
33
44 define void @foo() {
5 ; CHECK: foo:
5 ; CHECK-LABEL: foo:
66 %lab = load i8** @stored_label
77 indirectbr i8* %lab, [label %otherlab, label %retlab]
88 ; CHECK: adrp {{x[0-9]+}}, stored_label
22 @var = global float 0.0
33
44 define void @foo() {
5 ; CHECK: foo:
5 ; CHECK-LABEL: foo:
66
77 ; CHECK: stp d14, d15, [sp
88 ; CHECK: stp d12, d13, [sp
55 @var64 = global i64 0
66
77 define i8* @global_addr() {
8 ; CHECK: global_addr:
8 ; CHECK-LABEL: global_addr:
99 ret i8* @var8
1010 ; The movz/movk calculation should end up returned directly in x0.
1111 ; CHECK: movz x0, #:abs_g3:var8
1616 }
1717
1818 define i8 @global_i8() {
19 ; CHECK: global_i8:
19 ; CHECK-LABEL: global_i8:
2020 %val = load i8* @var8
2121 ret i8 %val
2222 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
2727 }
2828
2929 define i16 @global_i16() {
30 ; CHECK: global_i16:
30 ; CHECK-LABEL: global_i16:
3131 %val = load i16* @var16
3232 ret i16 %val
3333 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
3838 }
3939
4040 define i32 @global_i32() {
41 ; CHECK: global_i32:
41 ; CHECK-LABEL: global_i32:
4242 %val = load i32* @var32
4343 ret i32 %val
4444 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
4949 }
5050
5151 define i64 @global_i64() {
52 ; CHECK: global_i64:
52 ; CHECK-LABEL: global_i64:
5353 %val = load i64* @var64
5454 ret i64 %val
5555 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
33 @var64 = global i64 0
44
55 define void @foo() {
6 ; CHECK: foo:
6 ; CHECK-LABEL: foo:
77
88 %val1 = load volatile i32* @var32
99 %tst1 = icmp eq i32 %val1, 0
33 @var64 = global i64 0
44
55 define void @rev_i32() {
6 ; CHECK: rev_i32:
6 ; CHECK-LABEL: rev_i32:
77 %val0_tmp = load i32* @var32
88 %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
99 ; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
1212 }
1313
1414 define void @rev_i64() {
15 ; CHECK: rev_i64:
15 ; CHECK-LABEL: rev_i64:
1616 %val0_tmp = load i64* @var64
1717 %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
1818 ; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
2121 }
2222
2323 define void @rev32_i64() {
24 ; CHECK: rev32_i64:
24 ; CHECK-LABEL: rev32_i64:
2525 %val0_tmp = load i64* @var64
2626 %val1_tmp = shl i64 %val0_tmp, 32
2727 %val5_tmp = sub i64 64, 32
3434 }
3535
3636 define void @rev16_i32() {
37 ; CHECK: rev16_i32:
37 ; CHECK-LABEL: rev16_i32:
3838 %val0_tmp = load i32* @var32
3939 %val1_tmp = shl i32 %val0_tmp, 16
4040 %val2_tmp = lshr i32 %val0_tmp, 16
4646 }
4747
4848 define void @clz_zerodef_i32() {
49 ; CHECK: clz_zerodef_i32:
49 ; CHECK-LABEL: clz_zerodef_i32:
5050 %val0_tmp = load i32* @var32
5151 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
5252 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
5555 }
5656
5757 define void @clz_zerodef_i64() {
58 ; CHECK: clz_zerodef_i64:
58 ; CHECK-LABEL: clz_zerodef_i64:
5959 %val0_tmp = load i64* @var64
6060 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
6161 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
6464 }
6565
6666 define void @clz_zeroundef_i32() {
67 ; CHECK: clz_zeroundef_i32:
67 ; CHECK-LABEL: clz_zeroundef_i32:
6868 %val0_tmp = load i32* @var32
6969 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
7070 ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
7373 }
7474
7575 define void @clz_zeroundef_i64() {
76 ; CHECK: clz_zeroundef_i64:
76 ; CHECK-LABEL: clz_zeroundef_i64:
7777 %val0_tmp = load i64* @var64
7878 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
7979 ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
8282 }
8383
8484 define void @cttz_zerodef_i32() {
85 ; CHECK: cttz_zerodef_i32:
85 ; CHECK-LABEL: cttz_zerodef_i32:
8686 %val0_tmp = load i32* @var32
8787 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
8888 ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
9292 }
9393
9494 define void @cttz_zerodef_i64() {
95 ; CHECK: cttz_zerodef_i64:
95 ; CHECK-LABEL: cttz_zerodef_i64:
9696 %val0_tmp = load i64* @var64
9797 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
9898 ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
102102 }
103103
104104 define void @cttz_zeroundef_i32() {
105 ; CHECK: cttz_zeroundef_i32:
105 ; CHECK-LABEL: cttz_zeroundef_i32:
106106 %val0_tmp = load i32* @var32
107107 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
108108 ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
112112 }
113113
114114 define void @cttz_zeroundef_i64() {
115 ; CHECK: cttz_zeroundef_i64:
115 ; CHECK-LABEL: cttz_zeroundef_i64:
116116 %val0_tmp = load i64* @var64
117117 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
118118 ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
124124 ; These two are just compilation tests really: the operation's set to Expand in
125125 ; ISelLowering.
126126 define void @ctpop_i32() {
127 ; CHECK: ctpop_i32:
127 ; CHECK-LABEL: ctpop_i32:
128128 %val0_tmp = load i32* @var32
129129 %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
130130 store volatile i32 %val4_tmp, i32* @var32
132132 }
133133
134134 define void @ctpop_i64() {
135 ; CHECK: ctpop_i64:
135 ; CHECK-LABEL: ctpop_i64:
136136 %val0_tmp = load i64* @var64
137137 %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
138138 store volatile i64 %val4_tmp, i64* @var64
55 @var64_1 = global i64 0
66
77 define void @rorv_i64() {
8 ; CHECK: rorv_i64:
8 ; CHECK-LABEL: rorv_i64:
99 %val0_tmp = load i64* @var64_0
1010 %val1_tmp = load i64* @var64_1
1111 %val2_tmp = sub i64 64, %val1_tmp
1818 }
1919
2020 define void @asrv_i64() {
21 ; CHECK: asrv_i64:
21 ; CHECK-LABEL: asrv_i64:
2222 %val0_tmp = load i64* @var64_0
2323 %val1_tmp = load i64* @var64_1
2424 %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
2828 }
2929
3030 define void @lsrv_i64() {
31 ; CHECK: lsrv_i64:
31 ; CHECK-LABEL: lsrv_i64:
3232 %val0_tmp = load i64* @var64_0
3333 %val1_tmp = load i64* @var64_1
3434 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
3838 }
3939
4040 define void @lslv_i64() {
41 ; CHECK: lslv_i64:
41 ; CHECK-LABEL: lslv_i64:
4242 %val0_tmp = load i64* @var64_0
4343 %val1_tmp = load i64* @var64_1
4444 %val4_tmp = shl i64 %val0_tmp, %val1_tmp
4848 }
4949
5050 define void @udiv_i64() {
51 ; CHECK: udiv_i64:
51 ; CHECK-LABEL: udiv_i64:
5252 %val0_tmp = load i64* @var64_0
5353 %val1_tmp = load i64* @var64_1
5454 %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
5858 }
5959
6060 define void @sdiv_i64() {
61 ; CHECK: sdiv_i64:
61 ; CHECK-LABEL: sdiv_i64:
6262 %val0_tmp = load i64* @var64_0
6363 %val1_tmp = load i64* @var64_1
6464 %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
6969
7070
7171 define void @lsrv_i32() {
72 ; CHECK: lsrv_i32:
72 ; CHECK-LABEL: lsrv_i32:
7373 %val0_tmp = load i32* @var32_0
7474 %val1_tmp = load i32* @var32_1
7575 %val2_tmp = add i32 1, %val1_tmp
8080 }
8181
8282 define void @lslv_i32() {
83 ; CHECK: lslv_i32:
83 ; CHECK-LABEL: lslv_i32:
8484 %val0_tmp = load i32* @var32_0
8585 %val1_tmp = load i32* @var32_1
8686 %val2_tmp = add i32 1, %val1_tmp
9191 }
9292
9393 define void @rorv_i32() {
94 ; CHECK: rorv_i32:
94 ; CHECK-LABEL: rorv_i32:
9595 %val0_tmp = load i32* @var32_0
9696 %val6_tmp = load i32* @var32_1
9797 %val1_tmp = add i32 1, %val6_tmp
105105 }
106106
107107 define void @asrv_i32() {
108 ; CHECK: asrv_i32:
108 ; CHECK-LABEL: asrv_i32:
109109 %val0_tmp = load i32* @var32_0
110110 %val1_tmp = load i32* @var32_1
111111 %val2_tmp = add i32 1, %val1_tmp
116116 }
117117
118118 define void @sdiv_i32() {
119 ; CHECK: sdiv_i32:
119 ; CHECK-LABEL: sdiv_i32:
120120 %val0_tmp = load i32* @var32_0
121121 %val1_tmp = load i32* @var32_1
122122 %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
126126 }
127127
128128 define void @udiv_i32() {
129 ; CHECK: udiv_i32:
129 ; CHECK-LABEL: udiv_i32:
130130 %val0_tmp = load i32* @var32_0
131131 %val1_tmp = load i32* @var32_1
132132 %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
0 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
11
22 define i64 @ror_i64(i64 %in) {
3 ; CHECK: ror_i64:
3 ; CHECK-LABEL: ror_i64:
44 %left = shl i64 %in, 19
55 %right = lshr i64 %in, 45
66 %val5 = or i64 %left, %right
99 }
1010
1111 define i32 @ror_i32(i32 %in) {
12 ; CHECK: ror_i32:
12 ; CHECK-LABEL: ror_i32:
1313 %left = shl i32 %in, 9
1414 %right = lshr i32 %in, 23
1515 %val5 = or i32 %left, %right
1818 }
1919
2020 define i32 @extr_i32(i32 %lhs, i32 %rhs) {
21 ; CHECK: extr_i32:
21 ; CHECK-LABEL: extr_i32:
2222 %left = shl i32 %lhs, 6
2323 %right = lshr i32 %rhs, 26
2424 %val = or i32 %left, %right
3030 }
3131
3232 define i64 @extr_i64(i64 %lhs, i64 %rhs) {
33 ; CHECK: extr_i64:
33 ; CHECK-LABEL: extr_i64:
3434 %right = lshr i64 %rhs, 40
3535 %left = shl i64 %lhs, 24
3636 %val = or i64 %right, %left
4444 ; Regression test: a bad experimental pattern crept into git which optimised
4545 ; this pattern to a single EXTR.
4646 define i32 @extr_regress(i32 %a, i32 %b) {
47 ; CHECK: extr_regress:
47 ; CHECK-LABEL: extr_regress:
4848
4949 %sh1 = shl i32 %a, 14
5050 %sh2 = lshr i32 %b, 14
66 declare fastcc void @will_pop([8 x i32], i32 %val)
77
88 define fastcc void @foo(i32 %in) {
9 ; CHECK: foo:
9 ; CHECK-LABEL: foo:
1010
1111 %addr = alloca i8, i32 %in
1212
3333 declare void @wont_pop([8 x i32], i32 %val)
3434
3535 define void @foo1(i32 %in) {
36 ; CHECK: foo1:
36 ; CHECK-LABEL: foo1:
3737
3838 %addr = alloca i8, i32 %in
3939 ; Normal frame setup again
44 ; stack, so try to make sure this is respected.
55
66 define fastcc void @func_stack0() {
7 ; CHECK: func_stack0:
7 ; CHECK-LABEL: func_stack0:
88 ; CHECK: sub sp, sp, #48
99
10 ; CHECK-TAIL: func_stack0:
10 ; CHECK-TAIL-LABEL: func_stack0:
1111 ; CHECK-TAIL: sub sp, sp, #48
1212
1313
4444 }
4545
4646 define fastcc void @func_stack8([8 x i32], i32 %stacked) {
47 ; CHECK: func_stack8:
47 ; CHECK-LABEL: func_stack8:
4848 ; CHECK: sub sp, sp, #48
4949
50 ; CHECK-TAIL: func_stack8:
50 ; CHECK-TAIL-LABEL: func_stack8:
5151 ; CHECK-TAIL: sub sp, sp, #48
5252
5353
8383 }
8484
8585 define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
86 ; CHECK: func_stack32:
86 ; CHECK-LABEL: func_stack32:
8787 ; CHECK: sub sp, sp, #48
8888
89 ; CHECK-TAIL: func_stack32:
89 ; CHECK-TAIL-LABEL: func_stack32:
9090 ; CHECK-TAIL: sub sp, sp, #48
9191
9292
2525 declare double @nearbyint(double) readonly
2626
2727 define void @simple_float() {
28 ; CHECK: simple_float:
28 ; CHECK-LABEL: simple_float:
2929 %val1 = load volatile float* @varfloat
3030
3131 %valabs = call float @fabsf(float %val1)
6464 }
6565
6666 define void @simple_double() {
67 ; CHECK: simple_double:
67 ; CHECK-LABEL: simple_double:
6868 %val1 = load volatile double* @vardouble
6969
7070 %valabs = call double @fabs(double %val1)
103103 }
104104
105105 define void @converts() {
106 ; CHECK: converts:
106 ; CHECK-LABEL: converts:
107107
108108 %val16 = load volatile half* @varhalf
109109 %val32 = load volatile float* @varfloat
4545
4646 define double @testd_fmadd(double %a, double %b, double %c) {
4747 ; CHECK-LABEL: testd_fmadd:
48 ; CHECK-NOFAST: testd_fmadd:
48 ; CHECK-NOFAST-LABEL: testd_fmadd:
4949 %val = call double @llvm.fma.f64(double %a, double %b, double %c)
5050 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
5151 ; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
5454
5555 define double @testd_fmsub(double %a, double %b, double %c) {
5656 ; CHECK-LABEL: testd_fmsub:
57 ; CHECK-NOFAST: testd_fmsub:
57 ; CHECK-NOFAST-LABEL: testd_fmsub:
5858 %nega = fsub double -0.0, %a
5959 %val = call double @llvm.fma.f64(double %nega, double %b, double %c)
6060 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
6464
6565 define double @testd_fnmadd(double %a, double %b, double %c) {
6666 ; CHECK-LABEL: testd_fnmadd:
67 ; CHECK-NOFAST: testd_fnmadd:
67 ; CHECK-NOFAST-LABEL: testd_fnmadd:
6868 %negc = fsub double -0.0, %c
6969 %val = call double @llvm.fma.f64(double %a, double %b, double %negc)
7070 ; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
7474
7575 define double @testd_fnmsub(double %a, double %b, double %c) {
7676 ; CHECK-LABEL: testd_fnmsub:
77 ; CHECK-NOFAST: testd_fnmsub:
77 ; CHECK-NOFAST-LABEL: testd_fnmsub:
7878 %nega = fsub double -0.0, %a
7979 %negc = fsub double -0.0, %c
8080 %val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
33 @varf64 = global double 0.0
44
55 define void @check_float() {
6 ; CHECK: check_float:
6 ; CHECK-LABEL: check_float:
77
88 %val = load float* @varf32
99 %newval1 = fadd float %val, 8.5
1818 }
1919
2020 define void @check_double() {
21 ; CHECK: check_double:
21 ; CHECK-LABEL: check_double:
2222
2323 %val = load double* @varf64
2424 %newval1 = fadd double %val, 8.5
1010 @varstruct = global %myStruct zeroinitializer
1111
1212 define void @take_i8s(i8 %val1, i8 %val2) {
13 ; CHECK: take_i8s:
13 ; CHECK-LABEL: take_i8s:
1414 store i8 %val2, i8* @var8
1515 ; Not using w1 may be technically allowed, but it would indicate a
1616 ; problem in itself.
1919 }
2020
2121 define void @add_floats(float %val1, float %val2) {
22 ; CHECK: add_floats:
22 ; CHECK-LABEL: add_floats:
2323 %newval = fadd float %val1, %val2
2424 ; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
2525 store float %newval, float* @varfloat
3030 ; byval pointers should be allocated to the stack and copied as if
3131 ; with memcpy.
3232 define void @take_struct(%myStruct* byval %structval) {
33 ; CHECK: take_struct:
33 ; CHECK-LABEL: take_struct:
3434 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
3535 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
3636
5050
5151 ; %structval should be at sp + 16
5252 define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
53 ; CHECK: check_byval_align:
53 ; CHECK-LABEL: check_byval_align:
5454
5555 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
5656 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
7171 }
7272
7373 define i32 @return_int() {
74 ; CHECK: return_int:
74 ; CHECK-LABEL: return_int:
7575 %val = load i32* @var32
7676 ret i32 %val
7777 ; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
8080 }
8181
8282 define double @return_double() {
83 ; CHECK: return_double:
83 ; CHECK-LABEL: return_double:
8484 ret double 3.14
8585 ; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
8686 }
8989 ; small enough to go into registers. Not all that pretty, but it
9090 ; works.
9191 define [2 x i64] @return_struct() {
92 ; CHECK: return_struct:
92 ; CHECK-LABEL: return_struct:
9393 %addr = bitcast %myStruct* @varstruct to [2 x i64]*
9494 %val = load [2 x i64]* %addr
9595 ret [2 x i64] %val
106106 ; structs larger than 16 bytes, but C semantics can still be provided
107107 ; if LLVM does it to %myStruct too. So this is the simplest check
108108 define void @return_large_struct(%myStruct* sret %retval) {
109 ; CHECK: return_large_struct:
109 ; CHECK-LABEL: return_large_struct:
110110 %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
111111 %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
112112 %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
127127 define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
128128 i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
129129 double %notstacked) {
130 ; CHECK: struct_on_stack:
130 ; CHECK-LABEL: struct_on_stack:
131131 %addr = getelementptr %myStruct* %struct, i64 0, i32 0
132132 %val64 = load i64* %addr
133133 store i64 %val64, i64* @var64
147147 define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
148148 float %var4, float %var5, float %var6, float %var7,
149149 float %var8) {
150 ; CHECK: stacked_fpu:
150 ; CHECK-LABEL: stacked_fpu:
151151 store float %var8, float* @varfloat
152152 ; Beware as above: the offset would be different on big-endian
153153 ; machines if the first ldr were changed to use s-registers.
1616 declare void @take_floats(float %val1, float %val2)
1717
1818 define void @simple_args() {
19 ; CHECK: simple_args:
19 ; CHECK-LABEL: simple_args:
2020 %char1 = load i8* @var8
2121 %char2 = load i8* @var8_2
2222 call void @take_i8s(i8 %char1, i8 %char2)
4040 declare void @return_large_struct(%myStruct* sret %retval)
4141
4242 define void @simple_rets() {
43 ; CHECK: simple_rets:
43 ; CHECK-LABEL: simple_rets:
4444
4545 %int = call i32 @return_int()
4646 store i32 %int, i32* @var32
105105
106106
107107 define void @check_i128_align() {
108 ; CHECK: check_i128_align:
108 ; CHECK-LABEL: check_i128_align:
109109 %val = load i128* @var128
110110 call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
111111 i32 4, i32 5, i32 6, i32 7,
129129 @fptr = global void()* null
130130
131131 define void @check_indirect_call() {
132 ; CHECK: check_indirect_call:
132 ; CHECK-LABEL: check_indirect_call:
133133 %func = load void()** @fptr
134134 call void %func()
135135 ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]
1212 declare void @func()
1313
1414 define void @foo() nounwind {
15 ; CHECK: foo:
15 ; CHECK-LABEL: foo:
1616 entry:
1717 call void @consume(i32 ptrtoint (void ()* @func to i32))
1818 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func
44 @var = global %struct zeroinitializer
55
66 define i64 @check_size() {
7 ; CHECK: check_size:
7 ; CHECK-LABEL: check_size:
88 %starti = ptrtoint %struct* @var to i64
99
1010 %endp = getelementptr %struct* @var, i64 1
1616 }
1717
1818 define i64 @check_field() {
19 ; CHECK: check_field:
19 ; CHECK-LABEL: check_field:
2020 %starti = ptrtoint %struct* @var to i64
2121
2222 %endp = getelementptr %struct* @var, i64 0, i32 1
88 @var_double = global double 0.0
99
1010 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
11 ; CHECK: ldst_8bit:
11 ; CHECK-LABEL: ldst_8bit:
1212
1313 %addr8_sxtw = getelementptr i8* %base, i32 %off32
1414 %val8_sxtw = load volatile i8* %addr8_sxtw
3636
3737
3838 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
39 ; CHECK: ldst_16bit:
39 ; CHECK-LABEL: ldst_16bit:
4040
4141 %addr8_sxtwN = getelementptr i16* %base, i32 %off32
4242 %val8_sxtwN = load volatile i16* %addr8_sxtwN
9090 }
9191
9292 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
93 ; CHECK: ldst_32bit:
93 ; CHECK-LABEL: ldst_32bit:
9494
9595 %addr_sxtwN = getelementptr i32* %base, i32 %off32
9696 %val_sxtwN = load volatile i32* %addr_sxtwN
142142 }
143143
144144 define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
145 ; CHECK: ldst_64bit:
145 ; CHECK-LABEL: ldst_64bit:
146146
147147 %addr_sxtwN = getelementptr i64* %base, i32 %off32
148148 %val_sxtwN = load volatile i64* %addr_sxtwN
190190 }
191191
192192 define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
193 ; CHECK: ldst_float:
193 ; CHECK-LABEL: ldst_float:
194194
195195 %addr_sxtwN = getelementptr float* %base, i32 %off32
196196 %val_sxtwN = load volatile float* %addr_sxtwN
237237 }
238238
239239 define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
240 ; CHECK: ldst_double:
240 ; CHECK-LABEL: ldst_double:
241241
242242 %addr_sxtwN = getelementptr double* %base, i32 %off32
243243 %val_sxtwN = load volatile double* %addr_sxtwN
285285
286286
287287 define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
288 ; CHECK: ldst_128bit:
288 ; CHECK-LABEL: ldst_128bit:
289289
290290 %addr_sxtwN = getelementptr fp128* %base, i32 %off32
291291 %val_sxtwN = load volatile fp128* %addr_sxtwN
1010 @varptr = global i8* null
1111
1212 define void @ldst_8bit() {
13 ; CHECK: ldst_8bit:
13 ; CHECK-LABEL: ldst_8bit:
1414
1515 ; No architectural support for loads to 16-bit or 8-bit since we
1616 ; promote i8 during lowering.
7171 }
7272
7373 define void @ldst_16bit() {
74 ; CHECK: ldst_16bit:
74 ; CHECK-LABEL: ldst_16bit:
7575
7676 ; No architectural support for loads to 16-bit or 16-bit since we
7777 ; promote i16 during lowering.
139139 }
140140
141141 define void @ldst_32bit() {
142 ; CHECK: ldst_32bit:
142 ; CHECK-LABEL: ldst_32bit:
143143
144144 %addr_8bit = load i8** @varptr
145145
185185 }
186186
187187 define void @ldst_float() {
188 ; CHECK: ldst_float:
188 ; CHECK-LABEL: ldst_float:
189189
190190 %addr_8bit = load i8** @varptr
191191 %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
201201 }
202202
203203 define void @ldst_double() {
204 ; CHECK: ldst_double:
204 ; CHECK-LABEL: ldst_double:
205205
206206 %addr_8bit = load i8** @varptr
207207 %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
88 @var_double = global double 0.0
99
1010 define void @ldst_8bit() {
11 ; CHECK: ldst_8bit:
11 ; CHECK-LABEL: ldst_8bit:
1212
1313 ; No architectural support for loads to 16-bit or 8-bit since we
1414 ; promote i8 during lowering.
6262 }
6363
6464 define void @ldst_16bit() {
65 ; CHECK: ldst_16bit:
65 ; CHECK-LABEL: ldst_16bit:
6666
6767 ; No architectural support for load volatiles to 16-bit promote i16 during
6868 ; lowering.
116116 }
117117
118118 define void @ldst_32bit() {
119 ; CHECK: ldst_32bit:
119 ; CHECK-LABEL: ldst_32bit:
120120
121121 ; Straight 32-bit load/store
122122 %val32_noext = load volatile i32* @var_32bit
224224 }
225225
226226 define void @ldst_float() {
227 ; CHECK: ldst_float:
227 ; CHECK-LABEL: ldst_float:
228228
229229 %valfp = load volatile float* @var_float
230230 ; CHECK: adrp {{x[0-9]+}}, var_float
237237 }
238238
239239 define void @ldst_double() {
240 ; CHECK: ldst_double:
240 ; CHECK-LABEL: ldst_double:
241241
242242 %valfp = load volatile double* @var_double
243243 ; CHECK: adrp {{x[0-9]+}}, var_double
44 @var64 = global i64 0
55
66 define void @foo() {
7 ; CHECK: foo:
7 ; CHECK-LABEL: foo:
88 %val32 = load i32* @var32
99 %val64 = load i64* @var64
1010
5959 @vardouble = global double 0.0
6060
6161 define void @floating_lits() {
62 ; CHECK: floating_lits:
62 ; CHECK-LABEL: floating_lits:
6363
6464 %floatval = load float* @varfloat
6565 %newfloat = fadd float %floatval, 128.0
2323 }
2424
2525 define void @trivial_fp_func() {
26 ; CHECK-WITHFP: trivial_fp_func:
26 ; CHECK-WITHFP-LABEL: trivial_fp_func:
2727
2828 ; CHECK-WITHFP: sub sp, sp, #16
2929 ; CHECK-WITHFP: stp x29, x30, [sp]
4242
4343 define void @stack_local() {
4444 %local_var = alloca i64
45 ; CHECK: stack_local:
45 ; CHECK-LABEL: stack_local:
4646 ; CHECK: sub sp, sp, #16
4747
4848 %val = load i64* @var
66 @var2_64 = global i64 0
77
88 define void @logical_32bit() {
9 ; CHECK: logical_32bit:
9 ; CHECK-LABEL: logical_32bit:
1010 %val1 = load i32* @var1_32
1111 %val2 = load i32* @var2_32
1212
9696 }
9797
9898 define void @logical_64bit() {
99 ; CHECK: logical_64bit:
99 ; CHECK-LABEL: logical_64bit:
100100 %val1 = load i64* @var1_64
101101 %val2 = load i64* @var2_64
102102
189189 }
190190
191191 define void @flag_setting() {
192 ; CHECK: flag_setting:
192 ; CHECK-LABEL: flag_setting:
193193 %val1 = load i64* @var1_64
194194 %val2 = load i64* @var2_64
195195
33 declare void @bar()
44
55 define void @foo() {
6 ; CHECK: foo:
6 ; CHECK-LABEL: foo:
77 %func = load void()** @var
88
99 ; Calling a function encourages @foo to use a callee-saved register,
44 declare void @callee_stack16([8 x i32], i64, i64)
55
66 define void @caller_to0_from0() nounwind {
7 ; CHECK: caller_to0_from0:
7 ; CHECK-LABEL: caller_to0_from0:
88 ; CHECK-NEXT: // BB
99 tail call void @callee_stack0()
1010 ret void
1212 }
1313
1414 define void @caller_to0_from8([8 x i32], i64) nounwind{
15 ; CHECK: caller_to0_from8:
15 ; CHECK-LABEL: caller_to0_from8:
1616 ; CHECK-NEXT: // BB
1717
1818 tail call void @callee_stack0()
2121 }
2222
2323 define void @caller_to8_from0() {
24 ; CHECK: caller_to8_from0:
24 ; CHECK-LABEL: caller_to8_from0:
2525
2626 ; Caller isn't going to clean up any extra stack we allocate, so it
2727 ; can't be a tail call.
3131 }
3232
3333 define void @caller_to8_from8([8 x i32], i64 %a) {
34 ; CHECK: caller_to8_from8:
34 ; CHECK-LABEL: caller_to8_from8:
3535 ; CHECK-NOT: sub sp, sp,
3636
3737 ; This should reuse our stack area for the 42
4242 }
4343
4444 define void @caller_to16_from8([8 x i32], i64 %a) {
45 ; CHECK: caller_to16_from8:
45 ; CHECK-LABEL: caller_to16_from8:
4646
4747 ; Shouldn't be a tail call: we can't use SP+8 because our caller might
4848 ; have something there. This may sound obvious but implementation does
5353 }
5454
5555 define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
56 ; CHECK: caller_to8_from24:
56 ; CHECK-LABEL: caller_to8_from24:
5757 ; CHECK-NOT: sub sp, sp
5858
5959 ; Reuse our area, putting "42" at incoming sp
6464 }
6565
6666 define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
67 ; CHECK: caller_to16_from16:
67 ; CHECK-LABEL: caller_to16_from16:
6868 ; CHECK-NOT: sub sp, sp,
6969
7070 ; Here we want to make sure that both loads happen before the stores:
8484 @func = global void(i32)* null
8585
8686 define void @indirect_tail() {
87 ; CHECK: indirect_tail:
87 ; CHECK-LABEL: indirect_tail:
8888 ; CHECK-NOT: sub sp, sp
8989
9090 %fptr = load void(i32)** @func
44 declare fastcc void @callee_stack16([8 x i32], i64, i64)
55
66 define fastcc void @caller_to0_from0() nounwind {
7 ; CHECK: caller_to0_from0:
7 ; CHECK-LABEL: caller_to0_from0:
88 ; CHECK-NEXT: // BB
99 tail call fastcc void @callee_stack0()
1010 ret void
1212 }
1313
1414 define fastcc void @caller_to0_from8([8 x i32], i64) {
15 ; CHECK: caller_to0_from8:
15 ; CHECK-LABEL: caller_to0_from8:
1616
1717 tail call fastcc void @callee_stack0()
1818 ret void
2121 }
2222
2323 define fastcc void @caller_to8_from0() {
24 ; CHECK: caller_to8_from0:
24 ; CHECK-LABEL: caller_to8_from0:
2525 ; CHECK: sub sp, sp, #32
2626
2727 ; Key point is that the "42" should go #16 below incoming stack
3434 }
3535
3636 define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
37 ; CHECK: caller_to8_from8:
37 ; CHECK-LABEL: caller_to8_from8:
3838 ; CHECK: sub sp, sp, #16
3939
4040 ; Key point is that the "%a" should go where at SP on entry.
4646 }
4747
4848 define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
49 ; CHECK: caller_to16_from8:
49 ; CHECK-LABEL: caller_to16_from8:
5050 ; CHECK: sub sp, sp, #16
5151
5252 ; Important point is that the call reuses the "dead" argument space
6262
6363
6464 define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
65 ; CHECK: caller_to8_from24:
65 ; CHECK-LABEL: caller_to8_from24:
6666 ; CHECK: sub sp, sp, #16
6767
6868 ; Key point is that the "%a" should go where at #16 above SP on entry.
7575
7676
7777 define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
78 ; CHECK: caller_to16_from16:
78 ; CHECK-LABEL: caller_to16_from16:
7979 ; CHECK: sub sp, sp, #16
8080
8181 ; Here we want to make sure that both loads happen before the stores:
33 @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
44 @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
55
6 ; CHECK: dct_luma_sp:
6 ; CHECK-LABEL: dct_luma_sp:
77 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
88 entry:
99 ; Make sure to use base-updating stores for saving callee-saved registers.
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
11 ; pr4843
22 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
3 ;CHECK: v2regbug:
3 ;CHECK-LABEL: v2regbug:
44 ;CHECK: vzip.16
55 %tmp1 = load <4 x i16>* %B
66 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32>
33 %0 = type { double, double }
44
55 define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
6 ; CHECK: foo:
6 ; CHECK-LABEL: foo:
77 ; CHECK: bl __aeabi_dadd
88 ; CHECK-NOT: strd
99 ; CHECK: mov
1111 %3 = fmul float %0, %1 ; [#uses=1]
1212 %4 = fadd float 0.000000e+00, %3 ; [#uses=1]
1313 %5 = fsub float 1.000000e+00, %4 ; [#uses=1]
14 ; CHECK: foo:
14 ; CHECK-LABEL: foo:
1515 ; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
1616 %6 = fsub float 1.000000e+00, undef ; [#uses=2]
1717 %7 = fsub float %2, undef ; [#uses=1]
55
66 define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
77 entry:
8 ; ARM: t:
8 ; ARM-LABEL: t:
99 ; ARM: str r2, [r1], r0
1010
11 ; THUMB: t:
11 ; THUMB-LABEL: t:
1212 ; THUMB-NOT: str r0, [r1], r0
1313 ; THUMB: str r1, [r0]
1414 %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; [#uses=1]
33
44 define i32* @t(i32* %x) nounwind {
55 entry:
6 ; ARM: t:
6 ; ARM-LABEL: t:
77 ; ARM: push
88 ; ARM: mov r7, sp
99 ; ARM: bl _foo
1111 ; ARM: bl _foo
1212 ; ARM: pop {r7, pc}
1313
14 ; THUMB2: t:
14 ; THUMB2-LABEL: t:
1515 ; THUMB2: push
1616 ; THUMB2: mov r7, sp
1717 ; THUMB2: blx _foo
22
33 define hidden void @foo() nounwind ssp {
44 entry:
5 ; CHECK: foo:
5 ; CHECK-LABEL: foo:
66 ; CHECK: mov r7, sp
77 ; CHECK-NEXT: vpush {d8}
88 ; CHECK-NEXT: vpush {d10, d11}
88 @oStruct = external global %struct.Outer, align 4
99
1010 define void @main() nounwind {
11 ; CHECK: main:
11 ; CHECK-LABEL: main:
1212 ; CHECK-NOT: ldrd
1313 ; CHECK: mul
1414 for.body.lr.ph:
77 ; rdar://9172742
88
99 define i32 @t() nounwind {
10 ; CHECK: t:
10 ; CHECK-LABEL: t:
1111 entry:
1212 br label %bb2
1313
1111
1212 ; Make sure the scheduler schedules all uses of the preincrement
1313 ; induction variable before defining the postincrement value.
14 ; CHECK: t:
14 ; CHECK-LABEL: t:
1515 ; CHECK: %bb
1616 ; CHECK-NOT: mov
1717 bb: ; preds = %entry, %bb
33 ; rdar://9266679
44
55 define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
6 ; CHECK: t:
6 ; CHECK-LABEL: t:
77 entry:
88 br label %for.cond
99
99 @infoBlock = external global %struct.InformationBlock
1010
1111 define hidden void @foo() {
12 ; CHECK: foo:
12 ; CHECK-LABEL: foo:
1313 ; CHECK: ldr.w
1414 ; CHECK: ldr.w
1515 ; CHECK-NOT: ldm
2222 ;
2323 ; rdar://11116189
2424 define i64 @t(i64 %aInput) nounwind {
25 ; CHECK: t:
25 ; CHECK-LABEL: t:
2626 ; CHECK: movs [[REG:(r[0-9]+)]], #0
2727 ; CHECK: movt [[REG]], #46540
2828 ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
1212 ; v4i8
1313 ;
1414 define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
15 ;CHECK: sextload_v4i8_c:
15 ;CHECK-LABEL: sextload_v4i8_c:
1616 entry:
1717 %0 = load <4 x i8>* %v, align 8
1818 %v0 = sext <4 x i8> %0 to <4 x i32>
2525 ; v2i8
2626 ;
2727 define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
28 ;CHECK: sextload_v2i8_c:
28 ;CHECK-LABEL: sextload_v2i8_c:
2929 entry:
3030 %0 = load <2 x i8>* %v, align 8
3131 %v0 = sext <2 x i8> %0 to <2 x i64>
3838 ; v2i16
3939 ;
4040 define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
41 ;CHECK: sextload_v2i16_c:
41 ;CHECK-LABEL: sextload_v2i16_c:
4242 entry:
4343 %0 = load <2 x i16>* %v, align 8
4444 %v0 = sext <2 x i16> %0 to <2 x i64>
5353 ; v4i8
5454 ;
5555 define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
56 ;CHECK: sextload_v4i8_v:
56 ;CHECK-LABEL: sextload_v4i8_v:
5757 entry:
5858 %0 = load <4 x i8>* %v, align 8
5959 %v0 = sext <4 x i8> %0 to <4 x i32>
6969 ; v2i8
7070 ;
7171 define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
72 ;CHECK: sextload_v2i8_v:
72 ;CHECK-LABEL: sextload_v2i8_v:
7373 entry:
7474 %0 = load <2 x i8>* %v, align 8
7575 %v0 = sext <2 x i8> %0 to <2 x i64>
8585 ; v2i16
8686 ;
8787 define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
88 ;CHECK: sextload_v2i16_v:
88 ;CHECK-LABEL: sextload_v2i16_v:
8989 entry:
9090 %0 = load <2 x i16>* %v, align 8
9191 %v0 = sext <2 x i16> %0 to <2 x i64>
103103 ; v4i8 x v4i16
104104 ;
105105 define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
106 ;CHECK: sextload_v4i8_vs:
106 ;CHECK-LABEL: sextload_v4i8_vs:
107107 entry:
108108 %0 = load <4 x i8>* %v, align 8
109109 %v0 = sext <4 x i8> %0 to <4 x i32>
119119 ; v2i8
120120 ; v2i8 x v2i16
121121 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
122 ;CHECK: sextload_v2i8_vs:
122 ;CHECK-LABEL: sextload_v2i8_vs:
123123 entry:
124124 %0 = load <2 x i8>* %v, align 8
125125 %v0 = sext <2 x i8> %0 to <2 x i64>
135135 ; v2i16
136136 ; v2i16 x v2i32
137137 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
138 ;CHECK: sextload_v2i16_vs:
138 ;CHECK-LABEL: sextload_v2i16_vs:
139139 entry:
140140 %0 = load <2 x i16>* %v, align 8
141141 %v0 = sext <2 x i16> %0 to <2 x i64>
33 ; rdar://12300648
44
55 define i32 @t(i32 %x) {
6 ; CHECK: t:
6 ; CHECK-LABEL: t:
77 ; CHECK-NOT: movw
88 %tmp = add i32 %x, -65535
99 ret i32 %tmp
2222 ret void
2323 }
2424
25 ; CHECK: main:
25 ; CHECK-LABEL: main:
2626 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
2727 ; CHECK: movt [[BASE]], :upper16:static_val
2828 ; ldm is not formed when the coalescer failed to coalesce everything.
5252 ret void
5353 }
5454
55 ; CHECK: main_fixed_arg:
55 ; CHECK-LABEL: main_fixed_arg:
5656 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
5757 ; CHECK: movt [[BASE]], :upper16:static_val
5858 ; ldm is not formed when the coalescer failed to coalesce everything.
55
66 declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
77
8 ; CHECK: main:
8 ; CHECK-LABEL: main:
99 define i32 @main() nounwind {
1010 entry:
1111 ; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
44
55 declare void @f(%struct.s* %p);
66
7 ; CHECK: t:
7 ; CHECK-LABEL: t:
88 define void @t(i32 %a, %struct.s* byval %s) nounwind {
99 entry:
1010
1919 ret void
2020 }
2121
22 ; CHECK: caller:
22 ; CHECK-LABEL: caller:
2323 define void @caller() {
2424
2525 ; CHECK: ldm r0, {r1, r2, r3}
11 ;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
22 ;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
33
4 ;EXPECTED: foo:
5 ;CHECK: foo:
4 ;EXPECTED-LABEL: foo:
5 ;CHECK-LABEL: foo:
66 define i32 @foo(i32* %a) nounwind optsize {
77 entry:
88 %0 = load i32* %a, align 4
11 ; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
22
33 define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
4 ; CHECK: muladd:
4 ; CHECK-LABEL: muladd:
55 ; CHECK: fmaf
66 ; CHECK: fmaf
77 ; CHECK: fmaf
1616 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
1717
1818 define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
19 ; CHECK: muladd2:
19 ; CHECK-LABEL: muladd2:
2020 ; CHECK: fmaf
2121 ; CHECK: fmaf
2222 ; CHECK-NOT: fmaf
0 ;PR15293: ARM codegen ice - expected larger existing stack allocation
11 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
22
3 ;CHECK: foo:
3 ;CHECK-LABEL: foo:
44 ;CHECK: sub sp, sp, #8
55 ;CHECK: push {r11, lr}
66 ;CHECK: str r0, [sp, #8]
1010 ;CHECK: add sp, sp, #8
1111 ;CHECK: mov pc, lr
1212
13 ;CHECK: foo2:
13 ;CHECK-LABEL: foo2:
1414 ;CHECK: sub sp, sp, #8
1515 ;CHECK: push {r11, lr}
1616 ;CHECK: str r0, [sp, #8]
2323 ;CHECK: add sp, sp, #8
2424 ;CHECK: mov pc, lr
2525
26 ;CHECK: doFoo:
26 ;CHECK-LABEL: doFoo:
2727 ;CHECK: push {r11, lr}
2828 ;CHECK: ldr r0,
2929 ;CHECK: ldr r0, [r0]
3232 ;CHECK: mov pc, lr
3333
3434
35 ;CHECK: doFoo2:
35 ;CHECK-LABEL: doFoo2:
3636 ;CHECK: push {r11, lr}
3737 ;CHECK: ldr r0,
3838 ;CHECK: mov r1, #0
5252
5353 ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
5454 ;
55 ;CHECK: foo:
55 ;CHECK-LABEL: foo:
5656 ;CHECK-NOT: mov r0
5757 ;CHECK-NOT: ldr r0
5858 ;CHECK: bl fooUseI32
59 ;CHECK: doFoo:
59 ;CHECK-LABEL: doFoo:
6060 ;CHECK: movs r0, #43
6161 ;CHECK: bl foo
6262
88
99 @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
1010
11 ;CHECK: printfn:
11 ;CHECK-LABEL: printfn:
1212 define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
1313 entry:
1414 %conv = sext i16 %b to i32
11 ; rdar://13782395
22
33 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
4 ; CHECK: t1:
4 ; CHECK-LABEL: t1:
55 ; CHECK: Block address taken
66 ; CHECK-NOT: Address of block that was removed by CodeGen
77 store i8* blockaddress(@t1, %cond_true), i8** %retaddr
1818 }
1919
2020 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
21 ; CHECK: t2:
21 ; CHECK-LABEL: t2:
2222 ; CHECK: Block address taken
2323 ; CHECK: %cond_true
2424 ; CHECK: add
4040 }
4141
4242 define hidden fastcc void @t3(i8** %retaddr) {
43 ; CHECK: t3:
43 ; CHECK-LABEL: t3:
4444 ; CHECK: Block address taken
4545 ; CHECK-NOT: Address of block that was removed by CodeGen
4646 bb:
0 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s
11 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
22
3 ; CHECK-ENABLED: t1:
4 ; CHECK-DISABLED: t1:
3 ; CHECK-ENABLED-LABEL: t1:
4 ; CHECK-DISABLED-LABEL: t1:
55 define <2 x float> @t1(float %f) {
66 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
77 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
1010 ret <2 x float> %i2
1111 }
1212
13 ; CHECK-ENABLED: t2:
14 ; CHECK-DISABLED: t2:
13 ; CHECK-ENABLED-LABEL: t2:
14 ; CHECK-DISABLED-LABEL: t2:
1515 define <4 x float> @t2(float %g, float %f) {
1616 ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
1717 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
2020 ret <4 x float> %i2
2121 }
2222
23 ; CHECK-ENABLED: t3:
24 ; CHECK-DISABLED: t3:
23 ; CHECK-ENABLED-LABEL: t3:
24 ; CHECK-DISABLED-LABEL: t3:
2525 define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
2626 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
2727 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
3030 ret <2 x float> %i2
3131 }
3232
33 ; CHECK-ENABLED: t4:
34 ; CHECK-DISABLED: t4:
33 ; CHECK-ENABLED-LABEL: t4:
34 ; CHECK-DISABLED-LABEL: t4:
3535 define <2 x float> @t4(float %f) {
3636 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
3737 ; CHECK-DISABLED-NOT: vdup
4444 ret <2 x float> %i2
4545 }
4646
47 ; CHECK-ENABLED: t5:
48 ; CHECK-DISABLED: t5:
47 ; CHECK-ENABLED-LABEL: t5:
48 ; CHECK-DISABLED-LABEL: t5:
4949 define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
5050 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
5151 ; CHECK-ENABLED: vadd.f32
0 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
11
2 ; CHECK: t1:
2 ; CHECK-LABEL: t1:
33 define <2 x float> @t1(float* %A, <2 x float> %B) {
44 ; The generated code for this test uses a vld1.32 instruction
55 ; to write the lane 1 of a D register containing the value of
1414 ret <2 x float> %tmp3
1515 }
1616
17 ; CHECK: t2:
17 ; CHECK-LABEL: t2:
1818 define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
1919 entry:
2020 br label %loop
11 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
22
33 define i32 @f1(i32 %a, i64 %b) {
4 ; ELF: f1:
4 ; ELF-LABEL: f1:
55 ; ELF: mov r0, r2
6 ; DARWIN: f1:
6 ; DARWIN-LABEL: f1:
77 ; DARWIN: mov r0, r1
88 %tmp = call i32 @g1(i64 %b)
99 ret i32 %tmp
1111
1212 ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
1313 define i32 @f2() nounwind optsize {
14 ; ELF: f2:
14 ; ELF-LABEL: f2:
1515 ; ELF: mov [[REGISTER:(r[0-9]+)]], #128
1616 ; ELF: str [[REGISTER]], [
17 ; DARWIN: f2:
17 ; DARWIN-LABEL: f2:
1818 ; DARWIN: mov r3, #128
1919 entry:
2020 %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; [#uses=1]
2525
2626 ; test that on gnueabi a 64 bit value at this position will cause r3 to go
2727 ; unused and the value stored in [sp]
28 ; ELF: f3:
28 ; ELF-LABEL: f3:
2929 ; ELF: ldr r0, [sp]
3030 ; ELF-NEXT: mov pc, lr
31 ; DARWIN: f3:
31 ; DARWIN-LABEL: f3:
3232 ; DARWIN: mov r0, r3
3333 ; DARWIN-NEXT: mov pc, lr
3434 define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
44
55 define i8* @t() nounwind {
66 entry:
7 ; DARWIN: t:
7 ; DARWIN-LABEL: t:
88 ; DARWIN: mov r0, r7
99
10 ; LINUX: t:
10 ; LINUX-LABEL: t:
1111 ; LINUX: mov r0, r11
1212 %0 = call i8* @llvm.frameaddress(i32 0)
1313 ret i8* %0
66
77 define i8* @rt0(i32 %x) nounwind readnone {
88 entry:
9 ; CHECK: rt0:
9 ; CHECK-LABEL: rt0:
1010 ; CHECK: {r7, lr}
1111 ; CHECK: mov r0, lr
1212 %0 = tail call i8* @llvm.returnaddress(i32 0)
1515
1616 define i8* @rt2() nounwind readnone {
1717 entry:
18 ; CHECK: rt2:
18 ; CHECK-LABEL: rt2:
1919 ; CHECK: {r7, lr}
2020 ; CHECK: ldr r[[R0:[0-9]+]], [r7]
2121 ; CHECK: ldr r0, [r0]
1111 ; CHECK: bne
1212 ; CHECK: dmb {{ish$}}
1313
14 ; CHECK-THUMB: test1:
14 ; CHECK-THUMB-LABEL: test1:
1515 ; CHECK-THUMB: dmb {{ish$}}
1616 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
1717 ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
3636 ; CHECK: bne
3737 ; CHECK: dmb {{ish$}}
3838
39 ; CHECK-THUMB: test2:
39 ; CHECK-THUMB-LABEL: test2:
4040 ; CHECK-THUMB: dmb {{ish$}}
4141 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
4242 ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
6161 ; CHECK: bne
6262 ; CHECK: dmb {{ish$}}
6363
64 ; CHECK-THUMB: test3:
64 ; CHECK-THUMB-LABEL: test3:
6565 ; CHECK-THUMB: dmb {{ish$}}
6666 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
6767 ; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
8686 ; CHECK: bne
8787 ; CHECK: dmb {{ish$}}
8888
89 ; CHECK-THUMB: test4:
89 ; CHECK-THUMB-LABEL: test4:
9090 ; CHECK-THUMB: dmb {{ish$}}
9191 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
9292 ; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
111111 ; CHECK: bne
112112 ; CHECK: dmb {{ish$}}
113113
114 ; CHECK-THUMB: test5:
114 ; CHECK-THUMB-LABEL: test5:
115115 ; CHECK-THUMB: dmb {{ish$}}
116116 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
117117 ; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
134134 ; CHECK: bne
135135 ; CHECK: dmb {{ish$}}
136136
137 ; CHECK-THUMB: test6:
137 ; CHECK-THUMB-LABEL: test6:
138138 ; CHECK-THUMB: dmb {{ish$}}
139139 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
140140 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
158158 ; CHECK: bne
159159 ; CHECK: dmb {{ish$}}
160160
161 ; CHECK-THUMB: test7:
161 ; CHECK-THUMB-LABEL: test7:
162162 ; CHECK-THUMB: dmb {{ish$}}
163163 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
164164 ; CHECK-THUMB: cmp [[REG1]]
187187 ; CHECK: bne
188188 ; CHECK: dmb {{ish$}}
189189
190 ; CHECK-THUMB: test8:
190 ; CHECK-THUMB-LABEL: test8:
191191 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
192192 ; CHECK-THUMB: cmp [[REG1]]
193193 ; CHECK-THUMB: it eq
213213 ; CHECK: bne
214214 ; CHECK: dmb {{ish$}}
215215
216 ; CHECK-THUMB: test9:
216 ; CHECK-THUMB-LABEL: test9:
217217 ; CHECK-THUMB: dmb {{ish$}}
218218 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
219219 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
237237 ; CHECK: bne
238238 ; CHECK: dmb {{ish$}}
239239
240 ; CHECK-THUMB: test10:
240 ; CHECK-THUMB-LABEL: test10:
241241 ; CHECK-THUMB: dmb {{ish$}}
242242 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
243243 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
265265 ; CHECK: dmb {{ish$}}
266266
267267
268 ; CHECK-THUMB: test11:
268 ; CHECK-THUMB-LABEL: test11:
269269 ; CHECK-THUMB: dmb {{ish$}}
270270 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
271271 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
292292 ; CHECK: bne
293293 ; CHECK: dmb {{ish$}}
294294
295 ; CHECK-THUMB: test12:
295 ; CHECK-THUMB-LABEL: test12:
296296 ; CHECK-THUMB: dmb {{ish$}}
297297 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
298298 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
319319 ; CHECK: bne
320320 ; CHECK: dmb {{ish$}}
321321
322 ; CHECK-THUMB: test13:
322 ; CHECK-THUMB-LABEL: test13:
323323 ; CHECK-THUMB: dmb {{ish$}}
324324 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
325325 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
22 ; rdar://8964854
33
44 define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
5 ; ARM: t:
5 ; ARM-LABEL: t:
66 ; ARM: ldrexb
77 ; ARM: strexb
88
9 ; T2: t:
9 ; T2-LABEL: t:
1010 ; T2: ldrexb
1111 ; T2: strexb
1212 %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic
0 ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
11
2 ; CHECK: max:
2 ; CHECK-LABEL: max:
33 define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
44 {
55 ; CHECK: ldrex
99 ret i32 %old
1010 }
1111
12 ; CHECK: min:
12 ; CHECK-LABEL: min:
1313 define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
1414 {
1515 ; CHECK: ldrex
55
66 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
77 entry:
8 ; CHECK: t1:
8 ; CHECK-LABEL: t1:
99 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
1010 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
1111 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
1919 ; rdar://10357570
2020 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
2121 entry:
22 ; CHECK: t2:
22 ; CHECK-LABEL: t2:
2323 %tobool7 = icmp eq i32* %ptr2, null
2424 br i1 %tobool7, label %while.end, label %while.body
2525
5353 ; rdar://12878928
5454 define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
5555 entry:
56 ; CHECK: t3:
56 ; CHECK-LABEL: t3:
5757 %tobool7 = icmp eq i32* %ptr2, null
5858 br i1 %tobool7, label %while.end, label %while.body
5959
11
22 ; 4278190095 = 0xff00000f
33 define i32 @f1(i32 %a) {
4 ; CHECK: f1:
4 ; CHECK-LABEL: f1:
55 ; CHECK: bfc
66 %tmp = and i32 %a, 4278190095
77 ret i32 %tmp
99
1010 ; 4286578688 = 0xff800000
1111 define i32 @f2(i32 %a) {
12 ; CHECK: f2:
12 ; CHECK-LABEL: f2:
1313 ; CHECK: bfc
1414 %tmp = and i32 %a, 4286578688
1515 ret i32 %tmp
1717
1818 ; 4095 = 0x00000fff
1919 define i32 @f3(i32 %a) {
20 ; CHECK: f3:
20 ; CHECK-LABEL: f3:
2121 ; CHECK: bfc
2222 %tmp = and i32 %a, 4095
2323 ret i32 %tmp
5151 ; rdar://8458663
5252 define i32 @f5(i32 %a, i32 %b) nounwind {
5353 entry:
54 ; CHECK: f5:
54 ; CHECK-LABEL: f5:
5555 ; CHECK-NOT: bfc
5656 ; CHECK: bfi r0, r1, #20, #4
5757 %0 = and i32 %a, -15728641
6464 ; rdar://9609030
6565 define i32 @f6(i32 %a, i32 %b) nounwind readnone {
6666 entry:
67 ; CHECK: f6:
67 ; CHECK-LABEL: f6:
6868 ; CHECK-NOT: bic
6969 ; CHECK: bfi r0, r1, #8, #9
7070 %and = and i32 %a, -130817
0 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
11
22 define i32 @t1(i32 %x) nounwind {
3 ; CHECK: t1:
3 ; CHECK-LABEL: t1:
44 ; CHECK-NOT: InlineAsm
55 ; CHECK: rev
66 %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
33
44 define void @t1() noreturn minsize nounwind ssp {
55 entry:
6 ; ARM: t1:
6 ; ARM-LABEL: t1:
77 ; ARM: bl _bar
88
9 ; SWIFT: t1:
9 ; SWIFT-LABEL: t1:
1010 ; SWIFT: bl _bar
1111 tail call void @bar() noreturn nounwind
1212 unreachable
1414
1515 define void @t2() noreturn minsize nounwind ssp {
1616 entry:
17 ; ARM: t2:
17 ; ARM-LABEL: t2:
1818 ; ARM: bl _t1
1919
20 ; SWIFT: t2:
20 ; SWIFT-LABEL: t2:
2121 ; SWIFT: bl _t1
2222 tail call void @t1() noreturn nounwind
2323 unreachable
33
44 define void @t1() noreturn nounwind ssp {
55 entry:
6 ; ARM: t1:
6 ; ARM-LABEL: t1:
77 ; ARM: mov lr, pc
88 ; ARM: b _bar
99
10 ; SWIFT: t1:
10 ; SWIFT-LABEL: t1:
1111 ; SWIFT: mov lr, pc
1212 ; SWIFT: b _bar
1313 tail call void @bar() noreturn nounwind
1616
1717 define void @t2() noreturn nounwind ssp {
1818 entry:
19 ; ARM: t2:
19 ; ARM-LABEL: t2:
2020 ; ARM: mov lr, pc
2121 ; ARM: b _t1
2222
23 ; SWIFT: t2:
23 ; SWIFT-LABEL: t2:
2424 ; SWIFT: mov lr, pc
2525 ; SWIFT: b _t1
2626 tail call void @t1() noreturn nounwind
1010 declare void @g(i32, i32, i32, i32)
1111
1212 define void @t1() {
13 ; CHECKELF: t1:
13 ; CHECKELF-LABEL: t1:
1414 ; CHECKELF: bl g(PLT)
1515 call void @g( i32 1, i32 2, i32 3, i32 4 )
1616 ret void
1717 }
1818
1919 define void @t2() {
20 ; CHECKV6: t2:
20 ; CHECKV6-LABEL: t2:
2121 ; CHECKV6: bx r0
22 ; CHECKT2D: t2:
22 ; CHECKT2D-LABEL: t2:
2323 ; CHECKT2D: ldr
2424 ; CHECKT2D-NEXT: ldr
2525 ; CHECKT2D-NEXT: bx r0
2929 }
3030
3131 define void @t3() {
32 ; CHECKV6: t3:
32 ; CHECKV6-LABEL: t3:
3333 ; CHECKV6: b _t2
34 ; CHECKELF: t3:
34 ; CHECKELF-LABEL: t3:
3535 ; CHECKELF: b t2(PLT)
36 ; CHECKT2D: t3:
36 ; CHECKT2D-LABEL: t3:
3737 ; CHECKT2D: b.w _t2
3838
3939 tail call void @t2( ) ; [#uses=0]
4343 ; Sibcall optimization of expanded libcalls. rdar://8707777
4444 define double @t4(double %a) nounwind readonly ssp {
4545 entry:
46 ; CHECKV6: t4:
46 ; CHECKV6-LABEL: t4:
4747 ; CHECKV6: b _sin
48 ; CHECKELF: t4:
48 ; CHECKELF-LABEL: t4:
4949 ; CHECKELF: b sin(PLT)
5050 %0 = tail call double @sin(double %a) nounwind readonly ; [#uses=1]
5151 ret double %0
5353
5454 define float @t5(float %a) nounwind readonly ssp {
5555 entry:
56 ; CHECKV6: t5:
56 ; CHECKV6-LABEL: t5:
5757 ; CHECKV6: b _sinf
58 ; CHECKELF: t5:
58 ; CHECKELF-LABEL: t5:
5959 ; CHECKELF: b sinf(PLT)
6060 %0 = tail call float @sinf(float %a) nounwind readonly ; [#uses=1]
6161 ret float %0
6767
6868 define i32 @t6(i32 %a, i32 %b) nounwind readnone {
6969 entry:
70 ; CHECKV6: t6:
70 ; CHECKV6-LABEL: t6:
7171 ; CHECKV6: b ___divsi3
72 ; CHECKELF: t6:
72 ; CHECKELF-LABEL: t6:
7373 ; CHECKELF: b __aeabi_idiv(PLT)
7474 %0 = sdiv i32 %a, %b
7575 ret i32 %0
8181
8282 define void @t7() nounwind {
8383 entry:
84 ; CHECKT2D: t7:
84 ; CHECKT2D-LABEL: t7:
8585 ; CHECKT2D: blxeq _foo
8686 ; CHECKT2D-NEXT: pop.w
8787 ; CHECKT2D-NEXT: b.w _foo
100100 ; rdar://11140249
101101 define i32 @t8(i32 %x) nounwind ssp {
102102 entry:
103 ; CHECKT2D: t8:
103 ; CHECKT2D-LABEL: t8:
104104 ; CHECKT2D-NOT: push
105105 %and = and i32 %x, 1
106106 %tobool = icmp eq i32 %and, 0
146146 @x = external global i32, align 4
147147
148148 define i32 @t9() nounwind {
149 ; CHECKT2D: t9:
149 ; CHECKT2D-LABEL: t9:
150150 ; CHECKT2D: blx __ZN9MutexLockC1Ev
151151 ; CHECKT2D: blx __ZN9MutexLockD1Ev
152152 ; CHECKT2D: b.w ___divsi3
166166 ; Correctly preserve the input chain for the tailcall node in the bitcast case,
167167 ; otherwise the call to floorf is lost.
168168 define float @libcall_tc_test2(float* nocapture %a, float %b) {
169 ; CHECKT2D: libcall_tc_test2:
169 ; CHECKT2D-LABEL: libcall_tc_test2:
170170 ; CHECKT2D: blx _floorf
171171 ; CHECKT2D: b.w _truncf
172172 %1 = load float* %a, align 4
66 @numi = external global i32 ; [#uses=1]
77 @counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
88
9 ; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
9 ; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
1010 ; CHECK-NOT: bx lr
1111
1212 define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
5555 call void %fn()
5656 ret void
5757
58 ; CHECK: PR15520:
58 ; CHECK-LABEL: PR15520:
5959 ; CHECK: mov lr, pc
6060 ; CHECK: mov pc, r0
6161 }
0 ; RUN: llc < %s -march=arm | FileCheck %s
11
22 define i64 @f1(i64 %a, i64 %b) {
3 ; CHECK: f1:
3 ; CHECK-LABEL: f1:
44 ; CHECK: subs r
55 ; CHECK: sbc r
66 entry:
99 }
1010
1111 define i64 @f2(i64 %a, i64 %b) {
12 ; CHECK: f2:
12 ; CHECK-LABEL: f2:
1313 ; CHECK: adc r
1414 ; CHECK: subs r
1515 ; CHECK: sbc r
2121
2222 ; add with live carry
2323 define i64 @f3(i32 %al, i32 %bl) {
24 ; CHECK: f3:
24 ; CHECK-LABEL: f3:
2525 ; CHECK: adds r
2626 ; CHECK: adc r
2727 entry:
3838 ; rdar://10073745
3939 define i64 @f4(i64 %x) nounwind readnone {
4040 entry:
41 ; CHECK: f4:
41 ; CHECK-LABEL: f4:
4242 ; CHECK: rsbs r
4343 ; CHECK: rsc r
4444 %0 = sub nsw i64 0, %x
4848 ; rdar://12559385
4949 define i64 @f5(i32 %vi) {
5050 entry:
51 ; CHECK: f5:
51 ; CHECK-LABEL: f5:
5252 ; CHECK: movw [[REG:r[0-9]+]], #36102
5353 ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
5454 %v0 = zext i32 %vi to i64
66
77 define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
88 entry:
9 ; CHECK: t1:
9 ; CHECK-LABEL: t1:
1010 %0 = icmp eq %struct.list_head* %list, null
1111 br i1 %0, label %bb2, label %bb
1212
3232 ; rdar://8117827
3333 define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
3434 entry:
35 ; CHECK: t2:
35 ; CHECK-LABEL: t2:
3636 ; CHECK: beq LBB1_[[RET:.]]
3737 %0 = icmp eq i32 %passes, 0 ; [#uses=1]
3838 br i1 %0, label %bb5, label %bb.nph15
22 declare i32 @llvm.cttz.i32(i32, i1)
33
44 define i32 @f1(i32 %a) {
5 ; CHECK: f1:
5 ; CHECK-LABEL: f1:
66 ; CHECK: rbit
77 ; CHECK: clz
88 %tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
0 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
11
2 ; CHECK: f:
2 ; CHECK-LABEL: f:
33 define float @f(<4 x i16>* nocapture %in) {
44 ; CHECK: vldr
55 ; CHECK: vmovl.u16
0 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
11
22 define double @f1() nounwind {
3 ; CHECK: f1:
3 ; CHECK-LABEL: f1:
44 ; CHECK: .data_region
55 ; CHECK: .long 1413754129
66 ; CHECK: .long 1074340347
1010
1111
1212 define i32 @f2() {
13 ; CHECK: f2:
13 ; CHECK-LABEL: f2:
1414 ; CHECK: .data_region jt32
1515 ; CHECK: .end_data_region
1616
44
55 define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
66 entry:
7 ; A8: foo:
7 ; A8-LABEL: foo:
88 ; A8: bl ___divmodsi4
99 ; A8-NOT: bl ___divmodsi4
1010
11 ; SWIFT: foo:
11 ; SWIFT-LABEL: foo:
1212 ; SWIFT: sdiv
1313 ; SWIFT: mls
1414 ; SWIFT-NOT: bl __divmodsi4
2222
2323 define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
2424 entry:
25 ; A8: bar:
25 ; A8-LABEL: bar:
2626 ; A8: bl ___udivmodsi4
2727 ; A8-NOT: bl ___udivmodsi4
2828
29 ; SWIFT: bar:
29 ; SWIFT-LABEL: bar:
3030 ; SWIFT: udiv
3131 ; SWIFT: mls
3232 ; SWIFT-NOT: bl __udivmodsi4
4444
4545 define void @do_indent(i32 %cols) nounwind {
4646 entry:
47 ; A8: do_indent:
48 ; SWIFT: do_indent:
47 ; A8-LABEL: do_indent:
48 ; SWIFT-LABEL: do_indent:
4949 %0 = load i32* @flags, align 4
5050 %1 = and i32 %0, 67108864
5151 %2 = icmp eq i32 %1, 0
7676 ; rdar://11714607
7777 define i32 @howmany(i32 %x, i32 %y) nounwind {
7878 entry:
79 ; A8: howmany:
79 ; A8-LABEL: howmany:
8080 ; A8: bl ___udivmodsi4
8181 ; A8-NOT: ___udivsi3
8282
83 ; SWIFT: howmany:
83 ; SWIFT-LABEL: howmany:
8484 ; SWIFT: udiv
8585 ; SWIFT: mls
8686 ; SWIFT-NOT: bl __udivmodsi4
1414 declare void @__cxa_call_unexpected(i8*)
1515
1616 define i32 @main() {
17 ; CHECK: main:
17 ; CHECK-LABEL: main:
1818 entry:
1919 %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
2020 %0 = bitcast i8* %exception.i to i32*
111111
112112 declare void @_ZSt9terminatev()
113113
114 ; CHECK-FP: _Z4testiiiiiddddd:
114 ; CHECK-FP-LABEL: _Z4testiiiiiddddd:
115115 ; CHECK-FP: .fnstart
116116 ; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
117117 ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
123123 ; CHECK-FP: .handlerdata
124124 ; CHECK-FP: .fnend
125125
126 ; CHECK-FP-ELIM: _Z4testiiiiiddddd:
126 ; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
127127 ; CHECK-FP-ELIM: .fnstart
128128 ; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
129129 ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
133133 ; CHECK-FP-ELIM: .handlerdata
134134 ; CHECK-FP-ELIM: .fnend
135135
136 ; CHECK-V7-FP: _Z4testiiiiiddddd:
136 ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
137137 ; CHECK-V7-FP: .fnstart
138138 ; CHECK-V7-FP: .save {r4, r11, lr}
139139 ; CHECK-V7-FP: push {r4, r11, lr}
147147 ; CHECK-V7-FP: .handlerdata
148148 ; CHECK-V7-FP: .fnend
149149
150 ; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd:
150 ; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
151151 ; CHECK-V7-FP-ELIM: .fnstart
152152 ; CHECK-V7-FP-ELIM: .save {r4, lr}
153153 ; CHECK-V7-FP-ELIM: push {r4, lr}
172172 ret void
173173 }
174174
175 ; CHECK-FP: test2:
175 ; CHECK-FP-LABEL: test2:
176176 ; CHECK-FP: .fnstart
177177 ; CHECK-FP: .save {r11, lr}
178178 ; CHECK-FP: push {r11, lr}
182182 ; CHECK-FP: mov pc, lr
183183 ; CHECK-FP: .fnend
184184
185 ; CHECK-FP-ELIM: test2:
185 ; CHECK-FP-ELIM-LABEL: test2:
186186 ; CHECK-FP-ELIM: .fnstart
187187 ; CHECK-FP-ELIM: .save {r11, lr}
188188 ; CHECK-FP-ELIM: push {r11, lr}
190190 ; CHECK-FP-ELIM: mov pc, lr
191191 ; CHECK-FP-ELIM: .fnend
192192
193 ; CHECK-V7-FP: test2:
193 ; CHECK-V7-FP-LABEL: test2:
194194 ; CHECK-V7-FP: .fnstart
195195 ; CHECK-V7-FP: .save {r11, lr}
196196 ; CHECK-V7-FP: push {r11, lr}
199199 ; CHECK-V7-FP: pop {r11, pc}
200200 ; CHECK-V7-FP: .fnend
201201
202 ; CHECK-V7-FP-ELIM: test2:
202 ; CHECK-V7-FP-ELIM-LABEL: test2:
203203 ; CHECK-V7-FP-ELIM: .fnstart
204204 ; CHECK-V7-FP-ELIM: .save {r11, lr}
205205 ; CHECK-V7-FP-ELIM: push {r11, lr}
228228 ret i32 %add6
229229 }
230230
231 ; CHECK-FP: test3:
231 ; CHECK-FP-LABEL: test3:
232232 ; CHECK-FP: .fnstart
233233 ; CHECK-FP: .save {r4, r5, r11, lr}
234234 ; CHECK-FP: push {r4, r5, r11, lr}
238238 ; CHECK-FP: mov pc, lr
239239 ; CHECK-FP: .fnend
240240
241 ; CHECK-FP-ELIM: test3:
241 ; CHECK-FP-ELIM-LABEL: test3:
242242 ; CHECK-FP-ELIM: .fnstart
243243 ; CHECK-FP-ELIM: .save {r4, r5, r11, lr}
244244 ; CHECK-FP-ELIM: push {r4, r5, r11, lr}
246246 ; CHECK-FP-ELIM: mov pc, lr
247247 ; CHECK-FP-ELIM: .fnend
248248
249 ; CHECK-V7-FP: test3:
249 ; CHECK-V7-FP-LABEL: test3:
250250 ; CHECK-V7-FP: .fnstart
251251 ; CHECK-V7-FP: .save {r4, r5, r11, lr}
252252 ; CHECK-V7-FP: push {r4, r5, r11, lr}
255255 ; CHECK-V7-FP: pop {r4, r5, r11, pc}
256256 ; CHECK-V7-FP: .fnend
257257
258 ; CHECK-V7-FP-ELIM: test3:
258 ; CHECK-V7-FP-ELIM-LABEL: test3:
259259 ; CHECK-V7-FP-ELIM: .fnstart
260260 ; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr}
261261 ; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr}
272272 ret void
273273 }
274274
275 ; CHECK-FP: test4:
275 ; CHECK-FP-LABEL: test4:
276276 ; CHECK-FP: .fnstart
277277 ; CHECK-FP: mov pc, lr
278278 ; CHECK-FP: .cantunwind
279279 ; CHECK-FP: .fnend
280280
281 ; CHECK-FP-ELIM: test4:
281 ; CHECK-FP-ELIM-LABEL: test4:
282282 ; CHECK-FP-ELIM: .fnstart
283283 ; CHECK-FP-ELIM: mov pc, lr
284284 ; CHECK-FP-ELIM: .cantunwind
285285 ; CHECK-FP-ELIM: .fnend
286286
287 ; CHECK-V7-FP: test4:
287 ; CHECK-V7-FP-LABEL: test4:
288288 ; CHECK-V7-FP: .fnstart
289289 ; CHECK-V7-FP: bx lr
290290 ; CHECK-V7-FP: .cantunwind
291291 ; CHECK-V7-FP: .fnend
292292
293 ; CHECK-V7-FP-ELIM: test4:
293 ; CHECK-V7-FP-ELIM-LABEL: test4:
294294 ; CHECK-V7-FP-ELIM: .fnstart
295295 ; CHECK-V7-FP-ELIM: bx lr
296296 ; CHECK-V7-FP-ELIM: .cantunwind
22
33 define void @foo(i16* %ptr, i32 %a) nounwind {
44 entry:
5 ; CHECK: foo:
5 ; CHECK-LABEL: foo:
66 %tmp1 = icmp ult i32 %a, 100
77 br i1 %tmp1, label %bb1, label %bb2
88 bb1:
33
44 define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
55 entry:
6 ; THUMB: t1:
7 ; ARM: t1:
6 ; THUMB-LABEL: t1:
7 ; ARM-LABEL: t1:
88 %x = add i32 %a, %b
99 br i1 1, label %if.then, label %if.else
1010 ; THUMB-NOT: b {{\.?}}LBB0_1
1616 ; zext
1717
1818 define i8 @zext_1_8(i1 %a) nounwind ssp {
19 ; v7: zext_1_8:
19 ; v7-LABEL: zext_1_8:
2020 ; v7: and r0, r0, #1
21 ; prev6: zext_1_8:
21 ; prev6-LABEL: zext_1_8:
2222 ; prev6: and r0, r0, #1
2323 %r = zext i1 %a to i8
2424 ret i8 %r
2525 }
2626
2727 define i16 @zext_1_16(i1 %a) nounwind ssp {
28 ; v7: zext_1_16:
28 ; v7-LABEL: zext_1_16:
2929 ; v7: and r0, r0, #1
30 ; prev6: zext_1_16:
30 ; prev6-LABEL: zext_1_16:
3131 ; prev6: and r0, r0, #1
3232 %r = zext i1 %a to i16
3333 ret i16 %r
3434 }
3535
3636 define i32 @zext_1_32(i1 %a) nounwind ssp {
37 ; v7: zext_1_32:
37 ; v7-LABEL: zext_1_32:
3838 ; v7: and r0, r0, #1
39 ; prev6: zext_1_32:
39 ; prev6-LABEL: zext_1_32:
4040 ; prev6: and r0, r0, #1
4141 %r = zext i1 %a to i32
4242 ret i32 %r
4343 }
4444
4545 define i16 @zext_8_16(i8 %a) nounwind ssp {
46 ; v7: zext_8_16:
46 ; v7-LABEL: zext_8_16:
4747 ; v7: and r0, r0, #255
48 ; prev6: zext_8_16:
48 ; prev6-LABEL: zext_8_16:
4949 ; prev6: and r0, r0, #255
5050 %r = zext i8 %a to i16
5151 ret i16 %r
5252 }
5353
5454 define i32 @zext_8_32(i8 %a) nounwind ssp {
55 ; v7: zext_8_32:
55 ; v7-LABEL: zext_8_32:
5656 ; v7: and r0, r0, #255
57 ; prev6: zext_8_32:
57 ; prev6-LABEL: zext_8_32:
5858 ; prev6: and r0, r0, #255
5959 %r = zext i8 %a to i32
6060 ret i32 %r
6161 }
6262
6363 define i32 @zext_16_32(i16 %a) nounwind ssp {
64 ; v7: zext_16_32:
64 ; v7-LABEL: zext_16_32:
6565 ; v7: uxth r0, r0
66 ; prev6: zext_16_32:
66 ; prev6-LABEL: zext_16_32:
6767 ; prev6: lsl{{s?}} r0, r0, #16
6868 ; prev6: lsr{{s?}} r0, r0, #16
6969 %r = zext i16 %a to i32
7373 ; sext
7474
7575 define i8 @sext_1_8(i1 %a) nounwind ssp {
76 ; v7: sext_1_8:
76 ; v7-LABEL: sext_1_8:
7777 ; v7: lsl{{s?}} r0, r0, #31
7878 ; v7: asr{{s?}} r0, r0, #31
79 ; prev6: sext_1_8:
79 ; prev6-LABEL: sext_1_8:
8080 ; prev6: lsl{{s?}} r0, r0, #31
8181 ; prev6: asr{{s?}} r0, r0, #31
8282 %r = sext i1 %a to i8
8484 }
8585
8686 define i16 @sext_1_16(i1 %a) nounwind ssp {
87 ; v7: sext_1_16:
87 ; v7-LABEL: sext_1_16:
8888 ; v7: lsl{{s?}} r0, r0, #31
8989 ; v7: asr{{s?}} r0, r0, #31
90 ; prev6: sext_1_16:
90 ; prev6-LABEL: sext_1_16:
9191 ; prev6: lsl{{s?}} r0, r0, #31
9292 ; prev6: asr{{s?}} r0, r0, #31
9393 %r = sext i1 %a to i16
9595 }
9696
9797 define i32 @sext_1_32(i1 %a) nounwind ssp {
98 ; v7: sext_1_32:
98 ; v7-LABEL: sext_1_32:
9999 ; v7: lsl{{s?}} r0, r0, #31
100100 ; v7: asr{{s?}} r0, r0, #31
101 ; prev6: sext_1_32:
101 ; prev6-LABEL: sext_1_32:
102102 ; prev6: lsl{{s?}} r0, r0, #31
103103 ; prev6: asr{{s?}} r0, r0, #31
104104 %r = sext i1 %a to i32
106106 }
107107
108108 define i16 @sext_8_16(i8 %a) nounwind ssp {
109 ; v7: sext_8_16:
109 ; v7-LABEL: sext_8_16:
110110 ; v7: sxtb r0, r0
111 ; prev6: sext_8_16:
111 ; prev6-LABEL: sext_8_16:
112112 ; prev6: lsl{{s?}} r0, r0, #24
113113 ; prev6: asr{{s?}} r0, r0, #24
114114 %r = sext i8 %a to i16
116116 }
117117
118118 define i32 @sext_8_32(i8 %a) nounwind ssp {
119 ; v7: sext_8_32:
119 ; v7-LABEL: sext_8_32:
120120 ; v7: sxtb r0, r0
121 ; prev6: sext_8_32:
121 ; prev6-LABEL: sext_8_32:
122122 ; prev6: lsl{{s?}} r0, r0, #24
123123 ; prev6: asr{{s?}} r0, r0, #24
124124 %r = sext i8 %a to i32
126126 }
127127
128128 define i32 @sext_16_32(i16 %a) nounwind ssp {
129 ; v7: sext_16_32:
129 ; v7-LABEL: sext_16_32:
130130 ; v7: sxth r0, r0
131 ; prev6: sext_16_32:
131 ; prev6-LABEL: sext_16_32:
132132 ; prev6: lsl{{s?}} r0, r0, #16
133133 ; prev6: asr{{s?}} r0, r0, #16
134134 %r = sext i16 %a to i32
44
55 define i8* @frameaddr_index0() nounwind {
66 entry:
7 ; DARWIN-ARM: frameaddr_index0:
7 ; DARWIN-ARM-LABEL: frameaddr_index0:
88 ; DARWIN-ARM: push {r7}
99 ; DARWIN-ARM: mov r7, sp
1010 ; DARWIN-ARM: mov r0, r7
1111
12 ; DARWIN-THUMB2: frameaddr_index0:
12 ; DARWIN-THUMB2-LABEL: frameaddr_index0:
1313 ; DARWIN-THUMB2: str r7, [sp, #-4]!
1414 ; DARWIN-THUMB2: mov r7, sp
1515 ; DARWIN-THUMB2: mov r0, r7
1616
17 ; LINUX-ARM: frameaddr_index0:
17 ; LINUX-ARM-LABEL: frameaddr_index0:
1818 ; LINUX-ARM: push {r11}
1919 ; LINUX-ARM: mov r11, sp
2020 ; LINUX-ARM: mov r0, r11
2121
22 ; LINUX-THUMB2: frameaddr_index0:
22 ; LINUX-THUMB2-LABEL: frameaddr_index0:
2323 ; LINUX-THUMB2: str r7, [sp, #-4]!
2424 ; LINUX-THUMB2: mov r7, sp
2525 ; LINUX-THUMB2: mov r0, r7
3030
3131 define i8* @frameaddr_index1() nounwind {
3232 entry:
33 ; DARWIN-ARM: frameaddr_index1:
33 ; DARWIN-ARM-LABEL: frameaddr_index1:
3434 ; DARWIN-ARM: push {r7}
3535 ; DARWIN-ARM: mov r7, sp
3636 ; DARWIN-ARM: mov r0, r7
3737 ; DARWIN-ARM: ldr r0, [r0]
3838
39 ; DARWIN-THUMB2: frameaddr_index1:
39 ; DARWIN-THUMB2-LABEL: frameaddr_index1:
4040 ; DARWIN-THUMB2: str r7, [sp, #-4]!
4141 ; DARWIN-THUMB2: mov r7, sp
4242 ; DARWIN-THUMB2: mov r0, r7
4343 ; DARWIN-THUMB2: ldr r0, [r0]
4444
45 ; LINUX-ARM: frameaddr_index1:
45 ; LINUX-ARM-LABEL: frameaddr_index1:
4646 ; LINUX-ARM: push {r11}
4747 ; LINUX-ARM: mov r11, sp
4848 ; LINUX-ARM: ldr r0, [r11]
4949
50 ; LINUX-THUMB2: frameaddr_index1:
50 ; LINUX-THUMB2-LABEL: frameaddr_index1:
5151 ; LINUX-THUMB2: str r7, [sp, #-4]!
5252 ; LINUX-THUMB2: mov r7, sp
5353 ; LINUX-THUMB2: mov r0, r7
5959
6060 define i8* @frameaddr_index3() nounwind {
6161 entry:
62 ; DARWIN-ARM: frameaddr_index3:
62 ; DARWIN-ARM-LABEL: frameaddr_index3:
6363 ; DARWIN-ARM: push {r7}
6464 ; DARWIN-ARM: mov r7, sp
6565 ; DARWIN-ARM: mov r0, r7
6767 ; DARWIN-ARM: ldr r0, [r0]
6868 ; DARWIN-ARM: ldr r0, [r0]
6969
70 ; DARWIN-THUMB2: frameaddr_index3:
70 ; DARWIN-THUMB2-LABEL: frameaddr_index3:
7171 ; DARWIN-THUMB2: str r7, [sp, #-4]!
7272 ; DARWIN-THUMB2: mov r7, sp
7373 ; DARWIN-THUMB2: mov r0, r7
7575 ; DARWIN-THUMB2: ldr r0, [r0]
7676 ; DARWIN-THUMB2: ldr r0, [r0]
7777
78 ; LINUX-ARM: frameaddr_index3:
78 ; LINUX-ARM-LABEL: frameaddr_index3:
7979 ; LINUX-ARM: push {r11}
8080 ; LINUX-ARM: mov r11, sp
8181 ; LINUX-ARM: ldr r0, [r11]
8282 ; LINUX-ARM: ldr r0, [r0]
8383 ; LINUX-ARM: ldr r0, [r0]
8484
85 ; LINUX-THUMB2: frameaddr_index3:
85 ; LINUX-THUMB2-LABEL: frameaddr_index3:
8686 ; LINUX-THUMB2: str r7, [sp, #-4]!
8787 ; LINUX-THUMB2: mov r7, sp
8888 ; LINUX-THUMB2: mov r0, r7
55
66 define float @t1(float %acc, float %a, float %b) {
77 entry:
8 ; VFP2: t1:
8 ; VFP2-LABEL: t1:
99 ; VFP2: vmla.f32
1010
11 ; NEON: t1:
11 ; NEON-LABEL: t1:
1212 ; NEON: vmla.f32
1313
14 ; A8: t1:
14 ; A8-LABEL: t1:
1515 ; A8: vmul.f32
1616 ; A8: vadd.f32
1717 %0 = fmul float %a, %b
2121
2222 define double @t2(double %acc, double %a, double %b) {
2323 entry:
24 ; VFP2: t2:
24 ; VFP2-LABEL: t2:
2525 ; VFP2: vmla.f64
2626
27 ; NEON: t2:
27 ; NEON-LABEL: t2:
2828 ; NEON: vmla.f64
2929
30 ; A8: t2:
30 ; A8-LABEL: t2:
3131 ; A8: vmul.f64
3232 ; A8: vadd.f64
3333 %0 = fmul double %a, %b
3737
3838 define float @t3(float %acc, float %a, float %b) {
3939 entry:
40 ; VFP2: t3:
40 ; VFP2-LABEL: t3:
4141 ; VFP2: vmla.f32
4242
43 ; NEON: t3:
43 ; NEON-LABEL: t3:
4444 ; NEON: vmla.f32
4545
46 ; A8: t3:
46 ; A8-LABEL: t3:
4747 ; A8: vmul.f32
4848 ; A8: vadd.f32
4949 %0 = fmul float %a, %b
5555 ; rdar://8659675
5656 define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
5757 entry:
58 ; A8: t4:
58 ; A8-LABEL: t4:
5959 ; A8: vmul.f32
6060 ; A8: vmul.f32
6161 ; A8: vadd.f32
6262 ; A8: vadd.f32
6363
6464 ; Two vmla with now RAW hazard
65 ; A9: t4:
65 ; A9-LABEL: t4:
6666 ; A9: vmla.f32
6767 ; A9: vmla.f32
6868
69 ; HARD: t4:
69 ; HARD-LABEL: t4:
7070 ; HARD: vmla.f32 s0, s1, s2
7171 ; HARD: vmla.f32 s3, s1, s4
7272 %0 = fmul float %a, %b
8080
8181 define float @t5(float %a, float %b, float %c, float %d, float %e) {
8282 entry:
83 ; A8: t5:
83 ; A8-LABEL: t5:
8484 ; A8: vmul.f32
8585 ; A8: vmul.f32
8686 ; A8: vadd.f32
8787 ; A8: vadd.f32
8888
89 ; A9: t5:
89 ; A9-LABEL: t5:
9090 ; A9: vmla.f32
9191 ; A9: vmul.f32
9292 ; A9: vadd.f32
9393
94 ; HARD: t5:
94 ; HARD-LABEL: t5:
9595 ; HARD: vmla.f32 s4, s0, s1
9696 ; HARD: vmul.f32 s0, s2, s3
9797 ; HARD: vadd.f32 s0, s4, s0
33
44 define float @t1(float %acc, float %a, float %b) {
55 entry:
6 ; VFP2: t1:
6 ; VFP2-LABEL: t1:
77 ; VFP2: vnmls.f32
88
9 ; NEON: t1:
9 ; NEON-LABEL: t1:
1010 ; NEON: vnmls.f32
1111
12 ; A8: t1:
12 ; A8-LABEL: t1:
1313 ; A8: vmul.f32
1414 ; A8: vsub.f32
1515 %0 = fmul float %a, %b
1919
2020 define double @t2(double %acc, double %a, double %b) {
2121 entry:
22 ; VFP2: t2:
22 ; VFP2-LABEL: t2:
2323 ; VFP2: vnmls.f64
2424
25 ; NEON: t2:
25 ; NEON-LABEL: t2:
2626 ; NEON: vnmls.f64
2727
28 ; A8: t2:
28 ; A8-LABEL: t2:
2929 ; A8: vmul.f64
3030 ; A8: vsub.f64
3131 %0 = fmul double %a, %b
33
44 define float @t1(float %acc, float %a, float %b) {
55 entry:
6 ; VFP2: t1:
6 ; VFP2-LABEL: t1:
77 ; VFP2: vmls.f32
88
9 ; NEON: t1:
9 ; NEON-LABEL: t1:
1010 ; NEON: vmls.f32
1111
12 ; A8: t1:
12 ; A8-LABEL: t1:
1313 ; A8: vmul.f32
1414 ; A8: vsub.f32
1515 %0 = fmul float %a, %b
1919
2020 define double @t2(double %acc, double %a, double %b) {
2121 entry:
22 ; VFP2: t2:
22 ; VFP2-LABEL: t2:
2323 ; VFP2: vmls.f64
2424
25 ; NEON: t2:
25 ; NEON-LABEL: t2:
2626 ; NEON: vmls.f64
2727
28 ; A8: t2:
28 ; A8-LABEL: t2:
2929 ; A8: vmul.f64
3030 ; A8: vsub.f64
3131 %0 = fmul double %a, %b
66
77 define float @t1(float %acc, float %a, float %b) nounwind {
88 entry:
9 ; VFP2: t1:
9 ; VFP2-LABEL: t1:
1010 ; VFP2: vnmla.f32
1111
12 ; NEON: t1:
12 ; NEON-LABEL: t1:
1313 ; NEON: vnmla.f32
1414
15 ; A8U: t1:
15 ; A8U-LABEL: t1:
1616 ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
1717 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
1818
19 ; A8: t1:
19 ; A8-LABEL: t1:
2020 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
2121 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
2222 %0 = fmul float %a, %b
2727
2828 define float @t2(float %acc, float %a, float %b) nounwind {
2929 entry:
30 ; VFP2: t2:
30 ; VFP2-LABEL: t2:
3131 ; VFP2: vnmla.f32
3232
33 ; NEON: t2:
33 ; NEON-LABEL: t2:
3434 ; NEON: vnmla.f32
3535
36 ; A8U: t2:
36 ; A8U-LABEL: t2:
3737 ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
3838 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
3939
40 ; A8: t2:
40 ; A8-LABEL: t2:
4141 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
4242 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
4343 %0 = fmul float %a, %b
4848
4949 define double @t3(double %acc, double %a, double %b) nounwind {
5050 entry:
51 ; VFP2: t3:
51 ; VFP2-LABEL: t3:
5252 ; VFP2: vnmla.f64
5353
54 ; NEON: t3:
54 ; NEON-LABEL: t3:
5555 ; NEON: vnmla.f64
5656
57 ; A8U: t3:
57 ; A8U-LABEL: t3:
5858 ; A8U: vnmul.f64 d
5959 ; A8U: vsub.f64 d
6060
61 ; A8: t3:
61 ; A8-LABEL: t3:
6262 ; A8: vnmul.f64 d
6363 ; A8: vsub.f64 d
6464 %0 = fmul double %a, %b
6969
7070 define double @t4(double %acc, double %a, double %b) nounwind {
7171 entry:
72 ; VFP2: t4:
72 ; VFP2-LABEL: t4:
7373 ; VFP2: vnmla.f64
7474
75 ; NEON: t4:
75 ; NEON-LABEL: t4:
7676 ; NEON: vnmla.f64
7777
78 ; A8U: t4:
78 ; A8U-LABEL: t4:
7979 ; A8U: vnmul.f64 d
8080 ; A8U: vsub.f64 d
8181
82 ; A8: t4:
82 ; A8-LABEL: t4:
8383 ; A8: vnmul.f64 d
8484 ; A8: vsub.f64 d
8585 %0 = fmul double %a, %b
0 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
11
22 define float @f(i32 %a) {
3 ;CHECK: f:
3 ;CHECK-LABEL: f:
44 ;CHECK: vmov
55 ;CHECK-NEXT: vcvt.f32.s32
66 ;CHECK-NEXT: vmov
1010 }
1111
1212 define double @g(i32 %a) {
13 ;CHECK: g:
13 ;CHECK-LABEL: g:
1414 ;CHECK: vmov
1515 ;CHECK-NEXT: vcvt.f64.s32
1616 ;CHECK-NEXT: vmov
2020 }
2121
2222 define double @uint_to_double(i32 %a) {
23 ;CHECK: uint_to_double:
23 ;CHECK-LABEL: uint_to_double:
2424 ;CHECK: vmov
2525 ;CHECK-NEXT: vcvt.f64.u32
2626 ;CHECK-NEXT: vmov
3030 }
3131
3232 define float @uint_to_float(i32 %a) {
33 ;CHECK: uint_to_float:
33 ;CHECK-LABEL: uint_to_float:
3434 ;CHECK: vmov
3535 ;CHECK-NEXT: vcvt.f32.u32
3636 ;CHECK-NEXT: vmov
4040 }
4141
4242 define double @h(double* %v) {
43 ;CHECK: h:
43 ;CHECK-LABEL: h:
4444 ;CHECK: vldr
4545 ;CHECK-NEXT: vmov
4646 entry:
4949 }
5050
5151 define float @h2() {
52 ;CHECK: h2:
52 ;CHECK-LABEL: h2:
5353 ;CHECK: mov r0, #1065353216
5454 entry:
5555 ret float 1.000000e+00
5656 }
5757
5858 define double @f2(double %a) {
59 ;CHECK: f2:
59 ;CHECK-LABEL: f2:
6060 ;CHECK-NOT: vmov
6161 ret double %a
6262 }
6363
6464 define void @f3() {
65 ;CHECK: f3:
65 ;CHECK-LABEL: f3:
6666 ;CHECK-NOT: vmov
6767 ;CHECK: f4
6868 entry:
77 @z = common global i16 0
88
99 define arm_aapcs_vfpcc void @foo() nounwind {
10 ; CHECK: foo:
11 ; CHECK-FP6: foo:
10 ; CHECK-LABEL: foo:
11 ; CHECK-FP6-LABEL: foo:
1212 entry:
1313 %0 = load i16* @x, align 2
1414 %1 = load i16* @y, align 2
0 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
11
22 define float @f1(float %a, float %b) {
3 ;CHECK: f1:
3 ;CHECK-LABEL: f1:
44 ;CHECK: vadd.f32
55 entry:
66 %tmp = fadd float %a, %b ; [#uses=1]
88 }
99
1010 define double @f2(double %a, double %b) {
11 ;CHECK: f2:
11 ;CHECK-LABEL: f2:
1212 ;CHECK: vadd.f64
1313 entry:
1414 %tmp = fadd double %a, %b ; [#uses=1]
1616 }
1717
1818 define float @f3(float %a, float %b) {
19 ;CHECK: f3:
19 ;CHECK-LABEL: f3:
2020 ;CHECK: vmul.f32
2121 entry:
2222 %tmp = fmul float %a, %b ; [#uses=1]
2424 }
2525
2626 define double @f4(double %a, double %b) {
27 ;CHECK: f4:
27 ;CHECK-LABEL: f4:
2828 ;CHECK: vmul.f64
2929 entry:
3030 %tmp = fmul double %a, %b ; [#uses=1]
3232 }
3333
3434 define float @f5(float %a, float %b) {
35 ;CHECK: f5:
35 ;CHECK-LABEL: f5:
3636 ;CHECK: vsub.f32
3737 entry:
3838 %tmp = fsub float %a, %b ; [#uses=1]
4040 }
4141
4242 define double @f6(double %a, double %b) {
43 ;CHECK: f6:
43 ;CHECK-LABEL: f6:
4444 ;CHECK: vsub.f64
4545 entry:
4646 %tmp = fsub double %a, %b ; [#uses=1]
4848 }
4949
5050 define float @f7(float %a) {
51 ;CHECK: f7:
51 ;CHECK-LABEL: f7:
5252 ;CHECK: eor
5353 entry:
5454 %tmp1 = fsub float -0.000000e+00, %a ; [#uses=1]
5656 }
5757
5858 define double @f8(double %a) {
59 ;CHECK: f8:
59 ;CHECK-LABEL: f8:
6060 ;CHECK: vneg.f64
6161 entry:
6262 %tmp1 = fsub double -0.000000e+00, %a ; [#uses=1]
6464 }
6565
6666 define float @f9(float %a, float %b) {
67 ;CHECK: f9:
67 ;CHECK-LABEL: f9:
6868 ;CHECK: vdiv.f32
6969 entry:
7070 %tmp1 = fdiv float %a, %b ; [#uses=1]
7272 }
7373
7474 define double @f10(double %a, double %b) {
75 ;CHECK: f10:
75 ;CHECK-LABEL: f10:
7676 ;CHECK: vdiv.f64
7777 entry:
7878 %tmp1 = fdiv double %a, %b ; [#uses=1]
8080 }
8181
8282 define float @f11(float %a) {
83 ;CHECK: f11:
83 ;CHECK-LABEL: f11:
8484 ;CHECK: bic
8585 entry:
8686 %tmp1 = call float @fabsf( float %a ) readnone ; [#uses=1]
9090 declare float @fabsf(float)
9191
9292 define double @f12(double %a) {
93 ;CHECK: f12:
93 ;CHECK-LABEL: f12:
9494 ;CHECK: vabs.f64
9595 entry:
9696 %tmp1 = call double @fabs( double %a ) readnone ; [#uses=1]
44 ; Disable this optimization unless we know one of them is zero.
55 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
66 entry:
7 ; CHECK: t1:
7 ; CHECK-LABEL: t1:
88 ; CHECK: vldr [[S0:s[0-9]+]],
99 ; CHECK: vldr [[S1:s[0-9]+]],
1010 ; CHECK: vcmpe.f32 [[S1]], [[S0]]
2828 ; +0.0 == -0.0
2929 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
3030 entry:
31 ; CHECK: t2:
31 ; CHECK-LABEL: t2:
3232 ; CHECK-NOT: vldr
3333 ; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
3434 ; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
5454
5555 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
5656 entry:
57 ; CHECK: t3:
57 ; CHECK-LABEL: t3:
5858 ; CHECK-NOT: vldr
5959 ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
6060 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
0 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
11
22 define i32 @f1(float %a) {
3 ;CHECK: f1:
3 ;CHECK-LABEL: f1:
44 ;CHECK: vcmpe.f32
55 ;CHECK: movmi
66 entry:
1010 }
1111
1212 define i32 @f2(float %a) {
13 ;CHECK: f2:
13 ;CHECK-LABEL: f2:
1414 ;CHECK: vcmpe.f32
1515 ;CHECK: moveq
1616 entry:
2020 }
2121
2222 define i32 @f3(float %a) {
23 ;CHECK: f3:
23 ;CHECK-LABEL: f3:
2424 ;CHECK: vcmpe.f32
2525 ;CHECK: movgt
2626 entry:
3030 }
3131
3232 define i32 @f4(float %a) {
33 ;CHECK: f4:
33 ;CHECK-LABEL: f4:
3434 ;CHECK: vcmpe.f32
3535 ;CHECK: movge
3636 entry:
4040 }
4141
4242 define i32 @f5(float %a) {
43 ;CHECK: f5:
43 ;CHECK-LABEL: f5:
4444 ;CHECK: vcmpe.f32
4545 ;CHECK: movls
4646 entry:
5050 }
5151
5252 define i32 @f6(float %a) {
53 ;CHECK: f6:
53 ;CHECK-LABEL: f6:
5454 ;CHECK: vcmpe.f32
5555 ;CHECK: movne
5656 entry:
6060 }
6161
6262 define i32 @g1(double %a) {
63 ;CHECK: g1:
63 ;CHECK-LABEL: g1:
6464 ;CHECK: vcmpe.f64
6565 ;CHECK: movmi
6666 entry:
22
33 define i32 @f7(float %a, float %b) {
44 entry:
5 ; CHECK: f7:
5 ; CHECK-LABEL: f7:
66 ; CHECK: vcmpe.f32
77 ; CHECK: vmrs APSR_nzcv, fpscr
88 ; CHECK: movweq
11
22 define float @t1(float %x) nounwind readnone optsize {
33 entry:
4 ; CHECK: t1:
4 ; CHECK-LABEL: t1:
55 ; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
66 %0 = fadd float %x, 4.000000e+00
77 ret float %0
99
1010 define double @t2(double %x) nounwind readnone optsize {
1111 entry:
12 ; CHECK: t2:
12 ; CHECK-LABEL: t2:
1313 ; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
1414 %0 = fadd double %x, 3.000000e+00
1515 ret double %0
1717
1818 define double @t3(double %x) nounwind readnone optsize {
1919 entry:
20 ; CHECK: t3:
20 ; CHECK-LABEL: t3:
2121 ; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
2222 %0 = fmul double %x, -1.300000e+01
2323 ret double %0
2525
2626 define float @t4(float %x) nounwind readnone optsize {
2727 entry:
28 ; CHECK: t4:
28 ; CHECK-LABEL: t4:
2929 ; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
3030 %0 = fmul float %x, -2.400000e+01
3131 ret float %0
11 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
22
33 define float @f1(double %x) {
4 ;CHECK-VFP: f1:
4 ;CHECK-VFP-LABEL: f1:
55 ;CHECK-VFP: vcvt.f32.f64
6 ;CHECK: f1:
6 ;CHECK-LABEL: f1:
77 ;CHECK: truncdfsf2
88 entry:
99 %tmp1 = fptrunc double %x to float ; [#uses=1]
1111 }
1212
1313 define double @f2(float %x) {
14 ;CHECK-VFP: f2:
14 ;CHECK-VFP-LABEL: f2:
1515 ;CHECK-VFP: vcvt.f64.f32
16 ;CHECK: f2:
16 ;CHECK-LABEL: f2:
1717 ;CHECK: extendsfdf2
1818 entry:
1919 %tmp1 = fpext float %x to double ; [#uses=1]
2121 }
2222
2323 define i32 @f3(float %x) {
24 ;CHECK-VFP: f3:
24 ;CHECK-VFP-LABEL: f3:
2525 ;CHECK-VFP: vcvt.s32.f32
26 ;CHECK: f3:
26 ;CHECK-LABEL: f3:
2727 ;CHECK: fixsfsi
2828 entry:
2929 %tmp = fptosi float %x to i32 ; [#uses=1]
3131 }
3232
3333 define i32 @f4(float %x) {
34 ;CHECK-VFP: f4:
34 ;CHECK-VFP-LABEL: f4:
3535 ;CHECK-VFP: vcvt.u32.f32
36 ;CHECK: f4:
36 ;CHECK-LABEL: f4:
3737 ;CHECK: fixunssfsi
3838 entry:
3939 %tmp = fptoui float %x to i32 ; [#uses=1]
4141 }
4242
4343 define i32 @f5(double %x) {
44 ;CHECK-VFP: f5:
44 ;CHECK-VFP-LABEL: f5:
4545 ;CHECK-VFP: vcvt.s32.f64
46 ;CHECK: f5:
46 ;CHECK-LABEL: f5:
4747 ;CHECK: fixdfsi
4848 entry:
4949 %tmp = fptosi double %x to i32 ; [#uses=1]
5151 }
5252
5353 define i32 @f6(double %x) {
54 ;CHECK-VFP: f6:
54 ;CHECK-VFP-LABEL: f6:
5555 ;CHECK-VFP: vcvt.u32.f64
56 ;CHECK: f6:
56 ;CHECK-LABEL: f6:
5757 ;CHECK: fixunsdfsi
5858 entry:
5959 %tmp = fptoui double %x to i32 ; [#uses=1]
6161 }
6262
6363 define float @f7(i32 %a) {
64 ;CHECK-VFP: f7:
64 ;CHECK-VFP-LABEL: f7:
6565 ;CHECK-VFP: vcvt.f32.s32
66 ;CHECK: f7:
66 ;CHECK-LABEL: f7:
6767 ;CHECK: floatsisf
6868 entry:
6969 %tmp = sitofp i32 %a to float ; [#uses=1]
7171 }
7272
7373