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Debug Info: Implement DwarfUnit::addRegisterOpPiece() using DwarfExpression. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225717 91177308-0d34-0410-b5e6-96231b3b80d8 Adrian Prantl 5 years ago
2 changed file(s) with 4 addition(s) and 57 deletion(s). Raw diff Collapse all Expand all
8989 // If this is a valid register number, emit it.
9090 if (Reg >= 0) {
9191 AddReg(Reg);
92 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
92 if (PieceSizeInBits)
93 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
9394 return;
9495 }
9596
428428 }
429429
430430 /// addRegisterOp - Add register operand.
431 // FIXME: Ideally, this would share the implementation with
432 // AsmPrinter::EmitDwarfRegOpPiece.
433431 bool DwarfUnit::addRegisterOpPiece(DIELoc &TheDie, unsigned Reg,
434432 unsigned SizeInBits, unsigned OffsetInBits) {
435 const TargetRegisterInfo *RI = Asm->TM.getSubtargetImpl()->getRegisterInfo();
436 int DWReg = RI->getDwarfRegNum(Reg, false);
437 bool isSubRegister = DWReg < 0;
438
439 unsigned Idx = 0;
440
441 // Go up the super-register chain until we hit a valid dwarf register number.
442 for (MCSuperRegIterator SR(Reg, RI); SR.isValid() && DWReg < 0; ++SR) {
443 DWReg = RI->getDwarfRegNum(*SR, false);
444 if (DWReg >= 0)
445 Idx = RI->getSubRegIndex(*SR, Reg);
446 }
447
448 if (DWReg < 0)
449 return false;
450
451 // Emit register.
452 if (DWReg < 32)
453 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + DWReg);
454 else {
455 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_regx);
456 addUInt(TheDie, dwarf::DW_FORM_udata, DWReg);
457 }
458
459 // Emit mask.
460 bool isPiece = SizeInBits > 0;
461 if (isSubRegister || isPiece) {
462 const unsigned SizeOfByte = 8;
463 unsigned RegSizeInBits = RI->getSubRegIdxSize(Idx);
464 unsigned RegOffsetInBits = RI->getSubRegIdxOffset(Idx);
465 unsigned PieceSizeInBits = std::max(SizeInBits, RegSizeInBits);
466 unsigned PieceOffsetInBits = OffsetInBits ? OffsetInBits : RegOffsetInBits;
467 assert(RegSizeInBits >= SizeInBits && "register smaller than value");
468
469 if (RegOffsetInBits != PieceOffsetInBits) {
470 // Manually shift the value into place, since the DW_OP_piece
471 // describes the part of the variable, not the position of the
472 // subregister.
473 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
474 addUInt(TheDie, dwarf::DW_FORM_data1, RegOffsetInBits);
475 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_shr);
476 }
477
478 if (PieceOffsetInBits > 0 || PieceSizeInBits % SizeOfByte) {
479 assert(PieceSizeInBits > 0 && "piece has zero size");
480 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_bit_piece);
481 addUInt(TheDie, dwarf::DW_FORM_data1, PieceSizeInBits);
482 addUInt(TheDie, dwarf::DW_FORM_data1, PieceOffsetInBits);
483 } else {
484 assert(PieceSizeInBits > 0 && "piece has zero size");
485 addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_piece);
486 addUInt(TheDie, dwarf::DW_FORM_data1, PieceSizeInBits/SizeOfByte);
487 }
488 }
433 DIEDwarfExpression Expr(Asm->TM, *this, TheDie);
434 Expr.AddMachineRegPiece(Reg, SizeInBits, OffsetInBits);
489435 return true;
490436 }
491437