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[ARM] GlobalISel: Add reg mapping for s64 G_FCMP Map the result into GPR and the operands into FPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307653 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
2 changed file(s) with 38 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
278278 }
279279 case G_FCMP: {
280280 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
281 (void)Ty1;
282281 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
283282 (void)Ty2;
284283 assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
285 assert(Ty1.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
286 assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
284 assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
285 "Mismatched operand sizes for G_FCMP");
286
287 unsigned Size = Ty1.getSizeInBits();
288 assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
289
290 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
291 : &ARM::ValueMappings[ARM::DPR3OpsIdx];
287292 OperandsMapping =
288293 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
289 &ARM::ValueMappings[ARM::SPR3OpsIdx],
290 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
294 FPRValueMapping, FPRValueMapping});
291295 break;
292296 }
293297 case G_MERGE_VALUES: {
3535
3636 define void @test_icmp_eq_s32() { ret void }
3737 define void @test_fcmp_one_s32() #0 { ret void }
38 define void @test_fcmp_ugt_s64() #0 { ret void }
3839
3940 define void @test_select_s32() { ret void }
4041
771772
772773 ...
773774 ---
775 name: test_fcmp_ugt_s64
776 # CHECK-LABEL: name: test_fcmp_ugt_s64
777 legalized: true
778 regBankSelected: false
779 selected: false
780 # CHECK: registers:
781 # CHECK: - { id: 0, class: fprb, preferred-register: '' }
782 # CHECK: - { id: 1, class: fprb, preferred-register: '' }
783 # CHECK: - { id: 2, class: gprb, preferred-register: '' }
784
785 registers:
786 - { id: 0, class: _ }
787 - { id: 1, class: _ }
788 - { id: 2, class: _ }
789 - { id: 3, class: _ }
790 body: |
791 bb.0:
792 liveins: %d0, %d1
793
794 %0(s64) = COPY %d0
795 %1(s64) = COPY %d1
796 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
797 %3(s32) = G_ZEXT %2(s1)
798 %r0 = COPY %3(s32)
799 BX_RET 14, _, implicit %r0
800
801 ...
802 ---
774803 name: test_select_s32
775804 # CHECK-LABEL: name: test_select_s32
776805 legalized: true