llvm.org GIT mirror llvm / 8adae96
Evict local live ranges if they can be reassigned. The previous change to local live range allocation also suppressed eviction of local ranges. In rare cases, this could result in more expensive register choices. This commit actually revives a feature that I added long ago: check if live ranges can be reassigned before eviction. But now it only happens in rare cases of evicting a local live range because another local live range wants a cheaper register. The benefit is improved code size for some benchmarks on x86 and armv7. I measured no significant compile time increase and performance changes are noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187140 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 6 years ago
5 changed file(s) with 35 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
260260 bool calcCompactRegion(GlobalSplitCandidate&);
261261 void splitAroundRegion(LiveRangeEdit&, ArrayRef);
262262 void calcGapWeights(unsigned, SmallVectorImpl&);
263 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
263264 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
264265 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
265266 void evictInterference(LiveInterval&, unsigned,
493494 // Interference eviction
494495 //===----------------------------------------------------------------------===//
495496
497 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
498 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
499 unsigned PhysReg;
500 while ((PhysReg = Order.next())) {
501 if (PhysReg == PrevReg)
502 continue;
503
504 MCRegUnitIterator Units(PhysReg, TRI);
505 for (; Units.isValid(); ++Units) {
506 // Instantiate a "subquery", not to be confused with the Queries array.
507 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
508 if (subQ.checkInterference())
509 break;
510 }
511 // If no units have interference, break out with the current PhysReg.
512 if (!Units.isValid())
513 break;
514 }
515 if (PhysReg)
516 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
517 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
518 << '\n');
519 return PhysReg;
520 }
521
496522 /// shouldEvict - determine if A should evict the assigned live range B. The
497523 /// eviction policy defined by this function together with the allocation order
498524 /// defined by enqueue() decides which registers ultimately end up being split
593619 // If !MaxCost.isMax(), then we're just looking for a cheap register.
594620 // Evicting another local live range in this case could lead to suboptimal
595621 // coloring.
596 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf))
622 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
623 !canReassign(*Intf, PhysReg)) {
597624 return false;
625 }
598626 // Finally, apply the eviction policy for non-urgent evictions.
599627 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
600628 return false;
None ; RUN: true
1 ; Disabled for a single commit only.
2 ; disabled: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
3 ; disabled: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s
0 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s
42 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
53 ; dependency) when it isn't dependent on last CPSR defining instruction.
64 ; rdar://8928208
None ; RUN: true
1 ; Disabled for a single commit only
2 ; disabled: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR
3 ; disabled: llc -mcpu=corei7 -no-stack-coloring=true < %s | FileCheck %s --check-prefix=NOCOLOR
0 ; RUN: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR
1 ; RUN: llc -mcpu=corei7 -no-stack-coloring=true < %s | FileCheck %s --check-prefix=NOCOLOR
42
53 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
64 target triple = "x86_64-apple-macosx10.8.0"
None ; RUN: true
1 ; disabled: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
2 ; Disabled for a single commit only.
0 ; RUN: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
31 define i64 @test1(i32 %xx, i32 %test) nounwind {
42 %conv = zext i32 %xx to i64
53 %and = and i32 %test, 7
66 ; flag to disable it for this test case.
77 ;
88 ; CHECK: @wrap_mul4
9 ; CHECK: 21 regalloc - Number of spills inserted
9 ; CHECK: 22 regalloc - Number of spills inserted
1010
1111 define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
1212 entry: