llvm.org GIT mirror llvm / 8aae8dd
Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper functions static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 7 years ago
2 changed file(s) with 45 addition(s) and 99 deletion(s). Raw diff Collapse all Expand all
1283912839 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
1284012840 // or XMM0_V32I8 in AVX all of this code can be replaced with that
1284112841 // in the .td file.
12842 MachineBasicBlock *
12843 X86TargetLowering::EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
12844 bool Implicit, bool MemArg) const {
12845 assert(Subtarget->hasSSE42() &&
12846 "Target must have SSE4.2 or AVX features enabled");
12842 static MachineBasicBlock * EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
12843 const TargetInstrInfo *TII) {
12844 unsigned Opc;
12845 switch (MI->getOpcode()) {
12846 default: llvm_unreachable("illegal opcode!");
12847 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
12848 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
12849 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
12850 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
12851 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
12852 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
12853 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
12854 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
12855 }
1284712856
1284812857 DebugLoc dl = MI->getDebugLoc();
12849 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12850 unsigned Opc;
12851 if (!Subtarget->hasAVX()) {
12852 if (MemArg)
12853 Opc = Implicit ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
12854 else
12855 Opc = Implicit ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
12856 } else {
12857 if (MemArg)
12858 Opc = Implicit ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
12859 else
12860 Opc = Implicit ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
12861 }
12862
12863 unsigned NumArgs = Implicit ? 3 : 5;
12864 if (MemArg)
12865 NumArgs += X86::AddrNumOperands;
12866
1286712858 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12859
12860 unsigned NumArgs = MI->getNumOperands() - 1;
1286812861 for (unsigned i = 0; i < NumArgs; ++i) {
1286912862 MachineOperand &Op = MI->getOperand(i+1);
1287012863 if (!(Op.isReg() && Op.isImplicit()))
1287112864 MIB.addOperand(Op);
1287212865 }
12873 if (MemArg)
12866 if (MI->hasOneMemOperand())
1287412867 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1287512868
1287612869 BuildMI(*BB, MI, dl,
1288312876
1288412877 // FIXME: Custom handling because TableGen doesn't support multiple implicit
1288512878 // defs in an instruction pattern
12886 MachineBasicBlock *
12887 X86TargetLowering::EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
12888 bool Implicit, bool MemArg) const {
12889 assert(Subtarget->hasSSE42() &&
12890 "Target must have SSE4.2 or AVX features enabled");
12879 static MachineBasicBlock * EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
12880 const TargetInstrInfo *TII) {
12881 unsigned Opc;
12882 switch (MI->getOpcode()) {
12883 default: llvm_unreachable("illegal opcode!");
12884 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
12885 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
12886 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
12887 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
12888 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
12889 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
12890 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
12891 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
12892 }
1289112893
1289212894 DebugLoc dl = MI->getDebugLoc();
12893 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12894 unsigned Opc;
12895 if (!Subtarget->hasAVX()) {
12896 if (MemArg)
12897 Opc = Implicit ? X86::PCMPISTRIrm : X86::PCMPESTRIrm;
12898 else
12899 Opc = Implicit ? X86::PCMPISTRIrr : X86::PCMPESTRIrr;
12900 } else {
12901 if (MemArg)
12902 Opc = Implicit ? X86::VPCMPISTRIrm : X86::VPCMPESTRIrm;
12903 else
12904 Opc = Implicit ? X86::VPCMPISTRIrr : X86::VPCMPESTRIrr;
12905 }
12906
12907 unsigned NumArgs = Implicit ? 3 : 5;
12908 if (MemArg)
12909 NumArgs += X86::AddrNumOperands;
12910
1291112895 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12896
12897 unsigned NumArgs = MI->getNumOperands() - 1; // remove the results
1291212898 for (unsigned i = 0; i < NumArgs; ++i) {
1291312899 MachineOperand &Op = MI->getOperand(i+1);
1291412900 if (!(Op.isReg() && Op.isImplicit()))
1291512901 MIB.addOperand(Op);
1291612902 }
12917 if (MemArg)
12903 if (MI->hasOneMemOperand())
1291812904 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1291912905
1292012906 BuildMI(*BB, MI, dl,
1394213928 case X86::PCMPESTRM128REG:
1394313929 case X86::VPCMPESTRM128REG:
1394413930 case X86::PCMPESTRM128MEM:
13945 case X86::VPCMPESTRM128MEM: {
13946 bool Implicit, MemArg;
13947 switch (MI->getOpcode()) {
13948 default: llvm_unreachable("illegal opcode!");
13949 case X86::PCMPISTRM128REG:
13950 case X86::VPCMPISTRM128REG:
13951 Implicit = true; MemArg = false; break;
13952 case X86::PCMPISTRM128MEM:
13953 case X86::VPCMPISTRM128MEM:
13954 Implicit = true; MemArg = true; break;
13955 case X86::PCMPESTRM128REG:
13956 case X86::VPCMPESTRM128REG:
13957 Implicit = false; MemArg = false; break;
13958 case X86::PCMPESTRM128MEM:
13959 case X86::VPCMPESTRM128MEM:
13960 Implicit = false; MemArg = true; break;
13961 }
13962 return EmitPCMPSTRM(MI, BB, Implicit, MemArg);
13963 }
13931 case X86::VPCMPESTRM128MEM:
13932 assert(Subtarget->hasSSE42() &&
13933 "Target must have SSE4.2 or AVX features enabled");
13934 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
1396413935
1396513936 // String/text processing lowering.
1396613937 case X86::PCMPISTRIREG:
1397013941 case X86::PCMPESTRIREG:
1397113942 case X86::VPCMPESTRIREG:
1397213943 case X86::PCMPESTRIMEM:
13973 case X86::VPCMPESTRIMEM: {
13974 bool Implicit, MemArg;
13975 switch (MI->getOpcode()) {
13976 default: llvm_unreachable("illegal opcode!");
13977 case X86::PCMPISTRIREG:
13978 case X86::VPCMPISTRIREG:
13979 Implicit = true; MemArg = false; break;
13980 case X86::PCMPISTRIMEM:
13981 case X86::VPCMPISTRIMEM:
13982 Implicit = true; MemArg = true; break;
13983 case X86::PCMPESTRIREG:
13984 case X86::VPCMPESTRIREG:
13985 Implicit = false; MemArg = false; break;
13986 case X86::PCMPESTRIMEM:
13987 case X86::VPCMPESTRIMEM:
13988 Implicit = false; MemArg = true; break;
13989 }
13990 return EmitPCMPSTRI(MI, BB, Implicit, MemArg);
13991 }
13992
13993 // Thread synchronization.
13944 case X86::VPCMPESTRIMEM:
13945 assert(Subtarget->hasSSE42() &&
13946 "Target must have SSE4.2 or AVX features enabled");
13947 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
13948
13949 // Thread synchronization.
1399413950 case X86::MONITOR:
1399513951 return EmitMonitor(MI, BB);
1399613952
1399813954 case X86::XBEGIN:
1399913955 return EmitXBegin(MI, BB);
1400013956
14001 // Atomic Lowering.
13957 // Atomic Lowering.
1400213958 case X86::ATOMAND8:
1400313959 case X86::ATOMAND16:
1400413960 case X86::ATOMAND32:
870870 const SmallVectorImpl &Outs,
871871 LLVMContext &Context) const;
872872
873 /// Utility functions to emit string processing sse4.2 instructions
874 /// that return in xmm0.
875 /// This takes the instruction to expand, the associated machine basic
876 /// block, the number of args, and whether or not the second arg is
877 /// in memory or not.
878 MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
879 bool Implicit, bool MemArg) const;
880 MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
881 bool Implicit, bool MemArg) const;
882
883873 /// Utility functions to emit monitor and mwait instructions. These
884874 /// need to make sure that the arguments to the intrinsic are in the
885875 /// correct registers.