llvm.org GIT mirror llvm / 8aa5d0f
[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317564 91177308-0d34-0410-b5e6-96231b3b80d8 Florian Hahn 1 year, 11 months ago
1 changed file(s) with 5 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
601601 /// Return true if B is a suB-vector of P, i.e. P is a suPer-vector of B.
602602 auto IsSubVec = [](MVT B, MVT P) -> bool {
603603 if (!B.isVector() || !P.isVector())
604 return false;
605 // Logically a <4 x i32> is a valid subvector of
606 // but until there are obvious use-cases for this, keep the
607 // types separate.
608 if (B.isScalableVector() != P.isScalableVector())
604609 return false;
605610 if (B.getVectorElementType() != P.getVectorElementType())
606611 return false;