llvm.org GIT mirror llvm / 8a9af26
AMDGPU/R600: Delete dead code. Dead or the same as the base implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275616 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 4 years ago
2 changed file(s) with 1 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
2929
3030 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
3131 : AMDGPUInstrInfo(ST), RI(), ST(ST) {}
32
33 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
34 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
35 }
3632
3733 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
3834 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
9591 }
9692 }
9793
98 // Some instructions act as place holders to emulate operations that the GPU
99 // hardware does automatically. This function can be used to check if
100 // an opcode falls into this category.
101 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
102 switch (Opcode) {
103 default: return false;
104 case AMDGPU::RETURN:
105 return true;
106 }
107 }
108
10994 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
11095 return false;
11196 }
141126 return ((TargetFlags & R600_InstFlag::LDS_1A) |
142127 (TargetFlags & R600_InstFlag::LDS_1A1D) |
143128 (TargetFlags & R600_InstFlag::LDS_1A2D));
144 }
145
146 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
147 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
148129 }
149130
150131 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
247228 return false;
248229 }
249230
250 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
251 static const unsigned OpTable[] = {
252 AMDGPU::OpName::src0,
253 AMDGPU::OpName::src1,
254 AMDGPU::OpName::src2
255 };
256
257 assert (SrcNum < 3);
258 return getOperandIdx(Opcode, OpTable[SrcNum]);
259 }
260
261231 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
262232 static const unsigned SrcSelTable[][2] = {
263233 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
406376 return Src;
407377 }
408378
409 static unsigned
410 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
379 static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
411380 switch (Swz) {
412381 case R600InstrInfo::ALU_VEC_012_SCL_210: {
413382 unsigned Cycles[3] = { 2, 1, 0};
427396 }
428397 default:
429398 llvm_unreachable("Wrong Swizzle for Trans Slot");
430 return 0;
431399 }
432400 }
433401
979947 return isPredicateSetter(MI.getOpcode());
980948 }
981949
982
983 bool
984 R600InstrInfo::SubsumesPredicate(ArrayRef Pred1,
985 ArrayRef Pred2) const {
986 return false;
987 }
988950
989951 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
990952 ArrayRef Pred) const {
14191381 // Instruction flag getters/setters
14201382 //===----------------------------------------------------------------------===//
14211383
1422 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1423 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1424 }
1425
14261384 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx,
14271385 unsigned Flag) const {
14281386 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
6767 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
6868 MachineBasicBlock::iterator MBBI) const override;
6969
70 bool isTrig(const MachineInstr &MI) const;
71 bool isPlaceHolderOpcode(unsigned opcode) const;
7270 bool isReductionOp(unsigned opcode) const;
7371 bool isCubeOp(unsigned opcode) const;
7472
7674 bool isALUInstr(unsigned Opcode) const;
7775 bool hasInstrModifiers(unsigned Opcode) const;
7876 bool isLDSInstr(unsigned Opcode) const;
79 bool isLDSNoRetInstr(unsigned Opcode) const;
8077 bool isLDSRetInstr(unsigned Opcode) const;
8178
8279 /// \returns true if this \p Opcode represents an ALU instruction or an
9996 bool definesAddressRegister(MachineInstr &MI) const;
10097 bool readsLDSSrcReg(const MachineInstr &MI) const;
10198
102 /// \returns The operand index for the given source number. Legal values
103 /// for SrcNum are 0, 1, and 2.
104 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
10599 /// \returns The operand Index for the Sel operand given an index to one
106100 /// of the instruction's src operands.
107101 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
190184 bool DefinesPredicate(MachineInstr &MI,
191185 std::vector &Pred) const override;
192186
193 bool SubsumesPredicate(ArrayRef Pred1,
194 ArrayRef Pred2) const override;
195
196187 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
197188 MachineBasicBlock &FMBB) const override;
198189
204195 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
205196 const MachineInstr &MI,
206197 unsigned *PredCost = nullptr) const override;
207
208 int getInstrLatency(const InstrItineraryData *ItinData,
209 SDNode *Node) const override { return 1;}
210198
211199 bool expandPostRAPseudo(MachineInstr &MI) const override;
212200
295283 /// \brief Helper function for setting instruction flag values.
296284 void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
297285
298 /// \returns true if this instruction has an operand for storing target flags.
299 bool hasFlagOperand(const MachineInstr &MI) const;
300
301286 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
302287 void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
303288