llvm.org GIT mirror llvm / 8a8d479
Move global variables in TargetMachine into new TargetOptions class. As an API change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8 Nick Lewycky 8 years ago
62 changed file(s) with 726 addition(s) and 600 deletion(s). Raw diff Collapse all Expand all
6969 ///
7070 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
7171
72 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
73 /// return the equivalent code if we're allowed to assume that NaNs won't occur.
74 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
75
7276 /// getICmpCondCode - Return the ISD condition code corresponding to
7377 /// the given LLVM IR integer condition code.
7478 ///
4343 class MCTargetAsmLexer;
4444 class MCTargetAsmParser;
4545 class TargetMachine;
46 class TargetOptions;
4647 class raw_ostream;
4748 class formatted_raw_ostream;
4849
8586 StringRef TT,
8687 StringRef CPU,
8788 StringRef Features,
89 const TargetOptions &Options,
8890 Reloc::Model RM,
8991 CodeModel::Model CM,
9092 CodeGenOpt::Level OL);
333335 /// either the target triple from the module, or the target triple of the
334336 /// host if that does not exist.
335337 TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
336 StringRef Features,
338 StringRef Features, const TargetOptions &Options,
337339 Reloc::Model RM = Reloc::Default,
338340 CodeModel::Model CM = CodeModel::Default,
339341 CodeGenOpt::Level OL = CodeGenOpt::Default) const {
340342 if (!TargetMachineCtorFn)
341343 return 0;
342 return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM, OL);
344 return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
345 RM, CM, OL);
343346 }
344347
345348 /// createMCAsmBackend - Create a target specific assembly parser.
10161019 private:
10171020 static TargetMachine *Allocator(const Target &T, StringRef TT,
10181021 StringRef CPU, StringRef FS,
1022 const TargetOptions &Options,
10191023 Reloc::Model RM,
10201024 CodeModel::Model CM,
10211025 CodeGenOpt::Level OL) {
1022 return new TargetMachineImpl(T, TT, CPU, FS, RM, CM, OL);
1026 return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
10231027 }
10241028 };
10251029
422422 /// NoHonorSignDependentRounding - This predicate is true if support for
423423 /// sign-dependent-rounding is not enabled.
424424 def NoHonorSignDependentRounding
425 : Predicate<"!HonorSignDependentRoundingFPMath()">;
425 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
426426
427427 class Requires preds> {
428428 list Predicates = preds;
1313 #ifndef LLVM_TARGET_TARGETMACHINE_H
1414 #define LLVM_TARGET_TARGETMACHINE_H
1515
16 #include "llvm/Target/TargetOptions.h"
1617 #include "llvm/MC/MCCodeGenInfo.h"
1718 #include "llvm/ADT/StringRef.h"
1819 #include
6263 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
6364 protected: // Can only create subclasses.
6465 TargetMachine(const Target &T, StringRef TargetTriple,
65 StringRef CPU, StringRef FS);
66 StringRef CPU, StringRef FS, const TargetOptions &Options);
6667
6768 /// getSubtargetImpl - virtual method implemented by subclasses that returns
6869 /// a reference to that target's TargetSubtargetInfo-derived member variable.
99100 const StringRef getTargetTriple() const { return TargetTriple; }
100101 const StringRef getTargetCPU() const { return TargetCPU; }
101102 const StringRef getTargetFeatureString() const { return TargetFS; }
103
104 TargetOptions Options;
102105
103106 // Interfaces to the major aspects of target machine information:
104107 // -- Instruction opcode and operand information
283286 class LLVMTargetMachine : public TargetMachine {
284287 protected: // Can only create subclasses.
285288 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
286 StringRef CPU, StringRef FS,
289 StringRef CPU, StringRef FS, TargetOptions Options,
287290 Reloc::Model RM, CodeModel::Model CM,
288291 CodeGenOpt::Level OL);
292
293 /// printNoVerify - Add a pass to dump the machine function, if debugging is
294 /// enabled.
295 ///
296 void printNoVerify(PassManagerBase &PM, const char *Banner) const;
297
298 /// printAndVerify - Add a pass to dump then verify the machine function, if
299 /// those steps are enabled.
300 ///
301 void printAndVerify(PassManagerBase &PM, const char *Banner) const;
289302
290303 private:
291304 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
1414 #ifndef LLVM_TARGET_TARGETOPTIONS_H
1515 #define LLVM_TARGET_TARGETOPTIONS_H
1616
17 #include
18
1719 namespace llvm {
1820 class MachineFunction;
1921 class StringRef;
2628 Hard // Hard float.
2729 };
2830 }
29
30 /// PrintMachineCode - This flag is enabled when the -print-machineinstrs
31 /// option is specified on the command line, and should enable debugging
32 /// output from the code generator.
33 extern bool PrintMachineCode;
3431
35 /// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
36 /// specified on the command line. If the target supports the frame pointer
37 /// elimination optimization, this option should disable it.
38 extern bool NoFramePointerElim;
39
40 /// NoFramePointerElimNonLeaf - This flag is enabled when the
41 /// -disable-non-leaf-fp-elim is specified on the command line. If the target
42 /// supports the frame pointer elimination optimization, this option should
43 /// disable it for non-leaf functions.
44 extern bool NoFramePointerElimNonLeaf;
45
46 /// DisableFramePointerElim - This returns true if frame pointer elimination
47 /// optimization should be disabled for the given machine function.
48 extern bool DisableFramePointerElim(const MachineFunction &MF);
49
50 /// LessPreciseFPMAD - This flag is enabled when the
51 /// -enable-fp-mad is specified on the command line. When this flag is off
52 /// (the default), the code generator is not allowed to generate mad
53 /// (multiply add) if the result is "less precise" than doing those operations
54 /// individually.
55 extern bool LessPreciseFPMADOption;
56 extern bool LessPreciseFPMAD();
57
58 /// NoExcessFPPrecision - This flag is enabled when the
59 /// -disable-excess-fp-precision flag is specified on the command line. When
60 /// this flag is off (the default), the code generator is allowed to produce
61 /// results that are "more precise" than IEEE allows. This includes use of
62 /// FMA-like operations and use of the X86 FP registers without rounding all
63 /// over the place.
64 extern bool NoExcessFPPrecision;
65
66 /// UnsafeFPMath - This flag is enabled when the
67 /// -enable-unsafe-fp-math flag is specified on the command line. When
68 /// this flag is off (the default), the code generator is not allowed to
69 /// produce results that are "less precise" than IEEE allows. This includes
70 /// use of X86 instructions like FSIN and FCOS instead of libcalls.
71 /// UnsafeFPMath implies LessPreciseFPMAD.
72 extern bool UnsafeFPMath;
73
74 /// NoInfsFPMath - This flag is enabled when the
75 /// -enable-no-infs-fp-math flag is specified on the command line. When
76 /// this flag is off (the default), the code generator is not allowed to
77 /// assume the FP arithmetic arguments and results are never +-Infs.
78 extern bool NoInfsFPMath;
79
80 /// NoNaNsFPMath - This flag is enabled when the
81 /// -enable-no-nans-fp-math flag is specified on the command line. When
82 /// this flag is off (the default), the code generator is not allowed to
83 /// assume the FP arithmetic arguments and results are never NaNs.
84 extern bool NoNaNsFPMath;
85
86 /// HonorSignDependentRoundingFPMath - This returns true when the
87 /// -enable-sign-dependent-rounding-fp-math is specified. If this returns
88 /// false (the default), the code generator is allowed to assume that the
89 /// rounding behavior is the default (round-to-zero for all floating point to
90 /// integer conversions, and round-to-nearest for all other arithmetic
91 /// truncations). If this is enabled (set to true), the code generator must
92 /// assume that the rounding mode may dynamically change.
93 extern bool HonorSignDependentRoundingFPMathOption;
94 extern bool HonorSignDependentRoundingFPMath();
95
96 /// UseSoftFloat - This flag is enabled when the -soft-float flag is specified
97 /// on the command line. When this flag is on, the code generator will
98 /// generate libcalls to the software floating point library instead of
99 /// target FP instructions.
100 extern bool UseSoftFloat;
101
102 /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
103 /// on the command line. This setting may either be Default, Soft, or Hard.
104 /// Default selects the target's default behavior. Soft selects the ABI for
105 /// UseSoftFloat, but does not inidcate that FP hardware may not be used.
106 /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
107 /// Hard presumes that the normal FP ABI is used.
108 extern FloatABI::ABIType FloatABIType;
109
110 /// NoZerosInBSS - By default some codegens place zero-initialized data to
111 /// .bss section. This flag disables such behaviour (necessary, e.g. for
112 /// crt*.o compiling).
113 extern bool NoZerosInBSS;
114
115 /// JITExceptionHandling - This flag indicates that the JIT should emit
116 /// exception handling information.
117 extern bool JITExceptionHandling;
118
119 /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit
120 /// debug information and notify a debugger about it.
121 extern bool JITEmitDebugInfo;
122
123 /// JITEmitDebugInfoToDisk - This flag indicates that the JIT should write
124 /// the object files generated by the JITEmitDebugInfo flag to disk. This
125 /// flag is hidden and is only for debugging the debug info.
126 extern bool JITEmitDebugInfoToDisk;
127
128 /// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
129 /// specified on the commandline. When the flag is on, participating targets
130 /// will perform tail call optimization on all calls which use the fastcc
131 /// calling convention and which satisfy certain target-independent
132 /// criteria (being at the end of a function, having the same return type
133 /// as their parent function, etc.), using an alternate ABI if necessary.
134 extern bool GuaranteedTailCallOpt;
135
136 /// StackAlignmentOverride - Override default stack alignment for target.
137 extern unsigned StackAlignmentOverride;
138
139 /// RealignStack - This flag indicates whether the stack should be
140 /// automatically realigned, if needed.
141 extern bool RealignStack;
142
143 /// DisableJumpTables - This flag indicates jump tables should not be
144 /// generated.
145 extern bool DisableJumpTables;
146
147 /// EnableFastISel - This flag enables fast-path instruction selection
148 /// which trades away generated code quality in favor of reducing
149 /// compile time.
150 extern bool EnableFastISel;
151
15232 /// StrongPHIElim - This flag enables more aggressive PHI elimination
15333 /// wth earlier copy coalescing.
15434 extern bool StrongPHIElim;
15535
156 /// getTrapFunctionName - If this returns a non-empty string, this means isel
157 /// should lower Intrinsic::trap to a call to the specified function name
158 /// instead of an ISD::TRAP node.
159 extern StringRef getTrapFunctionName();
36 class TargetOptions {
37 public:
38 TargetOptions()
39 : PrintMachineCode(false), NoFramePointerElim(false),
40 NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false),
41 NoExcessFPPrecision(false), UnsafeFPMath(false), NoInfsFPMath(false),
42 NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false),
43 UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false),
44 JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
45 GuaranteedTailCallOpt(false), StackAlignmentOverride(0),
46 RealignStack(true), DisableJumpTables(false), EnableFastISel(false),
47 EnableSegmentedStacks(false), TrapFuncName(""),
48 FloatABIType(FloatABI::Default)
49 {}
16050
161 extern bool EnableSegmentedStacks;
51 /// PrintMachineCode - This flag is enabled when the -print-machineinstrs
52 /// option is specified on the command line, and should enable debugging
53 /// output from the code generator.
54 unsigned PrintMachineCode : 1;
16255
56 /// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
57 /// specified on the command line. If the target supports the frame pointer
58 /// elimination optimization, this option should disable it.
59 unsigned NoFramePointerElim : 1;
60
61 /// NoFramePointerElimNonLeaf - This flag is enabled when the
62 /// -disable-non-leaf-fp-elim is specified on the command line. If the
63 /// target supports the frame pointer elimination optimization, this option
64 /// should disable it for non-leaf functions.
65 unsigned NoFramePointerElimNonLeaf : 1;
66
67 /// DisableFramePointerElim - This returns true if frame pointer elimination
68 /// optimization should be disabled for the given machine function.
69 bool DisableFramePointerElim(const MachineFunction &MF) const;
70
71 /// LessPreciseFPMAD - This flag is enabled when the
72 /// -enable-fp-mad is specified on the command line. When this flag is off
73 /// (the default), the code generator is not allowed to generate mad
74 /// (multiply add) if the result is "less precise" than doing those
75 /// operations individually.
76 unsigned LessPreciseFPMADOption : 1;
77 bool LessPreciseFPMAD() const;
78
79 /// NoExcessFPPrecision - This flag is enabled when the
80 /// -disable-excess-fp-precision flag is specified on the command line.
81 /// When this flag is off (the default), the code generator is allowed to
82 /// produce results that are "more precise" than IEEE allows. This includes
83 /// use of FMA-like operations and use of the X86 FP registers without
84 /// rounding all over the place.
85 unsigned NoExcessFPPrecision : 1;
86
87 /// UnsafeFPMath - This flag is enabled when the
88 /// -enable-unsafe-fp-math flag is specified on the command line. When
89 /// this flag is off (the default), the code generator is not allowed to
90 /// produce results that are "less precise" than IEEE allows. This includes
91 /// use of X86 instructions like FSIN and FCOS instead of libcalls.
92 /// UnsafeFPMath implies LessPreciseFPMAD.
93 unsigned UnsafeFPMath : 1;
94
95 /// NoInfsFPMath - This flag is enabled when the
96 /// -enable-no-infs-fp-math flag is specified on the command line. When
97 /// this flag is off (the default), the code generator is not allowed to
98 /// assume the FP arithmetic arguments and results are never +-Infs.
99 unsigned NoInfsFPMath : 1;
100
101 /// NoNaNsFPMath - This flag is enabled when the
102 /// -enable-no-nans-fp-math flag is specified on the command line. When
103 /// this flag is off (the default), the code generator is not allowed to
104 /// assume the FP arithmetic arguments and results are never NaNs.
105 unsigned NoNaNsFPMath : 1;
106
107 /// HonorSignDependentRoundingFPMath - This returns true when the
108 /// -enable-sign-dependent-rounding-fp-math is specified. If this returns
109 /// false (the default), the code generator is allowed to assume that the
110 /// rounding behavior is the default (round-to-zero for all floating point
111 /// to integer conversions, and round-to-nearest for all other arithmetic
112 /// truncations). If this is enabled (set to true), the code generator must
113 /// assume that the rounding mode may dynamically change.
114 unsigned HonorSignDependentRoundingFPMathOption : 1;
115 bool HonorSignDependentRoundingFPMath() const;
116
117 /// UseSoftFloat - This flag is enabled when the -soft-float flag is
118 /// specified on the command line. When this flag is on, the code generator
119 /// will generate libcalls to the software floating point library instead of
120 /// target FP instructions.
121 unsigned UseSoftFloat : 1;
122
123 /// NoZerosInBSS - By default some codegens place zero-initialized data to
124 /// .bss section. This flag disables such behaviour (necessary, e.g. for
125 /// crt*.o compiling).
126 unsigned NoZerosInBSS : 1;
127
128 /// JITExceptionHandling - This flag indicates that the JIT should emit
129 /// exception handling information.
130 unsigned JITExceptionHandling : 1;
131
132 /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit
133 /// debug information and notify a debugger about it.
134 unsigned JITEmitDebugInfo : 1;
135
136 /// JITEmitDebugInfoToDisk - This flag indicates that the JIT should write
137 /// the object files generated by the JITEmitDebugInfo flag to disk. This
138 /// flag is hidden and is only for debugging the debug info.
139 unsigned JITEmitDebugInfoToDisk : 1;
140
141 /// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
142 /// specified on the commandline. When the flag is on, participating targets
143 /// will perform tail call optimization on all calls which use the fastcc
144 /// calling convention and which satisfy certain target-independent
145 /// criteria (being at the end of a function, having the same return type
146 /// as their parent function, etc.), using an alternate ABI if necessary.
147 unsigned GuaranteedTailCallOpt : 1;
148
149 /// StackAlignmentOverride - Override default stack alignment for target.
150 unsigned StackAlignmentOverride;
151
152 /// RealignStack - This flag indicates whether the stack should be
153 /// automatically realigned, if needed.
154 unsigned RealignStack : 1;
155
156 /// DisableJumpTables - This flag indicates jump tables should not be
157 /// generated.
158 unsigned DisableJumpTables : 1;
159
160 /// EnableFastISel - This flag enables fast-path instruction selection
161 /// which trades away generated code quality in favor of reducing
162 /// compile time.
163 unsigned EnableFastISel : 1;
164
165 unsigned EnableSegmentedStacks : 1;
166
167 /// getTrapFunctionName - If this returns a non-empty string, this means
168 /// isel should lower Intrinsic::trap to a call to the specified function
169 /// name instead of an ISD::TRAP node.
170 std::string TrapFuncName;
171 StringRef getTrapFunctionName() const;
172
173 /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
174 /// on the command line. This setting may either be Default, Soft, or Hard.
175 /// Default selects the target's default behavior. Soft selects the ABI for
176 /// UseSoftFloat, but does not indicate that FP hardware may not be used.
177 /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
178 /// Hard presumes that the normal FP ABI is used.
179 FloatABI::ABIType FloatABIType;
180 };
163181 } // End llvm namespace
164182
165183 #endif
None //===-- Analysis.cpp - CodeGen LLVM IR Analysis Utilities --*- C++ ------*-===//
0 //===-- Analysis.cpp - CodeGen LLVM IR Analysis Utilities -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
148148 /// consideration of global floating-point math flags.
149149 ///
150150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
151 ISD::CondCode FPC, FOC;
152151 switch (Pred) {
153 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
154 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
155 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
156 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
157 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
158 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
159 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
160 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
161 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
162 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
163 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
164 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
165 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
166 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
167 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
168 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
169 default:
170 llvm_unreachable("Invalid FCmp predicate opcode!");
171 FOC = FPC = ISD::SETFALSE;
172 break;
173 }
174 if (NoNaNsFPMath)
175 return FOC;
176 else
177 return FPC;
152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE;
153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ;
154 case FCmpInst::FCMP_OGT: return ISD::SETOGT;
155 case FCmpInst::FCMP_OGE: return ISD::SETOGE;
156 case FCmpInst::FCMP_OLT: return ISD::SETOLT;
157 case FCmpInst::FCMP_OLE: return ISD::SETOLE;
158 case FCmpInst::FCMP_ONE: return ISD::SETONE;
159 case FCmpInst::FCMP_ORD: return ISD::SETO;
160 case FCmpInst::FCMP_UNO: return ISD::SETUO;
161 case FCmpInst::FCMP_UEQ: return ISD::SETUEQ;
162 case FCmpInst::FCMP_UGT: return ISD::SETUGT;
163 case FCmpInst::FCMP_UGE: return ISD::SETUGE;
164 case FCmpInst::FCMP_ULT: return ISD::SETULT;
165 case FCmpInst::FCMP_ULE: return ISD::SETULE;
166 case FCmpInst::FCMP_UNE: return ISD::SETUNE;
167 case FCmpInst::FCMP_TRUE: return ISD::SETTRUE;
168 default: break;
169 }
170 llvm_unreachable("Invalid FCmp predicate opcode!");
171 return ISD::SETFALSE;
172 }
173
174 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
175 switch (CC) {
176 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ;
177 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE;
178 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;
179 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE;
180 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT;
181 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
182 default: break;
183 }
184 return CC;
178185 }
179186
180187 /// getICmpCondCode - Return the ISD condition code corresponding to
220227 // longjmp on x86), it can end up causing miscompilation that has not
221228 // been fully understood.
222229 if (!Ret &&
223 (!GuaranteedTailCallOpt || !isa(Term))) return false;
230 (!TLI.getTargetMachine().Options.GuaranteedTailCallOpt ||
231 !isa(Term))) return false;
224232
225233 // If I will have a chain, make sure no other instruction that will have a
226234 // chain interposes between I and the return.
14131413
14141414 DIE *CurFnDIE = constructScopeDIE(TheCU, FnScope);
14151415
1416 if (!DisableFramePointerElim(*MF))
1416 if (!MF->getTarget().Options.DisableFramePointerElim(*MF))
14171417 TheCU->addUInt(CurFnDIE, dwarf::DW_AT_APPLE_omit_frame_ptr,
14181418 dwarf::DW_FORM_flag, 1);
14191419
3939 #include "llvm/Support/FormattedStream.h"
4040 #include "llvm/Support/TargetRegistry.h"
4141 using namespace llvm;
42
43 namespace llvm {
44 bool EnableFastISel;
45 }
4642
4743 static cl::opt DisablePostRA("disable-post-ra", cl::Hidden,
4844 cl::desc("Disable Post Regalloc"));
113109
114110 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
115111 StringRef CPU, StringRef FS,
112 TargetOptions Options,
116113 Reloc::Model RM, CodeModel::Model CM,
117114 CodeGenOpt::Level OL)
118 : TargetMachine(T, Triple, CPU, FS) {
115 : TargetMachine(T, Triple, CPU, FS, Options) {
119116 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
120117 AsmInfo = T.createMCAsmInfo(Triple);
121118 // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
274271 return false; // success!
275272 }
276273
277 static void printNoVerify(PassManagerBase &PM, const char *Banner) {
278 if (PrintMachineCode)
274 void LLVMTargetMachine::printNoVerify(PassManagerBase &PM,
275 const char *Banner) const {
276 if (Options.PrintMachineCode)
279277 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
280278 }
281279
282 static void printAndVerify(PassManagerBase &PM,
283 const char *Banner) {
284 if (PrintMachineCode)
280 void LLVMTargetMachine::printAndVerify(PassManagerBase &PM,
281 const char *Banner) const {
282 if (Options.PrintMachineCode)
285283 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
286284
287285 if (VerifyMachineCode)
379377 if (EnableFastISelOption == cl::BOU_TRUE ||
380378 (getOptLevel() == CodeGenOpt::None &&
381379 EnableFastISelOption != cl::BOU_FALSE))
382 EnableFastISel = true;
380 Options.EnableFastISel = true;
383381
384382 // Ask the target for an isel.
385383 if (addInstSelector(PM))
705705 // we've been asked for it. This, when linked with a runtime with support
706706 // for segmented stacks (libgcc is one), will result in allocating stack
707707 // space in small chunks instead of one large contiguous block.
708 if (EnableSegmentedStacks)
708 if (Fn.getTarget().Options.EnableSegmentedStacks)
709709 TFI.adjustForSegmentedStacks(Fn);
710710 }
711711
360360 /// specified expression for the same cost as the expression itself, or 2 if we
361361 /// can compute the negated form more cheaply than the expression itself.
362362 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
363 const TargetOptions *Options,
363364 unsigned Depth = 0) {
364365 // No compile time optimizations on this type.
365366 if (Op.getValueType() == MVT::ppcf128)
382383 return LegalOperations ? 0 : 1;
383384 case ISD::FADD:
384385 // FIXME: determine better conditions for this xform.
385 if (!UnsafeFPMath) return 0;
386 if (!Options->UnsafeFPMath) return 0;
386387
387388 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
388 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
389 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
390 Depth + 1))
389391 return V;
390392 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
391 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
394 Depth + 1);
392395 case ISD::FSUB:
393396 // We can't turn -(A-B) into B-A when we honor signed zeros.
394 if (!UnsafeFPMath) return 0;
397 if (!Options->UnsafeFPMath) return 0;
395398
396399 // fold (fneg (fsub A, B)) -> (fsub B, A)
397400 return 1;
398401
399402 case ISD::FMUL:
400403 case ISD::FDIV:
401 if (HonorSignDependentRoundingFPMath()) return 0;
404 if (Options->HonorSignDependentRoundingFPMath()) return 0;
402405
403406 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
404 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
407 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
408 Depth + 1))
405409 return V;
406410
407 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
411 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
412 Depth + 1);
408413
409414 case ISD::FP_EXTEND:
410415 case ISD::FP_ROUND:
411416 case ISD::FSIN:
412 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
417 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
418 Depth + 1);
413419 }
414420 }
415421
433439 }
434440 case ISD::FADD:
435441 // FIXME: determine better conditions for this xform.
436 assert(UnsafeFPMath);
442 assert(DAG.getTarget().Options.UnsafeFPMath);
437443
438444 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
439 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
445 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
446 &DAG.getTarget().Options, Depth+1))
440447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
441448 GetNegatedExpression(Op.getOperand(0), DAG,
442449 LegalOperations, Depth+1),
448455 Op.getOperand(0));
449456 case ISD::FSUB:
450457 // We can't turn -(A-B) into B-A when we honor signed zeros.
451 assert(UnsafeFPMath);
458 assert(DAG.getTarget().Options.UnsafeFPMath);
452459
453460 // fold (fneg (fsub 0, B)) -> B
454461 if (ConstantFPSDNode *N0CFP = dyn_cast(Op.getOperand(0)))
461468
462469 case ISD::FMUL:
463470 case ISD::FDIV:
464 assert(!HonorSignDependentRoundingFPMath());
471 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
465472
466473 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
467 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
474 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
475 &DAG.getTarget().Options, Depth+1))
468476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
469477 GetNegatedExpression(Op.getOperand(0), DAG,
470478 LegalOperations, Depth+1),
52535261 if (N0CFP && !N1CFP)
52545262 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
52555263 // fold (fadd A, 0) -> A
5256 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5264 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5265 N1CFP->getValueAPF().isZero())
52575266 return N0;
52585267 // fold (fadd A, (fneg B)) -> (fsub A, B)
5259 if (isNegatibleForFree(N1, LegalOperations) == 2)
5268 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options) == 2)
52605269 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
52615270 GetNegatedExpression(N1, DAG, LegalOperations));
52625271 // fold (fadd (fneg A), B) -> (fsub B, A)
5263 if (isNegatibleForFree(N0, LegalOperations) == 2)
5272 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options) == 2)
52645273 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
52655274 GetNegatedExpression(N0, DAG, LegalOperations));
52665275
52675276 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5268 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5269 N0.getNode()->hasOneUse() && isa(N0.getOperand(1)))
5277 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5278 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5279 isa(N0.getOperand(1)))
52705280 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
52715281 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
52725282 N0.getOperand(1), N1));
52915301 if (N0CFP && N1CFP && VT != MVT::ppcf128)
52925302 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
52935303 // fold (fsub A, 0) -> A
5294 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5304 if (DAG.getTarget().Options.UnsafeFPMath &&
5305 N1CFP && N1CFP->getValueAPF().isZero())
52955306 return N0;
52965307 // fold (fsub 0, B) -> -B
5297 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5298 if (isNegatibleForFree(N1, LegalOperations))
5308 if (DAG.getTarget().Options.UnsafeFPMath &&
5309 N0CFP && N0CFP->getValueAPF().isZero()) {
5310 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
52995311 return GetNegatedExpression(N1, DAG, LegalOperations);
53005312 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
53015313 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
53025314 }
53035315 // fold (fsub A, (fneg B)) -> (fadd A, B)
5304 if (isNegatibleForFree(N1, LegalOperations))
5316 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
53055317 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
53065318 GetNegatedExpression(N1, DAG, LegalOperations));
53075319
53285340 if (N0CFP && !N1CFP)
53295341 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
53305342 // fold (fmul A, 0) -> 0
5331 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5343 if (DAG.getTarget().Options.UnsafeFPMath &&
5344 N1CFP && N1CFP->getValueAPF().isZero())
53325345 return N1;
53335346 // fold (fmul A, 0) -> 0, vector edition.
5334 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5347 if (DAG.getTarget().Options.UnsafeFPMath &&
5348 ISD::isBuildVectorAllZeros(N1.getNode()))
53355349 return N1;
53365350 // fold (fmul X, 2.0) -> (fadd X, X)
53375351 if (N1CFP && N1CFP->isExactlyValue(+2.0))
53425356 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
53435357
53445358 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5345 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5346 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5359 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5360 &DAG.getTarget().Options)) {
5361 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5362 &DAG.getTarget().Options)) {
53475363 // Both can be negated for free, check to see if at least one is cheaper
53485364 // negated.
53495365 if (LHSNeg == 2 || RHSNeg == 2)
53545370 }
53555371
53565372 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5357 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5373 if (DAG.getTarget().Options.UnsafeFPMath &&
5374 N1CFP && N0.getOpcode() == ISD::FMUL &&
53585375 N0.getNode()->hasOneUse() && isa(N0.getOperand(1)))
53595376 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
53605377 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
53825399
53835400
53845401 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5385 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5386 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5402 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5403 &DAG.getTarget().Options)) {
5404 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5405 &DAG.getTarget().Options)) {
53875406 // Both can be negated for free, check to see if at least one is cheaper
53885407 // negated.
53895408 if (LHSNeg == 2 || RHSNeg == 2)
56365655 SDValue N0 = N->getOperand(0);
56375656 EVT VT = N->getValueType(0);
56385657
5639 if (isNegatibleForFree(N0, LegalOperations))
5658 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options))
56405659 return GetNegatedExpression(N0, DAG, LegalOperations);
56415660
56425661 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
23332333
23342334 bool SelectionDAG::isKnownNeverNaN(SDValue Op) const {
23352335 // If we're told that NaNs won't happen, assume they won't.
2336 if (NoNaNsFPMath)
2336 if (getTarget().Options.NoNaNsFPMath)
23372337 return true;
23382338
23392339 // If the value is a constant, we can obviously see if it is a NaN or not.
26062606 break;
26072607 case ISD::FNEG:
26082608 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
2609 if (UnsafeFPMath && OpOpcode == ISD::FSUB)
2609 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
26102610 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
26112611 Operand.getNode()->getOperand(0));
26122612 if (OpOpcode == ISD::FNEG) // --X -> X
27412741 case ISD::FMUL:
27422742 case ISD::FDIV:
27432743 case ISD::FREM:
2744 if (UnsafeFPMath) {
2744 if (getTarget().Options.UnsafeFPMath) {
27452745 if (Opcode == ISD::FADD) {
27462746 // 0+x --> x
27472747 if (ConstantFPSDNode *CFP = dyn_cast(N1))
30643064 case ISD::FMUL:
30653065 case ISD::FDIV:
30663066 case ISD::FREM:
3067 if (UnsafeFPMath)
3067 if (getTarget().Options.UnsafeFPMath)
30683068 return N2;
30693069 break;
30703070 case ISD::MUL:
13341334 Condition = getICmpCondCode(IC->getPredicate());
13351335 } else if (const FCmpInst *FC = dyn_cast(Cond)) {
13361336 Condition = getFCmpCondCode(FC->getPredicate());
1337 if (TM.Options.NoNaNsFPMath)
1338 Condition = getFCmpCodeWithoutNaN(Condition);
13371339 } else {
13381340 Condition = ISD::SETEQ; // silence warning.
13391341 llvm_unreachable("Unknown compare instruction");
20012003 }
20022004
20032005 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2004 return !DisableJumpTables &&
2006 return !TLI.getTargetMachine().Options.DisableJumpTables &&
20052007 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
20062008 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
20072009 }
26242626 SDValue Op1 = getValue(I.getOperand(0));
26252627 SDValue Op2 = getValue(I.getOperand(1));
26262628 ISD::CondCode Condition = getFCmpCondCode(predicate);
2629 if (TM.Options.NoNaNsFPMath)
2630 Condition = getFCmpCodeWithoutNaN(Condition);
26272631 EVT DestVT = TLI.getValueType(I.getType());
26282632 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
26292633 }
50585062 }
50595063
50605064 case Intrinsic::trap: {
5061 StringRef TrapFuncName = getTrapFunctionName();
5065 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
50625066 if (TrapFuncName.empty()) {
50635067 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
50645068 return 0;
52205224
52215225 // If there's a possibility that fast-isel has already selected some amount
52225226 // of the current basic block, don't emit a tail call.
5223 if (isTailCall && EnableFastISel)
5227 if (isTailCall && TM.Options.EnableFastISel)
52245228 isTailCall = false;
52255229
52265230 std::pair Result =
65106514 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
65116515 /// entry block, return true. This includes arguments used by switches, since
65126516 /// the switch may expand into multiple basic blocks.
6513 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6517 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
65146518 // With FastISel active, we may be splitting blocks, so force creation
65156519 // of virtual registers for all non-dead arguments.
6516 if (EnableFastISel)
6520 if (FastISel)
65176521 return A->use_empty();
65186522
65196523 const BasicBlock *Entry = A->getParent()->begin();
67036707 SDB->getCurDebugLoc());
67046708
67056709 SDB->setValue(I, Res);
6706 if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6710 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
67076711 if (LoadSDNode *LNode =
67086712 dyn_cast(Res.getOperand(0).getNode()))
67096713 if (FrameIndexSDNode *FI =
67136717
67146718 // If this argument is live outside of the entry block, insert a copy from
67156719 // wherever we got it to the vreg that other BB's will reference it as.
6716 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6720 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
67176721 // If we can, though, try to skip creating an unnecessary vreg.
67186722 // FIXME: This isn't very clean... it would be nice to make this more
67196723 // general. It's also subtly incompatible with the hacks FastISel
67246728 continue;
67256729 }
67266730 }
6727 if (!isOnlyUsedInEntryBlock(I)) {
6731 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
67286732 FuncInfo->InitializeRegForValue(I);
67296733 SDB->CopyToExportRegsIfNeeded(I);
67306734 }
255255
256256 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
257257 // Do some sanity-checking on the command-line options.
258 assert((!EnableFastISelVerbose || EnableFastISel) &&
258 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
259259 "-fast-isel-verbose requires -fast-isel");
260 assert((!EnableFastISelAbort || EnableFastISel) &&
260 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
261261 "-fast-isel-abort requires -fast-isel");
262262
263263 const Function &Fn = *mf.getFunction();
822822 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
823823 // Initialize the Fast-ISel state, if needed.
824824 FastISel *FastIS = 0;
825 if (EnableFastISel)
825 if (TM.Options.EnableFastISel)
826826 FastIS = TLI.createFastISel(*FuncInfo);
827827
828828 // Iterate over all basic blocks in the function.
114114 // When trying to debug why GDB isn't getting the debug info right, it's
115115 // awfully helpful to write the object file to disk so that it can be
116116 // inspected with readelf and objdump.
117 if (JITEmitDebugInfoToDisk) {
117 if (TM.Options.JITEmitDebugInfoToDisk) {
118118 std::string Filename;
119119 raw_string_ostream O2(Filename);
120120 O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getName() << ".o";
361361 /// Instance of the JIT
362362 JIT *TheJIT;
363363
364 bool JITExceptionHandling;
365
366 bool JITEmitDebugInfo;
367
364368 public:
365369 JITEmitter(JIT &jit, JITMemoryManager *JMM, TargetMachine &TM)
366370 : SizeEstimate(0), Resolver(jit, *this), MMI(0), CurFn(0),
367 EmittedFunctions(this), TheJIT(&jit) {
371 EmittedFunctions(this), TheJIT(&jit),
372 JITExceptionHandling(TM.Options.JITExceptionHandling),
373 JITEmitDebugInfo(TM.Options.JITEmitDebugInfo) {
368374 MemMgr = JMM ? JMM : JITMemoryManager::CreateDefaultMemManager();
369375 if (jit.getJITInfo().needsGOT()) {
370376 MemMgr->AllocateGOT();
10361042 EmittedFunctions.erase(Emitted);
10371043 }
10381044
1039 if(JITExceptionHandling) {
1045 if (JITExceptionHandling) {
10401046 TheJIT->DeregisterTable(F);
10411047 }
10421048
10461052 }
10471053
10481054
1049 void* JITEmitter::allocateSpace(uintptr_t Size, unsigned Alignment) {
1055 void *JITEmitter::allocateSpace(uintptr_t Size, unsigned Alignment) {
10501056 if (BufferBegin)
10511057 return JITCodeEmitter::allocateSpace(Size, Alignment);
10521058
10581064 return CurBufferPtr;
10591065 }
10601066
1061 void* JITEmitter::allocateGlobal(uintptr_t Size, unsigned Alignment) {
1067 void *JITEmitter::allocateGlobal(uintptr_t Size, unsigned Alignment) {
10621068 // Delegate this call through the memory manager.
10631069 return MemMgr->allocateGlobal(Size, Alignment);
10641070 }
8585 }
8686
8787 // Allocate a target...
88 TargetOptions Options;
8889 TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
8990 MCPU, FeaturesStr,
91 Options,
9092 RM, CM, OL);
9193 assert(Target && "Could not allocate target machine!");
9294 return Target;
738738 }
739739
740740 // Signal various FP modes.
741 if (!UnsafeFPMath) {
741 if (!TM.Options.UnsafeFPMath) {
742742 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
743743 ARMBuildAttrs::Allowed);
744744 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
745745 ARMBuildAttrs::Allowed);
746746 }
747747
748 if (NoInfsFPMath && NoNaNsFPMath)
748 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
749749 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
750750 ARMBuildAttrs::Allowed);
751751 else
758758 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
759759
760760 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
761 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
761 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
762762 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
763763 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
764764 }
19331933 RegisterAsmPrinter X(TheARMTarget);
19341934 RegisterAsmPrinter Y(TheThumbTarget);
19351935 }
1936
630630 // 1. Dynamic stack realignment is explicitly disabled,
631631 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
632632 // 3. There are VLAs in the function and the base pointer is disabled.
633 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
633 return (MF.getTarget().Options.RealignStack && !AFI->isThumb1OnlyFunction() &&
634634 (!MFI->hasVarSizedObjects() || EnableBasePointer));
635635 }
636636
648648 bool ARMBaseRegisterInfo::
649649 cannotEliminateFrame(const MachineFunction &MF) const {
650650 const MachineFrameInfo *MFI = MF.getFrameInfo();
651 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
651 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
652652 return true;
653653 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
654654 || needsStackRealignment(MF);
17151715 // Use target triple & subtarget features to do actual dispatch.
17161716 if (Subtarget->isAAPCS_ABI()) {
17171717 if (Subtarget->hasVFP2() &&
1718 FloatABIType == FloatABI::Hard)
1718 TM.Options.FloatABIType == FloatABI::Hard)
17191719 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
17201720 else
17211721 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
3636
3737 const MachineFrameInfo *MFI = MF.getFrameInfo();
3838 // Always eliminate non-leaf frame pointers.
39 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
39 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
40 MFI->hasCalls()) ||
4041 RegInfo->needsStackRealignment(MF) ||
4142 MFI->hasVarSizedObjects() ||
4243 MFI->isFrameAddressTaken());
431431 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
432432 else
433433 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
434 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
434 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
435 !Subtarget->isThumb1Only()) {
435436 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
436437 if (!Subtarget->isFPOnlySP())
437438 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
673674 }
674675 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
675676
676 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
677 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
678 !Subtarget->isThumb1Only()) {
677679 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
678680 // iff target supports vfp2.
679681 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
711713 setOperationAction(ISD::FCOS, MVT::f64, Expand);
712714 setOperationAction(ISD::FREM, MVT::f64, Expand);
713715 setOperationAction(ISD::FREM, MVT::f32, Expand);
714 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
716 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
717 !Subtarget->isThumb1Only()) {
715718 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
716719 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717720 }
722725 setOperationAction(ISD::FMA, MVT::f32, Expand);
723726
724727 // Various VFP goodness
725 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
728 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
726729 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
727730 if (Subtarget->hasVFP2()) {
728731 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
750753
751754 setStackPointerRegisterToSaveRestore(ARM::SP);
752755
753 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
756 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
757 !Subtarget->hasVFP2())
754758 setSchedulingPreference(Sched::RegPressure);
755759 else
756760 setSchedulingPreference(Sched::Hybrid);
10911095 if (!Subtarget->isAAPCS_ABI())
10921096 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
10931097 else if (Subtarget->hasVFP2() &&
1094 FloatABIType == FloatABI::Hard && !isVarArg)
1098 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1099 !isVarArg)
10951100 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
10961101 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
10971102 }
29502955
29512956 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
29522957
2953 if (UnsafeFPMath &&
2958 if (getTargetMachine().Options.UnsafeFPMath &&
29542959 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
29552960 CC == ISD::SETNE || CC == ISD::SETUNE)) {
29562961 SDValue Result = OptimizeVFPBrcond(Op, DAG);
79477952 // will return -0, so vmin can only be used for unsafe math or if one of
79487953 // the operands is known to be nonzero.
79497954 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7950 !UnsafeFPMath &&
7955 !DAG.getTarget().Options.UnsafeFPMath &&
79517956 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
79527957 break;
79537958 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
79697974 // will return +0, so vmax can only be used for unsafe math or if one of
79707975 // the operands is known to be nonzero.
79717976 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
7972 !UnsafeFPMath &&
7977 !DAG.getTarget().Options.UnsafeFPMath &&
79737978 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
79747979 break;
79757980 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
3737 ///
3838 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
3939 StringRef CPU, StringRef FS,
40 const TargetOptions &Options,
4041 Reloc::Model RM, CodeModel::Model CM,
4142 CodeGenOpt::Level OL)
42 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
43 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
4344 Subtarget(TT, CPU, FS),
4445 JITInfo(),
4546 InstrItins(Subtarget.getInstrItineraryData()) {
4647 // Default to soft float ABI
47 if (FloatABIType == FloatABI::Default)
48 FloatABIType = FloatABI::Soft;
48 if (Options.FloatABIType == FloatABI::Default)
49 this->Options.FloatABIType = FloatABI::Soft;
4950 }
5051
5152 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
5253 StringRef CPU, StringRef FS,
54 const TargetOptions &Options,
5355 Reloc::Model RM, CodeModel::Model CM,
5456 CodeGenOpt::Level OL)
55 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), InstrInfo(Subtarget),
57 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
58 InstrInfo(Subtarget),
5659 DataLayout(Subtarget.isAPCS_ABI() ?
5760 std::string("e-p:32:32-f64:32:64-i64:32:64-"
5861 "v128:32:128-v64:32:64-n32-S32") :
7275
7376 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
7477 StringRef CPU, StringRef FS,
78 const TargetOptions &Options,
7579 Reloc::Model RM, CodeModel::Model CM,
7680 CodeGenOpt::Level OL)
77 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL),
81 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
7882 InstrInfo(Subtarget.hasThumb2()
7983 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
8084 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
4040 public:
4141 ARMBaseTargetMachine(const Target &T, StringRef TT,
4242 StringRef CPU, StringRef FS,
43 const TargetOptions &Options,
4344 Reloc::Model RM, CodeModel::Model CM,
4445 CodeGenOpt::Level OL);
4546
7071 public:
7172 ARMTargetMachine(const Target &T, StringRef TT,
7273 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
7375 Reloc::Model RM, CodeModel::Model CM,
7476 CodeGenOpt::Level OL);
7577
111113 public:
112114 ThumbTargetMachine(const Target &T, StringRef TT,
113115 StringRef CPU, StringRef FS,
116 const TargetOptions &Options,
114117 Reloc::Model RM, CodeModel::Model CM,
115118 CodeGenOpt::Level OL);
116119
2020
2121 struct CTargetMachine : public TargetMachine {
2222 CTargetMachine(const Target &T, StringRef TT,
23 StringRef CPU, StringRef FS,
23 StringRef CPU, StringRef FS, const TargetOptions &Options,
2424 Reloc::Model RM, CodeModel::Model CM,
2525 CodeGenOpt::Level OL)
26 : TargetMachine(T, TT, CPU, FS) {}
26 : TargetMachine(T, TT, CPU, FS, Options) { }
2727
2828 virtual bool addPassesToEmitFile(PassManagerBase &PM,
2929 formatted_raw_ostream &Out,
4646 const MachineFrameInfo *MFI = MF.getFrameInfo();
4747
4848 return MFI->getStackSize() &&
49 (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects());
49 (MF.getTarget().Options.DisableFramePointerElim(MF) ||
50 MFI->hasVarSizedObjects());
5051 }
5152
5253
3333
3434 SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
3535 StringRef CPU, StringRef FS,
36 const TargetOptions &Options,
3637 Reloc::Model RM, CodeModel::Model CM,
3738 CodeGenOpt::Level OL)
38 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
3940 Subtarget(TT, CPU, FS),
4041 DataLayout(Subtarget.getTargetDataString()),
4142 InstrInfo(*this),
3838 InstrItineraryData InstrItins;
3939 public:
4040 SPUTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
41 StringRef CPU, StringRef FS, const TargetOptions &Options,
4242 Reloc::Model RM, CodeModel::Model CM,
4343 CodeGenOpt::Level OL);
4444
2222
2323 struct CPPTargetMachine : public TargetMachine {
2424 CPPTargetMachine(const Target &T, StringRef TT,
25 StringRef CPU, StringRef FS,
25 StringRef CPU, StringRef FS, const TargetOptions &Options,
2626 Reloc::Model RM, CodeModel::Model CM,
2727 CodeGenOpt::Level OL)
28 : TargetMachine(T, TT, CPU, FS) {}
28 : TargetMachine(T, TT, CPU, FS, Options) {}
2929
3030 virtual bool addPassesToEmitFile(PassManagerBase &PM,
3131 formatted_raw_ostream &Out,
333333 // if frame pointer elimination is disabled.
334334 bool MBlazeFrameLowering::hasFP(const MachineFunction &MF) const {
335335 const MachineFrameInfo *MFI = MF.getFrameInfo();
336 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
336 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
337 MFI->hasVarSizedObjects();
337338 }
338339
339340 void MBlazeFrameLowering::emitPrologue(MachineFunction &MF) const {
3232 // an easier handling.
3333 MBlazeTargetMachine::
3434 MBlazeTargetMachine(const Target &T, StringRef TT,
35 StringRef CPU, StringRef FS,
35 StringRef CPU, StringRef FS, const TargetOptions &Options,
3636 Reloc::Model RM, CodeModel::Model CM,
37 CodeGenOpt::Level OL):
38 LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
39 Subtarget(TT, CPU, FS),
40 DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
41 InstrInfo(*this),
42 FrameLowering(Subtarget),
43 TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
44 InstrItins(Subtarget.getInstrItineraryData()) {
37 CodeGenOpt::Level OL)
38 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
39 Subtarget(TT, CPU, FS),
40 DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
41 InstrInfo(*this),
42 FrameLowering(Subtarget),
43 TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
44 InstrItins(Subtarget.getInstrItineraryData()) {
4545 }
4646
4747 // Install an instruction selector pass using
4242 public:
4343 MBlazeTargetMachine(const Target &T, StringRef TT,
4444 StringRef CPU, StringRef FS,
45 const TargetOptions &Options,
4546 Reloc::Model RM, CodeModel::Model CM,
4647 CodeGenOpt::Level OL);
4748
2828 bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const {
2929 const MachineFrameInfo *MFI = MF.getFrameInfo();
3030
31 return (DisableFramePointerElim(MF) ||
31 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
3232 MF.getFrameInfo()->hasVarSizedObjects() ||
3333 MFI->isFrameAddressTaken());
3434 }
2727 StringRef TT,
2828 StringRef CPU,
2929 StringRef FS,
30 const TargetOptions &Options,
3031 Reloc::Model RM, CodeModel::Model CM,
3132 CodeGenOpt::Level OL)
32 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
33 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
3334 Subtarget(TT, CPU, FS),
3435 // FIXME: Check TargetData string.
3536 DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
3838
3939 public:
4040 MSP430TargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
41 StringRef CPU, StringRef FS, const TargetOptions &Options,
4242 Reloc::Model RM, CodeModel::Model CM,
4343 CodeGenOpt::Level OL);
4444
8484 // if frame pointer elimination is disabled.
8585 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
8686 const MachineFrameInfo *MFI = MF.getFrameInfo();
87 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()
88 || MFI->isFrameAddressTaken();
87 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
88 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
8989 }
9090
9191 bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
3333 // Using CodeModel::Large enables different CALL behavior.
3434 MipsTargetMachine::
3535 MipsTargetMachine(const Target &T, StringRef TT,
36 StringRef CPU, StringRef FS,
36 StringRef CPU, StringRef FS, const TargetOptions &Options,
3737 Reloc::Model RM, CodeModel::Model CM,
3838 CodeGenOpt::Level OL,
39 bool isLittle):
40 LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
41 Subtarget(TT, CPU, FS, isLittle),
42 DataLayout(isLittle ?
43 (Subtarget.isABI_N64() ?
44 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
45 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
46 (Subtarget.isABI_N64() ?
47 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
48 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
49 InstrInfo(*this),
50 FrameLowering(Subtarget),
51 TLInfo(*this), TSInfo(*this), JITInfo() {
39 bool isLittle)
40 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
41 Subtarget(TT, CPU, FS, isLittle),
42 DataLayout(isLittle ?
43 (Subtarget.isABI_N64() ?
44 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
45 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
46 (Subtarget.isABI_N64() ?
47 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
48 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
49 InstrInfo(*this),
50 FrameLowering(Subtarget),
51 TLInfo(*this), TSInfo(*this), JITInfo() {
5252 }
5353
5454 MipsebTargetMachine::
5555 MipsebTargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
56 StringRef CPU, StringRef FS, const TargetOptions &Options,
5757 Reloc::Model RM, CodeModel::Model CM,
58 CodeGenOpt::Level OL) :
59 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
58 CodeGenOpt::Level OL)
59 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
6060
6161 MipselTargetMachine::
6262 MipselTargetMachine(const Target &T, StringRef TT,
63 StringRef CPU, StringRef FS,
63 StringRef CPU, StringRef FS, const TargetOptions &Options,
6464 Reloc::Model RM, CodeModel::Model CM,
65 CodeGenOpt::Level OL) :
66 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
65 CodeGenOpt::Level OL)
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
6767
6868 Mips64ebTargetMachine::
6969 Mips64ebTargetMachine(const Target &T, StringRef TT,
70 StringRef CPU, StringRef FS,
70 StringRef CPU, StringRef FS, const TargetOptions &Options,
7171 Reloc::Model RM, CodeModel::Model CM,
72 CodeGenOpt::Level OL) :
73 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
72 CodeGenOpt::Level OL)
73 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
7474
7575 Mips64elTargetMachine::
7676 Mips64elTargetMachine(const Target &T, StringRef TT,
77 StringRef CPU, StringRef FS,
77 StringRef CPU, StringRef FS, const TargetOptions &Options,
7878 Reloc::Model RM, CodeModel::Model CM,
79 CodeGenOpt::Level OL) :
80 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
79 CodeGenOpt::Level OL)
80 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
8181
8282 // Install an instruction selector pass using
8383 // the ISelDag to gen Mips code.
119119 PM.add(createMipsJITCodeEmitterPass(*this, JCE));
120120 return false;
121121 }
122
3737
3838 public:
3939 MipsTargetMachine(const Target &T, StringRef TT,
40 StringRef CPU, StringRef FS,
40 StringRef CPU, StringRef FS, const TargetOptions &Options,
4141 Reloc::Model RM, CodeModel::Model CM,
4242 CodeGenOpt::Level OL,
4343 bool isLittle);
8181 class MipsebTargetMachine : public MipsTargetMachine {
8282 public:
8383 MipsebTargetMachine(const Target &T, StringRef TT,
84 StringRef CPU, StringRef FS,
84 StringRef CPU, StringRef FS, const TargetOptions &Options,
8585 Reloc::Model RM, CodeModel::Model CM,
8686 CodeGenOpt::Level OL);
8787 };
9191 class MipselTargetMachine : public MipsTargetMachine {
9292 public:
9393 MipselTargetMachine(const Target &T, StringRef TT,
94 StringRef CPU, StringRef FS,
94 StringRef CPU, StringRef FS, const TargetOptions &Options,
9595 Reloc::Model RM, CodeModel::Model CM,
9696 CodeGenOpt::Level OL);
9797 };
102102 public:
103103 Mips64ebTargetMachine(const Target &T, StringRef TT,
104104 StringRef CPU, StringRef FS,
105 const TargetOptions &Options,
105106 Reloc::Model RM, CodeModel::Model CM,
106107 CodeGenOpt::Level OL);
107108 };
112113 public:
113114 Mips64elTargetMachine(const Target &T, StringRef TT,
114115 StringRef CPU, StringRef FS,
116 const TargetOptions &Options,
115117 Reloc::Model RM, CodeModel::Model CM,
116118 CodeGenOpt::Level OL);
117119 };
6666 "e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
6767 const char* DataLayout64 =
6868 "e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
69
70 // Copied from LLVMTargetMachine.cpp
71 void printNoVerify(PassManagerBase &PM, const char *Banner) {
72 if (PrintMachineCode)
73 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
74 }
75
76 void printAndVerify(PassManagerBase &PM,
77 const char *Banner) {
78 if (PrintMachineCode)
79 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
80
81 //if (VerifyMachineCode)
82 // PM.add(createMachineVerifierPass(Banner));
83 }
8469 }
8570
8671 // DataLayout and FrameLowering are filled with dummy data
8772 PTXTargetMachine::PTXTargetMachine(const Target &T,
8873 StringRef TT, StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
8975 Reloc::Model RM, CodeModel::Model CM,
9076 CodeGenOpt::Level OL,
9177 bool is64Bit)
92 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
9379 DataLayout(is64Bit ? DataLayout64 : DataLayout32),
9480 Subtarget(TT, CPU, FS, is64Bit),
9581 FrameLowering(Subtarget),
10086
10187 PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
10288 StringRef CPU, StringRef FS,
89 const TargetOptions &Options,
10390 Reloc::Model RM, CodeModel::Model CM,
10491 CodeGenOpt::Level OL)
105 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
92 : PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
10693 }
10794
10895 PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
10996 StringRef CPU, StringRef FS,
97 const TargetOptions &Options,
11098 Reloc::Model RM, CodeModel::Model CM,
11199 CodeGenOpt::Level OL)
112 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
100 : PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
113101 }
114102
115103 bool PTXTargetMachine::addInstSelector(PassManagerBase &PM) {
3434
3535 public:
3636 PTXTargetMachine(const Target &T, StringRef TT,
37 StringRef CPU, StringRef FS,
37 StringRef CPU, StringRef FS, const TargetOptions &Options,
3838 Reloc::Model RM, CodeModel::Model CM,
3939 CodeGenOpt::Level OL,
4040 bool is64Bit);
9393 public:
9494
9595 PTX32TargetMachine(const Target &T, StringRef TT,
96 StringRef CPU, StringRef FS,
96 StringRef CPU, StringRef FS, const TargetOptions &Options,
9797 Reloc::Model RM, CodeModel::Model CM,
9898 CodeGenOpt::Level OL);
9999 }; // class PTX32TargetMachine
102102 public:
103103
104104 PTX64TargetMachine(const Target &T, StringRef TT,
105 StringRef CPU, StringRef FS,
105 StringRef CPU, StringRef FS, const TargetOptions &Options,
106106 Reloc::Model RM, CodeModel::Model CM,
107107 CodeGenOpt::Level OL);
108108 }; // class PTX32TargetMachine
243243 if (MF.getFunction()->hasFnAttr(Attribute::Naked))
244244 return false;
245245
246 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
247 (GuaranteedTailCallOpt && MF.getInfo()->hasFastCall());
246 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
247 MFI->hasVarSizedObjects() ||
248 (MF.getTarget().Options.GuaranteedTailCallOpt &&
249 MF.getInfo()->hasFastCall());
248250 }
249251
250252
654656
655657 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
656658 // call optimization
657 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
659 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
658660 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
659661 PPCFunctionInfo *FI = MF.getInfo();
660662 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
757759
758760 // Reserve stack space to move the linkage area to in case of a tail call.
759761 int TCSPDelta = 0;
760 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
762 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
763 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
761764 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
762765 }
763766
862865
863866 // Take into account stack space reserved for tail calls.
864867 int TCSPDelta = 0;
865 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
868 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
869 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
866870 LowerBound = TCSPDelta;
867871 }
868872
16661666
16671667 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
16681668 // Potential tail calls could cause overwriting of argument stack slots.
1669 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1669 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1670 (CallConv == CallingConv::Fast));
16701671 unsigned PtrByteSize = 4;
16711672
16721673 // Assign locations to all of the incoming arguments.
18561857 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
18571858 bool isPPC64 = PtrVT == MVT::i64;
18581859 // Potential tail calls could cause overwriting of argument stack slots.
1859 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1860 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1861 (CallConv == CallingConv::Fast));
18601862 unsigned PtrByteSize = isPPC64 ? 8 : 4;
18611863
18621864 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
22622264 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
22632265
22642266 // Tail call needs the stack to be aligned.
2265 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2266 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2267 getStackAlignment();
2267 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2268 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2269 getFrameLowering()->getStackAlignment();
22682270 unsigned AlignMask = TargetAlign-1;
22692271 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
22702272 }
22982300 bool isVarArg,
22992301 const SmallVectorImpl &Ins,
23002302 SelectionDAG& DAG) const {
2301 if (!GuaranteedTailCallOpt)
2303 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
23022304 return false;
23032305
23042306 // Variable argument functions are not supported.
27512753 // the stack. Account for this here so these bytes can be pushed back on in
27522754 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
27532755 int BytesCalleePops =
2754 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2756 (CallConv == CallingConv::Fast &&
2757 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
27552758
27562759 if (InFlag.getNode())
27572760 Ops.push_back(InFlag);
28672870 // and restoring the callers stack pointer in this functions epilog. This is
28682871 // done because by tail calling the called function might overwrite the value
28692872 // in this function's (MF) stack pointer stack slot 0(SP).
2870 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2873 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2874 CallConv == CallingConv::Fast)
28712875 MF.getInfo()->setHasFastCall();
28722876
28732877 // Count how many bytes are to be pushed on the stack, including the linkage
30743078 // and restoring the callers stack pointer in this functions epilog. This is
30753079 // done because by tail calling the called function might overwrite the value
30763080 // in this function's (MF) stack pointer stack slot 0(SP).
3077 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
3081 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3082 CallConv == CallingConv::Fast)
30783083 MF.getInfo()->setHasFastCall();
30793084
30803085 unsigned nAltivecParamsAtEnd = 0;
57535758 MachineFunction &MF = DAG.getMachineFunction();
57545759 MachineFrameInfo *MFI = MF.getFrameInfo();
57555760 MFI->setFrameAddressIsTaken(true);
5756 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5761 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
5762 MFI->hasVarSizedObjects()) &&
57575763 MFI->getStackSize() &&
57585764 !MF.getFunction()->hasFnAttr(Attribute::Naked);
57595765 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
348348
349349 //===----------------------------------------------------------------------===//
350350 // PowerPC Instruction Predicate Definitions.
351 def FPContractions : Predicate<"!NoExcessFPPrecision">;
351 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
352352 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
353353 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
354354 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
300300 void PPCRegisterInfo::
301301 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
302302 MachineBasicBlock::iterator I) const {
303 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
303 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
304 I->getOpcode() == PPC::ADJCALLSTACKUP) {
304305 // Add (actually subtract) back the amount the callee popped on return.
305306 if (int CalleeAmt = I->getOperand(1).getImm()) {
306307 bool is64Bit = Subtarget.isPPC64();
2727
2828 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
2929 StringRef CPU, StringRef FS,
30 const TargetOptions &Options,
3031 Reloc::Model RM, CodeModel::Model CM,
3132 CodeGenOpt::Level OL,
3233 bool is64Bit)
33 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
3435 Subtarget(TT, CPU, FS, is64Bit),
3536 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
3637 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
4445
4546 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
4647 StringRef CPU, StringRef FS,
48 const TargetOptions &Options,
4749 Reloc::Model RM, CodeModel::Model CM,
4850 CodeGenOpt::Level OL)
49 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
51 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
5052 }
5153
5254
5355 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
5456 StringRef CPU, StringRef FS,
57 const TargetOptions &Options,
5558 Reloc::Model RM, CodeModel::Model CM,
5659 CodeGenOpt::Level OL)
57 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
5861 }
5962
6063
8083 if (Subtarget.isPPC64())
8184 // Temporary workaround for the inability of PPC64 JIT to handle jump
8285 // tables.
83 DisableJumpTables = true;
86 Options.DisableJumpTables = true;
8487
8588 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
8689 // writing?
4040
4141 public:
4242 PPCTargetMachine(const Target &T, StringRef TT,
43 StringRef CPU, StringRef FS,
43 StringRef CPU, StringRef FS, const TargetOptions &Options,
4444 Reloc::Model RM, CodeModel::Model CM,
4545 CodeGenOpt::Level OL, bool is64Bit);
4646
7878 class PPC32TargetMachine : public PPCTargetMachine {
7979 public:
8080 PPC32TargetMachine(const Target &T, StringRef TT,
81 StringRef CPU, StringRef FS,
81 StringRef CPU, StringRef FS, const TargetOptions &Options,
8282 Reloc::Model RM, CodeModel::Model CM,
8383 CodeGenOpt::Level OL);
8484 };
8888 class PPC64TargetMachine : public PPCTargetMachine {
8989 public:
9090 PPC64TargetMachine(const Target &T, StringRef TT,
91 StringRef CPU, StringRef FS,
91 StringRef CPU, StringRef FS, const TargetOptions &Options,
9292 Reloc::Model RM, CodeModel::Model CM,
9393 CodeGenOpt::Level OL);
9494 };
2525 ///
2626 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
2727 StringRef CPU, StringRef FS,
28 const TargetOptions &Options,
2829 Reloc::Model RM, CodeModel::Model CM,
2930 CodeGenOpt::Level OL,
3031 bool is64bit)
31 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
32 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
3233 Subtarget(TT, CPU, FS, is64bit),
3334 DataLayout(Subtarget.getDataLayout()),
3435 TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
5152
5253 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
5354 StringRef TT, StringRef CPU,
54 StringRef FS, Reloc::Model RM,
55 StringRef FS,
56 const TargetOptions &Options,
57 Reloc::Model RM,
5558 CodeModel::Model CM,
5659 CodeGenOpt::Level OL)
57 : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
60 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
5861 }
5962
6063 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
6164 StringRef TT, StringRef CPU,
62 StringRef FS, Reloc::Model RM,
65 StringRef FS,
66 const TargetOptions &Options,
67 Reloc::Model RM,
6368 CodeModel::Model CM,
6469 CodeGenOpt::Level OL)
65 : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
70 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
6671 }
3333 SparcFrameLowering FrameLowering;
3434 public:
3535 SparcTargetMachine(const Target &T, StringRef TT,
36 StringRef CPU, StringRef FS,
36 StringRef CPU, StringRef FS, const TargetOptions &Options,
3737 Reloc::Model RM, CodeModel::Model CM,
38 CodeGenOpt::Level OL, bool is64bit);
38 CodeGenOpt::Level OL, bool is64bit);
3939
4040 virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
4141 virtual const TargetFrameLowering *getFrameLowering() const {
6464 public:
6565 SparcV8TargetMachine(const Target &T, StringRef TT,
6666 StringRef CPU, StringRef FS,
67 const TargetOptions &Options,
6768 Reloc::Model RM, CodeModel::Model CM,
6869 CodeGenOpt::Level OL);
6970 };
7475 public:
7576 SparcV9TargetMachine(const Target &T, StringRef TT,
7677 StringRef CPU, StringRef FS,
78 const TargetOptions &Options,
7779 Reloc::Model RM, CodeModel::Model CM,
7880 CodeGenOpt::Level OL);
7981 };
4747 TargetLoweringObjectFile::~TargetLoweringObjectFile() {
4848 }
4949
50 static bool isSuitableForBSS(const GlobalVariable *GV) {
50 static bool isSuitableForBSS(const GlobalVariable *GV, bool NoZerosInBSS) {
5151 const Constant *C = GV->getInitializer();
5252
5353 // Must have zero initializer.
132132
133133 // Handle thread-local data first.
134134 if (GVar->isThreadLocal()) {
135 if (isSuitableForBSS(GVar))
135 if (isSuitableForBSS(GVar, TM.Options.NoZerosInBSS))
136136 return SectionKind::getThreadBSS();
137137 return SectionKind::getThreadData();
138138 }
142142 return SectionKind::getCommon();
143143
144144 // Variable can be easily put to BSS section.
145 if (isSuitableForBSS(GVar)) {
145 if (isSuitableForBSS(GVar, TM.Options.NoZerosInBSS)) {
146146 if (GVar->hasLocalLinkage())
147147 return SectionKind::getBSSLocal();
148148 else if (GVar->hasExternalLinkage())
2323 //
2424
2525 namespace llvm {
26 bool LessPreciseFPMADOption;
27 bool PrintMachineCode;
28 bool NoFramePointerElim;
29 bool NoFramePointerElimNonLeaf;
30 bool NoExcessFPPrecision;
31 bool UnsafeFPMath;
32 bool NoInfsFPMath;
33 bool NoNaNsFPMath;
34 bool HonorSignDependentRoundingFPMathOption;
35 bool UseSoftFloat;
36 FloatABI::ABIType FloatABIType;
37 bool NoImplicitFloat;
38 bool NoZerosInBSS;
39 bool JITExceptionHandling;
40 bool JITEmitDebugInfo;
41 bool JITEmitDebugInfoToDisk;
42 bool GuaranteedTailCallOpt;
43 unsigned StackAlignmentOverride;
44 bool RealignStack;
45 bool DisableJumpTables;
4626 bool StrongPHIElim;
4727 bool HasDivModLibcall;
4828 bool AsmVerbosityDefault(false);
49 bool EnableSegmentedStacks;
5029 }
5130
52 static cl::opt
53 PrintCode("print-machineinstrs",
54 cl::desc("Print generated machine code"),
55 cl::location(PrintMachineCode), cl::init(false));
56 static cl::opt
57 DisableFPElim("disable-fp-elim",
58 cl::desc("Disable frame pointer elimination optimization"),
59 cl::location(NoFramePointerElim),
60 cl::init(false));
61 static cl::opt
62 DisableFPElimNonLeaf("disable-non-leaf-fp-elim",
63 cl::desc("Disable frame pointer elimination optimization for non-leaf funcs"),
64 cl::location(NoFramePointerElimNonLeaf),
65 cl::init(false));
66 static cl::opt
67 DisableExcessPrecision("disable-excess-fp-precision",
68 cl::desc("Disable optimizations that may increase FP precision"),
69 cl::location(NoExcessFPPrecision),
70 cl::init(false));
71 static cl::opt
72 EnableFPMAD("enable-fp-mad",
73 cl::desc("Enable less precise MAD instructions to be generated"),
74 cl::location(LessPreciseFPMADOption),
75 cl::init(false));
76 static cl::opt
77 EnableUnsafeFPMath("enable-unsafe-fp-math",
78 cl::desc("Enable optimizations that may decrease FP precision"),
79 cl::location(UnsafeFPMath),
80 cl::init(false));
81 static cl::opt
82 EnableNoInfsFPMath("enable-no-infs-fp-math",
83 cl::desc("Enable FP math optimizations that assume no +-Infs"),
84 cl::location(NoInfsFPMath),
85 cl::init(false));
86 static cl::opt
87 EnableNoNaNsFPMath("enable-no-nans-fp-math",
88 cl::desc("Enable FP math optimizations that assume no NaNs"),
89 cl::location(NoNaNsFPMath),
90 cl::init(false));
91 static cl::opt
92 EnableHonorSignDependentRoundingFPMath("enable-sign-dependent-rounding-fp-math",
93 cl::Hidden,
94 cl::desc("Force codegen to assume rounding mode can change dynamically"),
95 cl::location(HonorSignDependentRoundingFPMathOption),
96 cl::init(false));
97 static cl::opt
98 GenerateSoftFloatCalls("soft-float",
99 cl::desc("Generate software floating point library calls"),
100 cl::location(UseSoftFloat),
101 cl::init(false));
102 static cl::opt
103 FloatABIForCalls("float-abi",
104 cl::desc("Choose float ABI type"),
105 cl::location(FloatABIType),
106 cl::init(FloatABI::Default),
107 cl::values(
108 clEnumValN(FloatABI::Default, "default",
109 "Target default float ABI type"),
110 clEnumValN(FloatABI::Soft, "soft",
111 "Soft float ABI (implied by -soft-float)"),
112 clEnumValN(FloatABI::Hard, "hard",
113 "Hard float ABI (uses FP registers)"),
114 clEnumValEnd));
115 static cl::opt
116 DontPlaceZerosInBSS("nozero-initialized-in-bss",
117 cl::desc("Don't place zero-initialized symbols into bss section"),
118 cl::location(NoZerosInBSS),
119 cl::init(false));
120 static cl::opt
121 EnableJITExceptionHandling("jit-enable-eh",
122 cl::desc("Emit exception handling information"),
123 cl::location(JITExceptionHandling),
124 cl::init(false));
125 // In debug builds, make this default to true.
126 #ifdef NDEBUG
127 #define EMIT_DEBUG false
128 #else
129 #define EMIT_DEBUG true
130 #endif
131 static cl::opt
132 EmitJitDebugInfo("jit-emit-debug",
133 cl::desc("Emit debug information to debugger"),
134 cl::location(JITEmitDebugInfo),
135 cl::init(EMIT_DEBUG));
136 #undef EMIT_DEBUG
137 static cl::opt
138 EmitJitDebugInfoToDisk("jit-emit-debug-to-disk",
139 cl::Hidden,
140 cl::desc("Emit debug info objfiles to disk"),
141 cl::location(JITEmitDebugInfoToDisk),
142 cl::init(false));
143
144 static cl::opt
145 EnableGuaranteedTailCallOpt("tailcallopt",
146 cl::desc("Turn fastcc calls into tail calls by (potentially) changing ABI."),
147 cl::location(GuaranteedTailCallOpt),
148 cl::init(false));
149 static cl::opt
150 OverrideStackAlignment("stack-alignment",
151 cl::desc("Override default stack alignment"),
152 cl::location(StackAlignmentOverride),
153 cl::init(0));
154 static cl::opt
155 EnableRealignStack("realign-stack",
156 cl::desc("Realign stack if needed"),
157 cl::location(RealignStack),
158 cl::init(true));
159 static cl::opt
160 DisableSwitchTables(cl::Hidden, "disable-jump-tables",
161 cl::desc("Do not generate jump tables."),
162 cl::location(DisableJumpTables),
163 cl::init(false));
164 static cl::opt
165 EnableStrongPHIElim(cl::Hidden, "strong-phi-elim",
166 cl::desc("Use strong PHI elimination."),
167 cl::location(StrongPHIElim),
168 cl::init(false));
169 static cl::opt
170 TrapFuncName("trap-func", cl::Hidden,
171 cl::desc("Emit a call to trap function rather than a trap instruction"),
172 cl::init(""));
17331 static cl::opt
17432 DataSections("fdata-sections",
17533 cl::desc("Emit data into separate sections"),
17836 FunctionSections("ffunction-sections",
17937 cl::desc("Emit functions into separate sections"),
18038 cl::init(false));
181 static cl::opt
182 SegmentedStacks("segmented-stacks",
183 cl::desc("Use segmented stacks if possible."),
184 cl::location(EnableSegmentedStacks),
185 cl::init(false));
18639
18740 //---------------------------------------------------------------------------
18841 // TargetMachine Class
18942 //
19043
19144 TargetMachine::TargetMachine(const Target &T,
192 StringRef TT, StringRef CPU, StringRef FS)
45 StringRef TT, StringRef CPU, StringRef FS,
46 const TargetOptions &Options)
19347 : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
19448 CodeGenInfo(0), AsmInfo(0),
19549 MCRelaxAll(false),
19751 MCSaveTempLabels(false),
19852 MCUseLoc(true),
19953 MCUseCFI(true),
200 MCUseDwarfDirectory(false) {
201 // Typically it will be subtargets that will adjust FloatABIType from Default
202 // to Soft or Hard.
203 if (UseSoftFloat)
204 FloatABIType = FloatABI::Soft;
54 MCUseDwarfDirectory(false),
55 Options(Options) {
20556 }
20657
20758 TargetMachine::~TargetMachine() {
257108 DataSections = V;
258109 }
259110
260 namespace llvm {
261 /// DisableFramePointerElim - This returns true if frame pointer elimination
262 /// optimization should be disabled for the given machine function.
263 bool DisableFramePointerElim(const MachineFunction &MF) {
264 // Check to see if we should eliminate non-leaf frame pointers and then
265 // check to see if we should eliminate all frame pointers.
266 if (NoFramePointerElimNonLeaf && !NoFramePointerElim) {
267 const MachineFrameInfo *MFI = MF.getFrameInfo();
268 return MFI->hasCalls();
269 }
270
271 return NoFramePointerElim;
111 /// DisableFramePointerElim - This returns true if frame pointer elimination
112 /// optimization should be disabled for the given machine function.
113 bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
114 // Check to see if we should eliminate non-leaf frame pointers and then
115 // check to see if we should eliminate all frame pointers.
116 if (NoFramePointerElimNonLeaf && !NoFramePointerElim) {
117 const MachineFrameInfo *MFI = MF.getFrameInfo();
118 return MFI->hasCalls();
272119 }
273120
274 /// LessPreciseFPMAD - This flag return true when -enable-fp-mad option
275 /// is specified on the command line. When this flag is off(default), the
276 /// code generator is not allowed to generate mad (multiply add) if the
277 /// result is "less precise" than doing those operations individually.
278 bool LessPreciseFPMAD() { return UnsafeFPMath || LessPreciseFPMADOption; }
121 return NoFramePointerElim;
122 }
279123
280 /// HonorSignDependentRoundingFPMath - Return true if the codegen must assume
281 /// that the rounding mode of the FPU can change from its default.
282 bool HonorSignDependentRoundingFPMath() {
283 return !UnsafeFPMath && HonorSignDependentRoundingFPMathOption;
284 }
124 /// LessPreciseFPMAD - This flag return true when -enable-fp-mad option
125 /// is specified on the command line. When this flag is off(default), the
126 /// code generator is not allowed to generate mad (multiply add) if the
127 /// result is "less precise" than doing those operations individually.
128 bool TargetOptions::LessPreciseFPMAD() const {
129 return UnsafeFPMath || LessPreciseFPMADOption;
130 }
285131
286 /// getTrapFunctionName - If this returns a non-empty string, this means isel
287 /// should lower Intrinsic::trap to a call to the specified function name
288 /// instead of an ISD::TRAP node.
289 StringRef getTrapFunctionName() {
290 return TrapFuncName;
291 }
132 /// HonorSignDependentRoundingFPMath - Return true if the codegen must assume
133 /// that the rounding mode of the FPU can change from its default.
134 bool TargetOptions::HonorSignDependentRoundingFPMath() const {
135 return !UnsafeFPMath && HonorSignDependentRoundingFPMathOption;
292136 }
137
138 /// getTrapFunctionName - If this returns a non-empty string, this means isel
139 /// should lower Intrinsic::trap to a call to the specified function name
140 /// instead of an ISD::TRAP node.
141 StringRef TargetOptions::getTrapFunctionName() const {
142 return TrapFuncName;
143 }
727727
728728 // fastcc with -tailcallopt is intended to provide a guaranteed
729729 // tail call optimization. Fastisel doesn't know how to do that.
730 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
730 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
731731 return false;
732732
733733 // Let SDISel handle vararg functions.
15281528
15291529 // fastcc with -tailcallopt is intended to provide a guaranteed
15301530 // tail call optimization. Fastisel doesn't know how to do that.
1531 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1531 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
15321532 return false;
15331533
15341534 PointerType *PT = cast(CS.getCalledValue()->getType());
15421542
15431543 // Fast-isel doesn't know about callee-pop yet.
15441544 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1545 GuaranteedTailCallOpt))
1545 TM.Options.GuaranteedTailCallOpt))
15461546 return false;
15471547
15481548 // Check whether the function can return without sret-demotion.
4646 const MachineModuleInfo &MMI = MF.getMMI();
4747 const TargetRegisterInfo *RI = TM.getRegisterInfo();
4848
49 return (DisableFramePointerElim(MF) ||
49 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
5050 RI->needsStackRealignment(MF) ||
5151 MFI->hasVarSizedObjects() ||
5252 MFI->isFrameAddressTaken() ||
637637 // stack pointer (we fit in the Red Zone).
638638 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
639639 !RegInfo->needsStackRealignment(MF) &&
640 !MFI->hasVarSizedObjects() && // No dynamic alloca.
641 !MFI->adjustsStack() && // No calls.
642 !IsWin64 && // Win64 has no Red Zone
643 !EnableSegmentedStacks) { // Regular stack
640 !MFI->hasVarSizedObjects() && // No dynamic alloca.
641 !MFI->adjustsStack() && // No calls.
642 !IsWin64 && // Win64 has no Red Zone
643 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
644644 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
645645 if (HasFP) MinSize += SlotSize;
646646 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
255255 if (Subtarget->is64Bit()) {
256256 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
257257 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
258 } else if (!UseSoftFloat) {
258 } else if (!TM.Options.UseSoftFloat) {
259259 // We have an algorithm for SSE2->double, and we turn this into a
260260 // 64-bit FILD followed by conditional FADD for other targets.
261261 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
269269 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
270270 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
271271
272 if (!UseSoftFloat) {
272 if (!TM.Options.UseSoftFloat) {
273273 // SSE has no i16 to fp conversion, only i32
274274 if (X86ScalarSSEf32) {
275275 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
312312 if (Subtarget->is64Bit()) {
313313 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
314314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
315 } else if (!UseSoftFloat) {
315 } else if (!TM.Options.UseSoftFloat) {
316316 // Since AVX is a superset of SSE3, only check for SSE here.
317317 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
318318 // Expand FP_TO_UINT into a select.
536536 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
537537 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
538538 MVT::i64 : MVT::i32, Custom);
539 else if (EnableSegmentedStacks)
539 else if (TM.Options.EnableSegmentedStacks)
540540 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
541541 MVT::i64 : MVT::i32, Custom);
542542 else
543543 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
544544 MVT::i64 : MVT::i32, Expand);
545545
546 if (!UseSoftFloat && X86ScalarSSEf64) {
546 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
547547 // f32 and f64 use SSE.
548548 // Set up the FP register classes.
549549 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
575575 // cases we handle.
576576 addLegalFPImmediate(APFloat(+0.0)); // xorpd
577577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 } else if (!UseSoftFloat && X86ScalarSSEf32) {
578 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
579579 // Use SSE for f32, x87 for f64.
580580 // Set up the FP register classes.
581581 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
604604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606606
607 if (!UnsafeFPMath) {
607 if (!TM.Options.UnsafeFPMath) {
608608 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
609609 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
610610 }
611 } else if (!UseSoftFloat) {
611 } else if (!TM.Options.UseSoftFloat) {
612612 // f32 and f64 in x87.
613613 // Set up the FP register classes.
614614 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
619619 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
620620 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
621621
622 if (!UnsafeFPMath) {
622 if (!TM.Options.UnsafeFPMath) {
623623 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
624624 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
625625 }
638638 setOperationAction(ISD::FMA, MVT::f32, Expand);
639639
640640 // Long double always uses X87.
641 if (!UseSoftFloat) {
641 if (!TM.Options.UseSoftFloat) {
642642 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
643643 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
644644 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
657657 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
658658 }
659659
660 if (!UnsafeFPMath) {
660 if (!TM.Options.UnsafeFPMath) {
661661 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
662662 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
663663 }
747747
748748 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
749749 // with -msoft-float, disable use of MMX as well.
750 if (!UseSoftFloat && Subtarget->hasMMX()) {
750 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
751751 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
752752 // No operations on x86mmx supported, everything uses intrinsics.
753753 }
784784 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
785785 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
786786
787 if (!UseSoftFloat && Subtarget->hasXMM()) {
787 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) {
788788 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
789789
790790 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
801801 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
802802 }
803803
804 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
804 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) {
805805 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
806806
807807 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
982982 if (Subtarget->hasSSE42orAVX())
983983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984984
985 if (!UseSoftFloat && Subtarget->hasAVX()) {
985 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
986986 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
987987 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
988988 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
17081708
17091709 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
17101710 /// a tailcall target by changing its ABI.
1711 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1711 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1712 bool GuaranteedTailCallOpt) {
17121713 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
17131714 }
17141715
17221723 unsigned i) const {
17231724 // Create the nodes corresponding to a load from this parameter slot.
17241725 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1725 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1726 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1727 getTargetMachine().Options.GuaranteedTailCallOpt);
17261728 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
17271729 EVT ValVT;
17281730
18721874
18731875 unsigned StackSize = CCInfo.getNextStackOffset();
18741876 // Align stack specially for tail calls.
1875 if (FuncIsMadeTailCallSafe(CallConv))
1877 if (FuncIsMadeTailCallSafe(CallConv,
1878 MF.getTarget().Options.GuaranteedTailCallOpt))
18761879 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
18771880
18781881 // If the function takes variable number of arguments, make a frame index for
19171920 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
19181921 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
19191922 "SSE register cannot be used when SSE is disabled!");
1920 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1923 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1924 NoImplicitFloatOps) &&
19211925 "SSE register cannot be used when SSE is disabled!");
1922 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1926 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1927 !Subtarget->hasXMM())
19231928 // Kernel mode asks for SSE to be disabled, so don't push them
19241929 // on the stack.
19251930 TotalNumXMMRegs = 0;
19972002 }
19982003
19992004 // Some CCs need callee pop.
2000 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
2005 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2006 MF.getTarget().Options.GuaranteedTailCallOpt)) {
20012007 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
20022008 } else {
20032009 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
20972103
20982104 // Sibcalls are automatically detected tailcalls which do not require
20992105 // ABI changes.
2100 if (!GuaranteedTailCallOpt && isTailCall)
2106 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
21012107 IsSibcall = true;
21022108
21032109 if (isTailCall)
21252131 // This is a sibcall. The memory operands are available in caller's
21262132 // own caller's stack.
21272133 NumBytes = 0;
2128 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2134 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2135 IsTailCallConvention(CallConv))
21292136 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
21302137
21312138 int FPDiff = 0;
23042311 int FI = 0;
23052312 // Do not flag preceding copytoreg stuff together with the following stuff.
23062313 InFlag = SDValue();
2307 if (GuaranteedTailCallOpt) {
2314 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
23082315 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
23092316 CCValAssign &VA = ArgLocs[i];
23102317 if (VA.isRegLoc())
24842491
24852492 // Create the CALLSEQ_END node.
24862493 unsigned NumBytesForCalleeToPush;
2487 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2494 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2495 getTargetMachine().Options.GuaranteedTailCallOpt))
24882496 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
24892497 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
24902498 // If this is a call to a struct-return function, the callee
26422650 CallingConv::ID CallerCC = CallerF->getCallingConv();
26432651 bool CCMatch = CallerCC == CalleeCC;
26442652
2645 if (GuaranteedTailCallOpt) {
2653 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
26462654 if (IsTailCallConvention(CalleeCC) && CCMatch)
26472655 return true;
26482656 return false;
91189126 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
91199127 SelectionDAG &DAG) const {
91209128 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9121 EnableSegmentedStacks) &&
9129 getTargetMachine().Options.EnableSegmentedStacks) &&
91229130 "This should be used only on Windows targets or when segmented stacks "
91239131 "are being used");
91249132 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
91329140 bool Is64Bit = Subtarget->is64Bit();
91339141 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
91349142
9135 if (EnableSegmentedStacks) {
9143 if (getTargetMachine().Options.EnableSegmentedStacks) {
91369144 MachineFunction &MF = DAG.getMachineFunction();
91379145 MachineRegisterInfo &MRI = MF.getRegInfo();
91389146
92689276
92699277 if (ArgMode == 2) {
92709278 // Sanity Check: Make sure using fp_offset makes sense.
9271 assert(!UseSoftFloat &&
9279 assert(!getTargetMachine().Options.UseSoftFloat &&
92729280 !(DAG.getMachineFunction()
92739281 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
92749282 Subtarget->hasXMM());
1214312151 MachineFunction *MF = BB->getParent();
1214412152 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1214512153
12146 assert(EnableSegmentedStacks);
12154 assert(getTargetMachine().Options.EnableSegmentedStacks);
1214712155
1214812156 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
1214912157 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
1302313031 // the operands would cause it to handle comparisons between positive
1302413032 // and negative zero incorrectly.
1302513033 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13026 if (!UnsafeFPMath &&
13034 if (!DAG.getTarget().Options.UnsafeFPMath &&
1302713035 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
1302813036 break;
1302913037 std::swap(LHS, RHS);
1303313041 case ISD::SETOLE:
1303413042 // Converting this to a min would handle comparisons between positive
1303513043 // and negative zero incorrectly.
13036 if (!UnsafeFPMath &&
13044 if (!DAG.getTarget().Options.UnsafeFPMath &&
1303713045 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
1303813046 break;
1303913047 Opcode = X86ISD::FMIN;
1305113059 case ISD::SETOGE:
1305213060 // Converting this to a max would handle comparisons between positive
1305313061 // and negative zero incorrectly.
13054 if (!UnsafeFPMath &&
13062 if (!DAG.getTarget().Options.UnsafeFPMath &&
1305513063 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
1305613064 break;
1305713065 Opcode = X86ISD::FMAX;
1306113069 // the operands would cause it to handle comparisons between positive
1306213070 // and negative zero incorrectly.
1306313071 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13064 if (!UnsafeFPMath &&
13072 if (!DAG.getTarget().Options.UnsafeFPMath &&
1306513073 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
1306613074 break;
1306713075 std::swap(LHS, RHS);
1308713095 // Converting this to a min would handle comparisons between positive
1308813096 // and negative zero incorrectly, and swapping the operands would
1308913097 // cause it to handle NaNs incorrectly.
13090 if (!UnsafeFPMath &&
13098 if (!DAG.getTarget().Options.UnsafeFPMath &&
1309113099 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
1309213100 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
1309313101 break;
1309713105 break;
1309813106 case ISD::SETUGT:
1309913107 // Converting this to a min would handle NaNs incorrectly.
13100 if (!UnsafeFPMath &&
13108 if (!DAG.getTarget().Options.UnsafeFPMath &&
1310113109 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
1310213110 break;
1310313111 Opcode = X86ISD::FMIN;
1312213130 // Converting this to a max would handle comparisons between positive
1312313131 // and negative zero incorrectly, and swapping the operands would
1312413132 // cause it to handle NaNs incorrectly.
13125 if (!UnsafeFPMath &&
13133 if (!DAG.getTarget().Options.UnsafeFPMath &&
1312613134 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
1312713135 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
1312813136 break;
1408614094 SDValue StoredVal = St->getOperand(1);
1408714095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1408814096
14089 // If we are saving a concatination of two XMM registers, perform two stores.
14097 // If we are saving a concatenation of two XMM registers, perform two stores.
1409014098 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
1409114099 // 128-bit ones. If in the future the cost becomes only one memory access the
1409214100 // first version would be better.
1419614204
1419714205 const Function *F = DAG.getMachineFunction().getFunction();
1419814206 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14199 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
14207 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
1420014208 && Subtarget->hasXMMInt();
1420114209 if ((VT.isVector() ||
1420214210 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
451451
452452 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
453453 const MachineFrameInfo *MFI = MF.getFrameInfo();
454 return (RealignStack &&
454 return (MF.getTarget().Options.RealignStack &&
455455 !MFI->hasVarSizedObjects());
456456 }
457457
389389 assert((!In64BitMode || HasX86_64) &&
390390 "64-bit code requested on a subtarget that doesn't support it!");
391391
392 if(EnableSegmentedStacks && !isTargetELF())
393 report_fatal_error("Segmented stacks are only implemented on ELF.");
394
395392 // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
396393 // 32 and 64 bit) and for all 64-bit targets.
397394 if (StackAlignOverride)
3030
3131 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
3232 StringRef CPU, StringRef FS,
33 const TargetOptions &Options,
3334 Reloc::Model RM, CodeModel::Model CM,
3435 CodeGenOpt::Level OL)
35 : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, false),
36 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
3637 DataLayout(getSubtargetImpl()->isTargetDarwin() ?
3738 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
3839 "n8:16:32-S128" :
5152
5253 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
5354 StringRef CPU, StringRef FS,
55 const TargetOptions &Options,
5456 Reloc::Model RM, CodeModel::Model CM,
5557 CodeGenOpt::Level OL)
56 : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, true),
58 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
5759 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
5860 "n8:16:32:64-S128"),
5961 InstrInfo(*this),
6668 ///
6769 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
6870 StringRef CPU, StringRef FS,
71 const TargetOptions &Options,
6972 Reloc::Model RM, CodeModel::Model CM,
7073 CodeGenOpt::Level OL,
7174 bool is64Bit)
72 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
73 Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
75 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
76 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
7477 FrameLowering(*this, Subtarget),
7578 ELFWriterInfo(is64Bit, true) {
7679 // Determine the PICStyle based on the target selected.
9497 }
9598
9699 // default to hard float ABI
97 if (FloatABIType == FloatABI::Default)
98 FloatABIType = FloatABI::Hard;
100 if (Options.FloatABIType == FloatABI::Default)
101 this->Options.FloatABIType = FloatABI::Hard;
102
103 if (Options.EnableSegmentedStacks && !Subtarget.isTargetELF())
104 report_fatal_error("Segmented stacks are only implemented on ELF.");
99105 }
100106
101107 //===----------------------------------------------------------------------===//
3737
3838 public:
3939 X86TargetMachine(const Target &T, StringRef TT,
40 StringRef CPU, StringRef FS,
40 StringRef CPU, StringRef FS, const TargetOptions &Options,
4141 Reloc::Model RM, CodeModel::Model CM,
4242 CodeGenOpt::Level OL,
4343 bool is64Bit);
8484 X86JITInfo JITInfo;
8585 public:
8686 X86_32TargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
87 StringRef CPU, StringRef FS, const TargetOptions &Options,
8888 Reloc::Model RM, CodeModel::Model CM,
8989 CodeGenOpt::Level OL);
9090 virtual const TargetData *getTargetData() const { return &DataLayout; }
112112 X86JITInfo JITInfo;
113113 public:
114114 X86_64TargetMachine(const Target &T, StringRef TT,
115 StringRef CPU, StringRef FS,
115 StringRef CPU, StringRef FS, const TargetOptions &Options,
116116 Reloc::Model RM, CodeModel::Model CM,
117117 CodeGenOpt::Level OL);
118118 virtual const TargetData *getTargetData() const { return &DataLayout; }
8383 }
8484
8585 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
86 return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();
86 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
87 MF.getFrameInfo()->hasVarSizedObjects();
8788 }
8889
8990 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
2020 ///
2121 XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
2222 StringRef CPU, StringRef FS,
23 const TargetOptions &Options,
2324 Reloc::Model RM, CodeModel::Model CM,
2425 CodeGenOpt::Level OL)
25 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
26 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
2627 Subtarget(TT, CPU, FS),
2728 DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
2829 "i16:16:32-i32:32:32-i64:32:32-n32"),
3232 XCoreSelectionDAGInfo TSInfo;
3333 public:
3434 XCoreTargetMachine(const Target &T, StringRef TT,
35 StringRef CPU, StringRef FS,
35 StringRef CPU, StringRef FS, const TargetOptions &Options,
3636 Reloc::Model RM, CodeModel::Model CM,
3737 CodeGenOpt::Level OL);
3838
140140 cl::desc("Do not emit code that uses the red zone."),
141141 cl::init(false));
142142
143 static cl::opt
144 EnableFPMAD("enable-fp-mad",
145 cl::desc("Enable less precise MAD instructions to be generated"),
146 cl::init(false));
147
148 static cl::opt
149 PrintCode("print-machineinstrs",
150 cl::desc("Print generated machine code"),
151 cl::init(false));
152
153 static cl::opt
154 DisableFPElim("disable-fp-elim",
155 cl::desc("Disable frame pointer elimination optimization"),
156 cl::init(false));
157
158 static cl::opt
159 DisableFPElimNonLeaf("disable-non-leaf-fp-elim",
160 cl::desc("Disable frame pointer elimination optimization for non-leaf funcs"),
161 cl::init(false));
162
163 static cl::opt
164 DisableExcessPrecision("disable-excess-fp-precision",
165 cl::desc("Disable optimizations that may increase FP precision"),
166 cl::init(false));
167
168 static cl::opt
169 EnableUnsafeFPMath("enable-unsafe-fp-math",
170 cl::desc("Enable optimizations that may decrease FP precision"),
171 cl::init(false));
172
173 static cl::opt
174 EnableNoInfsFPMath("enable-no-infs-fp-math",
175 cl::desc("Enable FP math optimizations that assume no +-Infs"),
176 cl::init(false));
177
178 static cl::opt
179 EnableNoNaNsFPMath("enable-no-nans-fp-math",
180 cl::desc("Enable FP math optimizations that assume no NaNs"),
181 cl::init(false));
182
183 static cl::opt
184 EnableHonorSignDependentRoundingFPMath("enable-sign-dependent-rounding-fp-math",
185 cl::Hidden,
186 cl::desc("Force codegen to assume rounding mode can change dynamically"),
187 cl::init(false));
188
189 static cl::opt
190 GenerateSoftFloatCalls("soft-float",
191 cl::desc("Generate software floating point library calls"),
192 cl::init(false));
193
194 static cl::opt
195 FloatABIForCalls("float-abi",
196 cl::desc("Choose float ABI type"),
197 cl::init(FloatABI::Default),
198 cl::values(
199 clEnumValN(FloatABI::Default, "default",
200 "Target default float ABI type"),
201 clEnumValN(FloatABI::Soft, "soft",
202 "Soft float ABI (implied by -soft-float)"),
203 clEnumValN(FloatABI::Hard, "hard",
204 "Hard float ABI (uses FP registers)"),
205 clEnumValEnd));
206
207 static cl::opt
208 DontPlaceZerosInBSS("nozero-initialized-in-bss",
209 cl::desc("Don't place zero-initialized symbols into bss section"),
210 cl::init(false));
211
212 static cl::opt
213 EnableJITExceptionHandling("jit-enable-eh",
214 cl::desc("Emit exception handling information"),
215 cl::init(false));
216
217 // In debug builds, make this default to true.
218 #ifdef NDEBUG
219 #define EMIT_DEBUG false
220 #else
221 #define EMIT_DEBUG true
222 #endif
223 static cl::opt
224 EmitJitDebugInfo("jit-emit-debug",
225 cl::desc("Emit debug information to debugger"),
226 cl::init(EMIT_DEBUG));
227 #undef EMIT_DEBUG
228
229 static cl::opt
230 EmitJitDebugInfoToDisk("jit-emit-debug-to-disk",
231 cl::Hidden,
232 cl::desc("Emit debug info objfiles to disk"),
233 cl::init(false));
234
235 static cl::opt
236 EnableGuaranteedTailCallOpt("tailcallopt",
237 cl::desc("Turn fastcc calls into tail calls by (potentially) changing ABI."),
238 cl::init(false));
239
240 static cl::opt
241 OverrideStackAlignment("stack-alignment",
242 cl::desc("Override default stack alignment"),
243 cl::init(0));
244
245 static cl::opt
246 EnableRealignStack("realign-stack",
247 cl::desc("Realign stack if needed"),
248 cl::init(true));
249
250 static cl::opt
251 DisableSwitchTables(cl::Hidden, "disable-jump-tables",
252 cl::desc("Do not generate jump tables."),
253 cl::init(false));
254
255 static cl::opt
256 EnableStrongPHIElim(cl::Hidden, "strong-phi-elim",
257 cl::desc("Use strong PHI elimination."),
258 cl::init(false));
259
260 static cl::opt
261 TrapFuncName("trap-func", cl::Hidden,
262 cl::desc("Emit a call to trap function rather than a trap instruction"),
263 cl::init(""));
264
265 static cl::opt
266 SegmentedStacks("segmented-stacks",
267 cl::desc("Use segmented stacks if possible."),
268 cl::init(false));
269
270
143271 // GetFileNameRoot - Helper function to get the basename of a filename.
144272 static inline std::string
145273 GetFileNameRoot(const std::string &InputFilename) {
317445 case '3': OLvl = CodeGenOpt::Aggressive; break;
318446 }
319447
448 TargetOptions Options;
449 Options.LessPreciseFPMADOption = EnableFPMAD;
450 Options.PrintMachineCode = PrintCode;
451 Options.NoFramePointerElim = DisableFPElim;
452 Options.NoFramePointerElimNonLeaf = DisableFPElimNonLeaf;
453 Options.NoExcessFPPrecision = DisableExcessPrecision;
454 Options.UnsafeFPMath = EnableUnsafeFPMath;
455 Options.NoInfsFPMath = EnableNoInfsFPMath;
456 Options.NoNaNsFPMath = EnableNoNaNsFPMath;
457 Options.HonorSignDependentRoundingFPMathOption =
458 EnableHonorSignDependentRoundingFPMath;
459 Options.UseSoftFloat = GenerateSoftFloatCalls;
460 if (FloatABIForCalls != FloatABI::Default)
461 Options.FloatABIType = FloatABIForCalls;
462 Options.NoZerosInBSS = DontPlaceZerosInBSS;
463 Options.JITExceptionHandling = EnableJITExceptionHandling;
464 Options.JITEmitDebugInfo = EmitJitDebugInfo;
465 Options.JITEmitDebugInfoToDisk = EmitJitDebugInfoToDisk;
466 Options.GuaranteedTailCallOpt = EnableGuaranteedTailCallOpt;
467 Options.StackAlignmentOverride = OverrideStackAlignment;
468 Options.RealignStack = EnableRealignStack;
469 Options.DisableJumpTables = DisableSwitchTables;
470 Options.TrapFuncName = TrapFuncName;
471 Options.EnableSegmentedStacks = SegmentedStacks;
472
320473 std::auto_ptr
321474 target(TheTarget->createTargetMachine(TheTriple.getTriple(),
322 MCPU, FeaturesStr,
475 MCPU, FeaturesStr, Options,
323476 RelocModel, CMModel, OLvl));
324477 assert(target.get() && "Could not allocate target machine!");
325478 TargetMachine &Target = *target.get();
332485
333486 if (EnableDwarfDirectory)
334487 Target.setMCUseDwarfDirectory(true);
488
489 if (GenerateSoftFloatCalls)
490 FloatABIForCalls = FloatABI::Soft;
335491
336492 // Disable .loc support for older OS X versions.
337493 if (TheTriple.isMacOSX() &&
264264 SubtargetFeatures Features;
265265 Features.getDefaultSubtargetFeatures(llvm::Triple(Triple));
266266 std::string FeatureStr = Features.getString();
267 _target = march->createTargetMachine(Triple, _mCpu, FeatureStr,
267 TargetOptions Options;
268 _target = march->createTargetMachine(Triple, _mCpu, FeatureStr, Options,
268269 RelocModel);
269270 }
270271 return false;
158158 Features.getDefaultSubtargetFeatures(llvm::Triple(Triple));
159159 std::string FeatureStr = Features.getString();
160160 std::string CPU;
161 TargetMachine *target = march->createTargetMachine(Triple, CPU, FeatureStr);
161 TargetOptions Options;
162 TargetMachine *target = march->createTargetMachine(Triple, CPU, FeatureStr,
163 Options);
162164 LTOModule *Ret = new LTOModule(m.take(), target);
163165 if (Ret->ParseSymbols(errMsg)) {
164166 delete Ret;