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Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs" This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274367 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 4 years ago
1 changed file(s) with 334 addition(s) and 151 deletion(s). Raw diff Collapse all Expand all
535535 }
536536
537537 class T2MulLong opc22_20, bits<4> opc7_4,
538 string opc, list pattern>
539 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
540 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
538 dag oops, dag iops, InstrItinClass itin,
539 string opc, string asm, list pattern>
540 : T2I {
541541 bits<4> RdLo;
542542 bits<4> RdHi;
543543 bits<4> Rn;
551551 let Inst{7-4} = opc7_4;
552552 let Inst{3-0} = Rm;
553553 }
554 class T2MlaLong opc22_20, bits<4> opc7_4, string opc>
555 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
556 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
557 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
558 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
554 class T2MlaLong opc22_20, bits<4> opc7_4,
555 dag oops, dag iops, InstrItinClass itin,
556 string opc, string asm, list pattern>
557 : T2I {
559558 bits<4> RdLo;
560559 bits<4> RdHi;
561560 bits<4> Rn;
25442543 let Inst{7-4} = 0b0000; // Multiply
25452544 }
25462545
2547 class T2FourRegMLA op7_4, string opc, list pattern>
2548 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2549 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2550 Requires<[IsThumb2, UseMulOps]> {
2546 def t2MLA: T2FourReg<
2547 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2548 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2549 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2550 Requires<[IsThumb2, UseMulOps]> {
25512551 let Inst{31-27} = 0b11111;
25522552 let Inst{26-23} = 0b0110;
25532553 let Inst{22-20} = 0b000;
2554 let Inst{7-4} = op7_4;
2555 }
2556
2557 def t2MLA : T2FourRegMLA<0b0000, "mla",
2558 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2559 rGPR:$Ra))]>;
2560 def t2MLS: T2FourRegMLA<0b0001, "mls",
2561 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2562 rGPR:$Rm)))]>;
2554 let Inst{7-4} = 0b0000; // Multiply
2555 }
2556
2557 def t2MLS: T2FourReg<
2558 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2559 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2560 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2561 Requires<[IsThumb2, UseMulOps]> {
2562 let Inst{31-27} = 0b11111;
2563 let Inst{26-23} = 0b0110;
2564 let Inst{22-20} = 0b000;
2565 let Inst{7-4} = 0b0001; // Multiply and Subtract
2566 }
25632567
25642568 // Extra precision multiplies with low / high results
25652569 let hasSideEffects = 0 in {
25662570 let isCommutable = 1 in {
2567 def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
2568 def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
2571 def t2SMULL : T2MulLong<0b000, 0b0000,
2572 (outs rGPR:$RdLo, rGPR:$RdHi),
2573 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2574 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2575
2576 def t2UMULL : T2MulLong<0b010, 0b0000,
2577 (outs rGPR:$RdLo, rGPR:$RdHi),
2578 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2579 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
25692580 } // isCommutable
25702581
25712582 // Multiply + accumulate
2572 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
2573 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
2574 def t2UMAAL : T2MulLong<0b110, 0b0110, "umaal", []>,
2575 Requires<[IsThumb2, HasDSP]>;
2583 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2584 (outs rGPR:$RdLo, rGPR:$RdHi),
2585 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2586 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2587 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2588
2589 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2590 (outs rGPR:$RdLo, rGPR:$RdHi),
2591 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2592 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2593 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2594
2595 def t2UMAAL : T2MulLong<0b110, 0b0110,
2596 (outs rGPR:$RdLo, rGPR:$RdHi),
2597 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2598 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2599 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
2600 Requires<[IsThumb2, HasDSP]>;
25762601 } // hasSideEffects
25772602
25782603 // Rounding variants of the below included for disassembly only
25792604
25802605 // Most significant word multiply
2581 class T2SMMUL op7_4, string opc, list pattern>
2582 : T2ThreeReg<(outs rGPR:$Rd),
2583 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2584 opc, "\t$Rd, $Rn, $Rm", pattern>,
2585 Requires<[IsThumb2, HasDSP]> {
2606 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2607 "smmul", "\t$Rd, $Rn, $Rm",
2608 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2609 Requires<[IsThumb2, HasDSP]> {
25862610 let Inst{31-27} = 0b11111;
25872611 let Inst{26-23} = 0b0110;
25882612 let Inst{22-20} = 0b101;
25892613 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2590 let Inst{7-4} = op7_4;
2591 }
2592 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2593 rGPR:$Rm))]>;
2594 def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
2595
2596 class T2FourRegSMMLA op22_20, bits<4> op7_4, string opc,
2597 list pattern>
2598 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2599 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2614 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2615 }
2616
2617 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2618 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2619 Requires<[IsThumb2, HasDSP]> {
2620 let Inst{31-27} = 0b11111;
2621 let Inst{26-23} = 0b0110;
2622 let Inst{22-20} = 0b101;
2623 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2624 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2625 }
2626
2627 def t2SMMLA : T2FourReg<
2628 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2629 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2630 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
26002631 Requires<[IsThumb2, HasDSP, UseMulOps]> {
26012632 let Inst{31-27} = 0b11111;
26022633 let Inst{26-23} = 0b0110;
2603 let Inst{22-20} = op22_20;
2604 let Inst{7-4} = op7_4;
2605 }
2606
2607 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
2608 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
2609 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
2610 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
2611 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
2612 def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
2613
2614 class T2ThreeRegSMUL op22_20, bits<2> op5_4, string opc,
2615 list pattern>
2616 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
2617 "\t$Rd, $Rn, $Rm", pattern>,
2618 Requires<[IsThumb2, HasDSP]> {
2634 let Inst{22-20} = 0b101;
2635 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2636 }
2637
2638 def t2SMMLAR: T2FourReg<
2639 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2640 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2641 Requires<[IsThumb2, HasDSP]> {
2642 let Inst{31-27} = 0b11111;
2643 let Inst{26-23} = 0b0110;
2644 let Inst{22-20} = 0b101;
2645 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2646 }
2647
2648 def t2SMMLS: T2FourReg<
2649 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2650 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2651 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2652 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2653 let Inst{31-27} = 0b11111;
2654 let Inst{26-23} = 0b0110;
2655 let Inst{22-20} = 0b110;
2656 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2657 }
2658
2659 def t2SMMLSR:T2FourReg<
2660 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2661 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2662 Requires<[IsThumb2, HasDSP]> {
2663 let Inst{31-27} = 0b11111;
2664 let Inst{26-23} = 0b0110;
2665 let Inst{22-20} = 0b110;
2666 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2667 }
2668
2669 multiclass T2I_smul {
2670 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2671 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2672 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2673 (sext_inreg rGPR:$Rm, i16)))]>,
2674 Requires<[IsThumb2, HasDSP]> {
26192675 let Inst{31-27} = 0b11111;
26202676 let Inst{26-23} = 0b0110;
2621 let Inst{22-20} = op22_20;
2677 let Inst{22-20} = 0b001;
26222678 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
26232679 let Inst{7-6} = 0b00;
2624 let Inst{5-4} = op5_4;
2625 }
2626
2627 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
2628 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2629 (sext_inreg rGPR:$Rm, i16)))]>;
2630 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
2631 [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
2632 (sra rGPR:$Rm, (i32 16))))]>;
2633 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
2634 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2635 (sext_inreg rGPR:$Rm, i16)))]>;
2636 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
2637 [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
2638 (sra rGPR:$Rm, (i32 16))))]>;
2639 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
2640 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
2641
2642 class T2FourRegSMLA op5_4, string opc, list pattern>
2643 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
2644 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2645 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2680 let Inst{5-4} = 0b00;
2681 }
2682
2683 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2684 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2685 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2686 (sra rGPR:$Rm, (i32 16))))]>,
2687 Requires<[IsThumb2, HasDSP]> {
2688 let Inst{31-27} = 0b11111;
2689 let Inst{26-23} = 0b0110;
2690 let Inst{22-20} = 0b001;
2691 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2692 let Inst{7-6} = 0b00;
2693 let Inst{5-4} = 0b01;
2694 }
2695
2696 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2697 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2698 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2699 (sext_inreg rGPR:$Rm, i16)))]>,
2700 Requires<[IsThumb2, HasDSP]> {
2701 let Inst{31-27} = 0b11111;
2702 let Inst{26-23} = 0b0110;
2703 let Inst{22-20} = 0b001;
2704 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2705 let Inst{7-6} = 0b00;
2706 let Inst{5-4} = 0b10;
2707 }
2708
2709 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2710 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2711 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2712 (sra rGPR:$Rm, (i32 16))))]>,
2713 Requires<[IsThumb2, HasDSP]> {
2714 let Inst{31-27} = 0b11111;
2715 let Inst{26-23} = 0b0110;
2716 let Inst{22-20} = 0b001;
2717 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2718 let Inst{7-6} = 0b00;
2719 let Inst{5-4} = 0b11;
2720 }
2721
2722 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2723 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2724 []>,
2725 Requires<[IsThumb2, HasDSP]> {
2726 let Inst{31-27} = 0b11111;
2727 let Inst{26-23} = 0b0110;
2728 let Inst{22-20} = 0b011;
2729 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2730 let Inst{7-6} = 0b00;
2731 let Inst{5-4} = 0b00;
2732 }
2733
2734 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2735 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2736 []>,
2737 Requires<[IsThumb2, HasDSP]> {
2738 let Inst{31-27} = 0b11111;
2739 let Inst{26-23} = 0b0110;
2740 let Inst{22-20} = 0b011;
2741 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2742 let Inst{7-6} = 0b00;
2743 let Inst{5-4} = 0b01;
2744 }
2745 }
2746
2747
2748 multiclass T2I_smla {
2749 def BB : T2FourReg<
2750 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2751 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2752 [(set rGPR:$Rd, (add rGPR:$Ra,
2753 (opnode (sext_inreg rGPR:$Rn, i16),
2754 (sext_inreg rGPR:$Rm, i16))))]>,
2755 Requires<[IsThumb2, HasDSP, UseMulOps]> {
26462756 let Inst{31-27} = 0b11111;
26472757 let Inst{26-23} = 0b0110;
26482758 let Inst{22-20} = 0b001;
26492759 let Inst{7-6} = 0b00;
2650 let Inst{5-4} = op5_4;
2651 }
2652
2653 def t2SMLABB : T2FourRegSMLA<0b00, "smlabb",
2654 [(set rGPR:$Rd, (add rGPR:$Ra,
2655 (mul (sext_inreg rGPR:$Rn, i16),
2656 (sext_inreg rGPR:$Rm, i16))))]>;
2657 def t2SMLABT : T2FourRegSMLA<0b01, "smlabt",
2658 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
2659 (sra rGPR:$Rm, (i32 16)))))]>;
2660 def t2SMLATB : T2FourRegSMLA<0b10, "smlatb",
2661 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2662 (sext_inreg rGPR:$Rm, i16))))]>;
2663 def t2SMLATT : T2FourRegSMLA<0b11, "smlatt",
2664 [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
2665 (sra rGPR:$Rm, (i32 16)))))]>;
2666 def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
2667 let Inst{22-20} = 0b011;
2668 }
2669 def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
2670 let Inst{22-20} = 0b011;
2671 }
2672
2673 class T2SMLAL op22_20, bits<4> op7_4, string opc, list pattern>
2674 : T2FourReg_mac<1, op22_20, op7_4,
2675 (outs rGPR:$Ra, rGPR:$Rd),
2676 (ins rGPR:$Rn, rGPR:$Rm),
2677 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2678 Requires<[IsThumb2, HasDSP]>;
2760 let Inst{5-4} = 0b00;
2761 }
2762
2763 def BT : T2FourReg<
2764 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2765 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2766 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2767 (sra rGPR:$Rm, (i32 16)))))]>,
2768 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2769 let Inst{31-27} = 0b11111;
2770 let Inst{26-23} = 0b0110;
2771 let Inst{22-20} = 0b001;
2772 let Inst{7-6} = 0b00;
2773 let Inst{5-4} = 0b01;
2774 }
2775
2776 def TB : T2FourReg<
2777 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2778 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2779 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2780 (sext_inreg rGPR:$Rm, i16))))]>,
2781 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2782 let Inst{31-27} = 0b11111;
2783 let Inst{26-23} = 0b0110;
2784 let Inst{22-20} = 0b001;
2785 let Inst{7-6} = 0b00;
2786 let Inst{5-4} = 0b10;
2787 }
2788
2789 def TT : T2FourReg<
2790 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2791 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2792 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2793 (sra rGPR:$Rm, (i32 16)))))]>,
2794 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2795 let Inst{31-27} = 0b11111;
2796 let Inst{26-23} = 0b0110;
2797 let Inst{22-20} = 0b001;
2798 let Inst{7-6} = 0b00;
2799 let Inst{5-4} = 0b11;
2800 }
2801
2802 def WB : T2FourReg<
2803 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2804 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2805 []>,
2806 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2807 let Inst{31-27} = 0b11111;
2808 let Inst{26-23} = 0b0110;
2809 let Inst{22-20} = 0b011;
2810 let Inst{7-6} = 0b00;
2811 let Inst{5-4} = 0b00;
2812 }
2813
2814 def WT : T2FourReg<
2815 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2816 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2817 []>,
2818 Requires<[IsThumb2, HasDSP, UseMulOps]> {
2819 let Inst{31-27} = 0b11111;
2820 let Inst{26-23} = 0b0110;
2821 let Inst{22-20} = 0b011;
2822 let Inst{7-6} = 0b00;
2823 let Inst{5-4} = 0b01;
2824 }
2825 }
2826
2827 defm t2SMUL : T2I_smul<"smul", mul>;
2828 defm t2SMLA : T2I_smla<"smla", mul>;
26792829
26802830 // Halfword multiple accumulate long: SMLAL
2681 def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
2682 def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
2683 def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
2684 def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
2685
2686 class T2DualHalfMul op22_20, bits<4> op7_4, string opc>
2687 : T2ThreeReg_mac<0, op22_20, op7_4,
2688 (outs rGPR:$Rd),
2689 (ins rGPR:$Rn, rGPR:$Rm),
2690 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
2691 Requires<[IsThumb2, HasDSP]> {
2831 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2832 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2833 [/* For disassembly only; pattern left blank */]>,
2834 Requires<[IsThumb2, HasDSP]>;
2835 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2836 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2837 [/* For disassembly only; pattern left blank */]>,
2838 Requires<[IsThumb2, HasDSP]>;
2839 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2840 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2841 [/* For disassembly only; pattern left blank */]>,
2842 Requires<[IsThumb2, HasDSP]>;
2843 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2844 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2845 [/* For disassembly only; pattern left blank */]>,
2846 Requires<[IsThumb2, HasDSP]>;
2847
2848 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2849 def t2SMUAD: T2ThreeReg_mac<
2850 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2851 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2852 Requires<[IsThumb2, HasDSP]> {
26922853 let Inst{15-12} = 0b1111;
26932854 }
2694
2695 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2696 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
2697 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
2698 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
2699 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
2700
2701 class T2DualHalfMulAdd op22_20, bits<4> op7_4, string opc>
2702 : T2FourReg_mac<0, op22_20, op7_4,
2703 (outs rGPR:$Rd),
2704 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
2705 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
2706 Requires<[IsThumb2, HasDSP]>;
2707
2708 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
2709 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
2710 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
2711 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
2712
2713 class T2DualHalfMulAddLong op22_20, bits<4> op7_4, string opc>
2714 : T2FourReg_mac<1, op22_20, op7_4,
2715 (outs rGPR:$Ra, rGPR:$Rd),
2716 (ins rGPR:$Rn, rGPR:$Rm),
2717 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2718 Requires<[IsThumb2, HasDSP]>;
2719
2720 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
2721 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
2722 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
2723 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
2855 def t2SMUADX:T2ThreeReg_mac<
2856 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2857 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2858 Requires<[IsThumb2, HasDSP]> {
2859 let Inst{15-12} = 0b1111;
2860 }
2861 def t2SMUSD: T2ThreeReg_mac<
2862 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2863 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2864 Requires<[IsThumb2, HasDSP]> {
2865 let Inst{15-12} = 0b1111;
2866 }
2867 def t2SMUSDX:T2ThreeReg_mac<
2868 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2869 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2870 Requires<[IsThumb2, HasDSP]> {
2871 let Inst{15-12} = 0b1111;
2872 }
2873 def t2SMLAD : T2FourReg_mac<
2874 0, 0b010, 0b0000, (outs rGPR:$Rd),
2875 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2876 "\t$Rd, $Rn, $Rm, $Ra", []>,
2877 Requires<[IsThumb2, HasDSP]>;
2878 def t2SMLADX : T2FourReg_mac<
2879 0, 0b010, 0b0001, (outs rGPR:$Rd),
2880 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2881 "\t$Rd, $Rn, $Rm, $Ra", []>,
2882 Requires<[IsThumb2, HasDSP]>;
2883 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2884 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2885 "\t$Rd, $Rn, $Rm, $Ra", []>,
2886 Requires<[IsThumb2, HasDSP]>;
2887 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2888 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2889 "\t$Rd, $Rn, $Rm, $Ra", []>,
2890 Requires<[IsThumb2, HasDSP]>;
2891 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2892 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2893 "\t$Ra, $Rd, $Rn, $Rm", []>,
2894 Requires<[IsThumb2, HasDSP]>;
2895 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2896 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2897 "\t$Ra, $Rd, $Rn, $Rm", []>,
2898 Requires<[IsThumb2, HasDSP]>;
2899 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2900 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2901 "\t$Ra, $Rd, $Rn, $Rm", []>,
2902 Requires<[IsThumb2, HasDSP]>;
2903 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2904 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2905 "\t$Ra, $Rd, $Rn, $Rm", []>,
2906 Requires<[IsThumb2, HasDSP]>;
27242907
27252908 //===----------------------------------------------------------------------===//
27262909 // Division Instructions.