llvm.org GIT mirror llvm / 8a3eab9
Remove the local register allocator. Please use the fast allocator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
32 changed file(s) with 16 addition(s) and 1335 deletion(s). Raw diff Collapse all Expand all
15931593 different register allocators:

15941594
15951595
1596
  • Simple — This is a very simple implementation that does not
  • 1597 keep values in registers across instructions. This register allocator
    1598 immediately spills every value right after it is computed, and reloads all
    1599 used operands from memory to temporary registers before each
    1600 instruction.
    1601
    1602
  • Local — This register allocator is an improvement on the
  • 1603 Simple implementation. It allocates registers on a basic block
    1604 level, attempting to keep values in registers and reusing registers as
    1605 appropriate.
    1606
    16071596
  • Linear ScanThe default allocator. This is the
  • 16081597 well-know linear scan register allocator. Whereas the
    16091598 Simple and Local algorithms use a direct mapping
    16101599 implementation technique, the Linear Scan implementation
    16111600 uses a spiller in order to place load and stores.
    1601
    1602
  • Fast — This register allocator is the default for debug
  • 1603 builds. It allocates registers on a basic block level, attempting to keep
    1604 values in registers and reusing registers as appropriate.
    1605
    1606
  • PBQP — A Partitioned Boolean Quadratic Programming (PBQP)
  • 1607 based register allocator. This allocator works by constructing a PBQP
    1608 problem representing the register allocation problem under consideration,
    1609 solving this using a PBQP solver, and mapping the solution back to a
    1610 register assignment.
    1611
    16121612
    16131613
    16141614

    The type of register allocator used in llc can be chosen with the

    16161616
    16171617
    16181618
    
                      
                    
    1619 $ llc -regalloc=simple file.bc -o sp.s;
    1620 $ llc -regalloc=local file.bc -o lc.s;
    16211619 $ llc -regalloc=linearscan file.bc -o ln.s;
    1620 $ llc -regalloc=fast file.bc -o fa.s;
    1621 $ llc -regalloc=pbqp file.bc -o pbqp.s;
    16221622
    16231623
    16241624
    3232
    3333 (void) llvm::createDeadMachineInstructionElimPass();
    3434
    35 (void) llvm::createLocalRegisterAllocator();
    3635 (void) llvm::createFastRegisterAllocator();
    3736 (void) llvm::createLinearScanRegisterAllocator();
    3837 (void) llvm::createPBQPRegisterAllocator();
    8989 ///
    9090 FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);
    9191
    92 /// LocalRegisterAllocation Pass - This pass register allocates the input code
    93 /// a basic block at a time, yielding code better than the simple register
    94 /// allocator, but not as good as a global allocator.
    95 ///
    96 FunctionPass *createLocalRegisterAllocator();
    97
    9892 /// FastRegisterAllocation Pass - This pass register allocates as fast as
    9993 /// possible. It is best suited for debug code where live ranges are short.
    10094 ///
    5151 PseudoSourceValue.cpp
    5252 RegAllocFast.cpp
    5353 RegAllocLinearScan.cpp
    54 RegAllocLocal.cpp
    5554 RegAllocPBQP.cpp
    5655 RegisterCoalescer.cpp
    5756 RegisterScavenging.cpp
    +0
    -1254
    lib/CodeGen/RegAllocLocal.cpp less more
    None //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
    1 //
    2 // The LLVM Compiler Infrastructure
    3 //
    4 // This file is distributed under the University of Illinois Open Source
    5 // License. See LICENSE.TXT for details.
    6 //
    7 //===----------------------------------------------------------------------===//
    8 //
    9 // This register allocator allocates registers to a basic block at a time,
    10 // attempting to keep values in registers and reusing registers as appropriate.
    11 //
    12 //===----------------------------------------------------------------------===//
    13
    14 #define DEBUG_TYPE "regalloc"
    15 #include "llvm/BasicBlock.h"
    16 #include "llvm/CodeGen/MachineFunctionPass.h"
    17 #include "llvm/CodeGen/MachineInstr.h"
    18 #include "llvm/CodeGen/MachineFrameInfo.h"
    19 #include "llvm/CodeGen/MachineRegisterInfo.h"
    20 #include "llvm/CodeGen/Passes.h"
    21 #include "llvm/CodeGen/RegAllocRegistry.h"
    22 #include "llvm/Target/TargetInstrInfo.h"
    23 #include "llvm/Target/TargetMachine.h"
    24 #include "llvm/Support/CommandLine.h"
    25 #include "llvm/Support/Debug.h"
    26 #include "llvm/Support/ErrorHandling.h"
    27 #include "llvm/Support/raw_ostream.h"
    28 #include "llvm/ADT/DenseMap.h"
    29 #include "llvm/ADT/IndexedMap.h"
    30 #include "llvm/ADT/SmallSet.h"
    31 #include "llvm/ADT/SmallVector.h"
    32 #include "llvm/ADT/Statistic.h"
    33 #include "llvm/ADT/STLExtras.h"
    34 #include
    35 using namespace llvm;
    36
    37 STATISTIC(NumStores, "Number of stores added");
    38 STATISTIC(NumLoads , "Number of loads added");
    39 STATISTIC(NumCopies, "Number of copies coalesced");
    40
    41 static RegisterRegAlloc
    42 localRegAlloc("local", "local register allocator",
    43 createLocalRegisterAllocator);
    44
    45 namespace {
    46 class RALocal : public MachineFunctionPass {
    47 public:
    48 static char ID;
    49 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
    50 private:
    51 const TargetMachine *TM;
    52 MachineFunction *MF;
    53 MachineRegisterInfo *MRI;
    54 const TargetRegisterInfo *TRI;
    55 const TargetInstrInfo *TII;
    56
    57 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
    58 // values are spilled.
    59 IndexedMap StackSlotForVirtReg;
    60
    61 // Virt2PhysRegMap - This map contains entries for each virtual register
    62 // that is currently available in a physical register.
    63 IndexedMap Virt2PhysRegMap;
    64
    65 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
    66 return Virt2PhysRegMap[VirtReg];
    67 }
    68
    69 // PhysRegsUsed - This array is effectively a map, containing entries for
    70 // each physical register that currently has a value (ie, it is in
    71 // Virt2PhysRegMap). The value mapped to is the virtual register
    72 // corresponding to the physical register (the inverse of the
    73 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
    74 // because it is used by a future instruction, and to -2 if it is not
    75 // allocatable. If the entry for a physical register is -1, then the
    76 // physical register is "not in the map".
    77 //
    78 std::vector PhysRegsUsed;
    79
    80 // PhysRegsUseOrder - This contains a list of the physical registers that
    81 // currently have a virtual register value in them. This list provides an
    82 // ordering of registers, imposing a reallocation order. This list is only
    83 // used if all registers are allocated and we have to spill one, in which
    84 // case we spill the least recently used register. Entries at the front of
    85 // the list are the least recently used registers, entries at the back are
    86 // the most recently used.
    87 //
    88 std::vector PhysRegsUseOrder;
    89
    90 // Virt2LastUseMap - This maps each virtual register to its last use
    91 // (MachineInstr*, operand index pair).
    92 IndexedMap, VirtReg2IndexFunctor>
    93 Virt2LastUseMap;
    94
    95 std::pair& getVirtRegLastUse(unsigned Reg) {
    96 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    97 return Virt2LastUseMap[Reg];
    98 }
    99
    100 // VirtRegModified - This bitset contains information about which virtual
    101 // registers need to be spilled back to memory when their registers are
    102 // scavenged. If a virtual register has simply been rematerialized, there
    103 // is no reason to spill it to memory when we need the register back.
    104 //
    105 BitVector VirtRegModified;
    106
    107 // UsedInMultipleBlocks - Tracks whether a particular register is used in
    108 // more than one block.
    109 BitVector UsedInMultipleBlocks;
    110
    111 void markVirtRegModified(unsigned Reg, bool Val = true) {
    112 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    113 Reg -= TargetRegisterInfo::FirstVirtualRegister;
    114 if (Val)
    115 VirtRegModified.set(Reg);
    116 else
    117 VirtRegModified.reset(Reg);
    118 }
    119
    120 bool isVirtRegModified(unsigned Reg) const {
    121 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
    122 assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
    123 VirtRegModified.size() && "Illegal virtual register!");
    124 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
    125 }
    126
    127 void AddToPhysRegsUseOrder(unsigned Reg) {
    128 std::vector::iterator It =
    129 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
    130 if (It != PhysRegsUseOrder.end())
    131 PhysRegsUseOrder.erase(It);
    132 PhysRegsUseOrder.push_back(Reg);
    133 }
    134
    135 void MarkPhysRegRecentlyUsed(unsigned Reg) {
    136 if (PhysRegsUseOrder.empty() ||
    137 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
    138
    139 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) {
    140 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
    141 if (!areRegsEqual(Reg, RegMatch)) continue;
    142
    143 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
    144 // Add it to the end of the list
    145 PhysRegsUseOrder.push_back(RegMatch);
    146 if (RegMatch == Reg)
    147 return; // Found an exact match, exit early
    148 }
    149 }
    150
    151 public:
    152 virtual const char *getPassName() const {
    153 return "Local Register Allocator";
    154 }
    155
    156 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
    157 AU.setPreservesCFG();
    158 AU.addRequiredID(PHIEliminationID);
    159 AU.addRequiredID(TwoAddressInstructionPassID);
    160 MachineFunctionPass::getAnalysisUsage(AU);
    161 }
    162
    163 private:
    164 /// runOnMachineFunction - Register allocate the whole function
    165 bool runOnMachineFunction(MachineFunction &Fn);
    166
    167 /// AllocateBasicBlock - Register allocate the specified basic block.
    168 void AllocateBasicBlock(MachineBasicBlock &MBB);
    169
    170
    171 /// areRegsEqual - This method returns true if the specified registers are
    172 /// related to each other. To do this, it checks to see if they are equal
    173 /// or if the first register is in the alias set of the second register.
    174 ///
    175 bool areRegsEqual(unsigned R1, unsigned R2) const {
    176 if (R1 == R2) return true;
    177 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
    178 *AliasSet; ++AliasSet) {
    179 if (*AliasSet == R1) return true;
    180 }
    181 return false;
    182 }
    183
    184 /// getStackSpaceFor - This returns the frame index of the specified virtual
    185 /// register on the stack, allocating space if necessary.
    186 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
    187
    188 /// removePhysReg - This method marks the specified physical register as no
    189 /// longer being in use.
    190 ///
    191 void removePhysReg(unsigned PhysReg);
    192
    193 void storeVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    194 unsigned VirtReg, unsigned PhysReg, bool isKill);
    195
    196 /// spillVirtReg - This method spills the value specified by PhysReg into
    197 /// the virtual register slot specified by VirtReg. It then updates the RA
    198 /// data structures to indicate the fact that PhysReg is now available.
    199 ///
    200 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
    201 unsigned VirtReg, unsigned PhysReg);
    202
    203 /// spillPhysReg - This method spills the specified physical register into
    204 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
    205 /// true, then the request is ignored if the physical register does not
    206 /// contain a virtual register.
    207 ///
    208 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
    209 unsigned PhysReg, bool OnlyVirtRegs = false);
    210
    211 /// assignVirtToPhysReg - This method updates local state so that we know
    212 /// that PhysReg is the proper container for VirtReg now. The physical
    213 /// register must not be used for anything else when this is called.
    214 ///
    215 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
    216
    217 /// isPhysRegAvailable - Return true if the specified physical register is
    218 /// free and available for use. This also includes checking to see if
    219 /// aliased registers are all free...
    220 ///
    221 bool isPhysRegAvailable(unsigned PhysReg) const;
    222
    223 /// getFreeReg - Look to see if there is a free register available in the
    224 /// specified register class. If not, return 0.
    225 ///
    226 unsigned getFreeReg(const TargetRegisterClass *RC);
    227
    228 /// getReg - Find a physical register to hold the specified virtual
    229 /// register. If all compatible physical registers are used, this method
    230 /// spills the last used virtual register to the stack, and uses that
    231 /// register. If NoFree is true, that means the caller knows there isn't
    232 /// a free register, do not call getFreeReg().
    233 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
    234 unsigned VirtReg, bool NoFree = false);
    235
    236 /// reloadVirtReg - This method transforms the specified virtual
    237 /// register use to refer to a physical register. This method may do this
    238 /// in one of several ways: if the register is available in a physical
    239 /// register already, it uses that physical register. If the value is not
    240 /// in a physical register, and if there are physical registers available,
    241 /// it loads it into a register: PhysReg if that is an available physical
    242 /// register, otherwise any physical register of the right class.
    243 /// If register pressure is high, and it is possible, it tries to fold the
    244 /// load of the virtual register into the instruction itself. It avoids
    245 /// doing this if register pressure is low to improve the chance that
    246 /// subsequent instructions can use the reloaded value. This method
    247 /// returns the modified instruction.
    248 ///
    249 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
    250 unsigned OpNum, SmallSet &RRegs,
    251 unsigned PhysReg);
    252
    253 /// ComputeLocalLiveness - Computes liveness of registers within a basic
    254 /// block, setting the killed/dead flags as appropriate.
    255 void ComputeLocalLiveness(MachineBasicBlock& MBB);
    256
    257 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
    258 unsigned PhysReg);
    259 };
    260 char RALocal::ID = 0;
    261 }
    262
    263 /// getStackSpaceFor - This allocates space for the specified virtual register
    264 /// to be held on the stack.
    265 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
    266 // Find the location Reg would belong...
    267 int SS = StackSlotForVirtReg[VirtReg];
    268 if (SS != -1)
    269 return SS; // Already has space allocated?
    270
    271 // Allocate a new stack object for this spill location...
    272 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
    273 RC->getAlignment());
    274
    275 // Assign the slot.
    276 StackSlotForVirtReg[VirtReg] = FrameIdx;
    277 return FrameIdx;
    278 }
    279
    280
    281 /// removePhysReg - This method marks the specified physical register as no
    282 /// longer being in use.
    283 ///
    284 void RALocal::removePhysReg(unsigned PhysReg) {
    285 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
    286
    287 std::vector::iterator It =
    288 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
    289 if (It != PhysRegsUseOrder.end())
    290 PhysRegsUseOrder.erase(It);
    291 }
    292
    293 /// storeVirtReg - Store a virtual register to its assigned stack slot.
    294 void RALocal::storeVirtReg(MachineBasicBlock &MBB,
    295 MachineBasicBlock::iterator I,
    296 unsigned VirtReg, unsigned PhysReg,
    297 bool isKill) {
    298 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
    299 int FrameIndex = getStackSpaceFor(VirtReg, RC);
    300 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
    301 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
    302 ++NumStores; // Update statistics
    303
    304 // Mark the spill instruction as last use if we're not killing the register.
    305 if (!isKill) {
    306 MachineInstr *Spill = llvm::prior(I);
    307 int OpNum = Spill->findRegisterUseOperandIdx(PhysReg);
    308 if (OpNum < 0)
    309 getVirtRegLastUse(VirtReg) = std::make_pair((MachineInstr*)0, 0);
    310 else
    311 getVirtRegLastUse(VirtReg) = std::make_pair(Spill, OpNum);
    312 }
    313 }
    314
    315 /// spillVirtReg - This method spills the value specified by PhysReg into the
    316 /// virtual register slot specified by VirtReg. It then updates the RA data
    317 /// structures to indicate the fact that PhysReg is now available.
    318 ///
    319 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
    320 MachineBasicBlock::iterator I,
    321 unsigned VirtReg, unsigned PhysReg) {
    322 assert(VirtReg && "Spilling a physical register is illegal!"
    323 " Must not have appropriate kill for the register or use exists beyond"
    324 " the intended one.");
    325 DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
    326 << " containing %reg" << VirtReg);
    327
    328 if (!isVirtRegModified(VirtReg)) {
    329 DEBUG(dbgs() << " which has not been modified, so no store necessary!");
    330 std::pair &LastUse = getVirtRegLastUse(VirtReg);
    331 if (LastUse.first)
    332 LastUse.first->getOperand(LastUse.second).setIsKill();
    333 } else {
    334 // Otherwise, there is a virtual register corresponding to this physical
    335 // register. We only need to spill it into its stack slot if it has been
    336 // modified.
    337 // If the instruction reads the register that's spilled, (e.g. this can
    338 // happen if it is a move to a physical register), then the spill
    339 // instruction is not a kill.
    340 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
    341 storeVirtReg(MBB, I, VirtReg, PhysReg, isKill);
    342 }
    343
    344 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
    345
    346 DEBUG(dbgs() << '\n');
    347 removePhysReg(PhysReg);
    348 }
    349
    350
    351 /// spillPhysReg - This method spills the specified physical register into the
    352 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
    353 /// then the request is ignored if the physical register does not contain a
    354 /// virtual register.
    355 ///
    356 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
    357 unsigned PhysReg, bool OnlyVirtRegs) {
    358 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
    359 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
    360 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
    361 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
    362 return;
    363 }
    364
    365 // If the selected register aliases any other registers, we must make
    366 // sure that one of the aliases isn't alive.
    367 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    368 *AliasSet; ++AliasSet) {
    369 if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register.
    370 PhysRegsUsed[*AliasSet] == -2) // If allocatable.
    371 continue;
    372
    373 if (PhysRegsUsed[*AliasSet])
    374 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
    375 }
    376 }
    377
    378
    379 /// assignVirtToPhysReg - This method updates local state so that we know
    380 /// that PhysReg is the proper container for VirtReg now. The physical
    381 /// register must not be used for anything else when this is called.
    382 ///
    383 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
    384 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
    385 // Update information to note the fact that this register was just used, and
    386 // it holds VirtReg.
    387 PhysRegsUsed[PhysReg] = VirtReg;
    388 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
    389 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
    390 }
    391
    392
    393 /// isPhysRegAvailable - Return true if the specified physical register is free
    394 /// and available for use. This also includes checking to see if aliased
    395 /// registers are all free...
    396 ///
    397 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
    398 if (PhysRegsUsed[PhysReg] != -1) return false;
    399
    400 // If the selected register aliases any other allocated registers, it is
    401 // not free!
    402 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    403 *AliasSet; ++AliasSet)
    404 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
    405 return false; // Can't use this reg then.
    406 return true;
    407 }
    408
    409
    410 /// getFreeReg - Look to see if there is a free register available in the
    411 /// specified register class. If not, return 0.
    412 ///
    413 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
    414 // Get iterators defining the range of registers that are valid to allocate in
    415 // this class, which also specifies the preferred allocation order.
    416 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
    417 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
    418
    419 for (; RI != RE; ++RI)
    420 if (isPhysRegAvailable(*RI)) { // Is reg unused?
    421 assert(*RI != 0 && "Cannot use register!");
    422 return *RI; // Found an unused register!
    423 }
    424 return 0;
    425 }
    426
    427
    428 /// getReg - Find a physical register to hold the specified virtual
    429 /// register. If all compatible physical registers are used, this method spills
    430 /// the last used virtual register to the stack, and uses that register.
    431 ///
    432 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
    433 unsigned VirtReg, bool NoFree) {
    434 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
    435
    436 // First check to see if we have a free register of the requested type...
    437 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
    438
    439 if (PhysReg != 0) {
    440 // Assign the register.
    441 assignVirtToPhysReg(VirtReg, PhysReg);
    442 return PhysReg;
    443 }
    444
    445 // If we didn't find an unused register, scavenge one now!
    446 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
    447
    448 // Loop over all of the preallocated registers from the least recently used
    449 // to the most recently used. When we find one that is capable of holding
    450 // our register, use it.
    451 for (unsigned i = 0; PhysReg == 0; ++i) {
    452 assert(i != PhysRegsUseOrder.size() &&
    453 "Couldn't find a register of the appropriate class!");
    454
    455 unsigned R = PhysRegsUseOrder[i];
    456
    457 // We can only use this register if it holds a virtual register (ie, it
    458 // can be spilled). Do not use it if it is an explicitly allocated
    459 // physical register!
    460 assert(PhysRegsUsed[R] != -1 &&
    461 "PhysReg in PhysRegsUseOrder, but is not allocated?");
    462 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
    463 // If the current register is compatible, use it.
    464 if (RC->contains(R)) {
    465 PhysReg = R;
    466 break;
    467 }
    468
    469 // If one of the registers aliased to the current register is
    470 // compatible, use it.
    471 for (const unsigned *AliasIt = TRI->getAliasSet(R);
    472 *AliasIt; ++AliasIt) {
    473 if (!RC->contains(*AliasIt)) continue;
    474
    475 // If this is pinned down for some reason, don't use it. For
    476 // example, if CL is pinned, and we run across CH, don't use
    477 // CH as justification for using scavenging ECX (which will
    478 // fail).
    479 if (PhysRegsUsed[*AliasIt] == 0) continue;
    480
    481 // Make sure the register is allocatable. Don't allocate SIL on
    482 // x86-32.
    483 if (PhysRegsUsed[*AliasIt] == -2) continue;
    484
    485 PhysReg = *AliasIt; // Take an aliased register
    486 break;
    487 }
    488 }
    489 }
    490
    491 assert(PhysReg && "Physical register not assigned!?!?");
    492
    493 // At this point PhysRegsUseOrder[i] is the least recently used register of
    494 // compatible register class. Spill it to memory and reap its remains.
    495 spillPhysReg(MBB, I, PhysReg);
    496
    497 // Now that we know which register we need to assign this to, do it now!
    498 assignVirtToPhysReg(VirtReg, PhysReg);
    499 return PhysReg;
    500 }
    501
    502
    503 /// reloadVirtReg - This method transforms the specified virtual
    504 /// register use to refer to a physical register. This method may do this in
    505 /// one of several ways: if the register is available in a physical register
    506 /// already, it uses that physical register. If the value is not in a physical
    507 /// register, and if there are physical registers available, it loads it into a
    508 /// register: PhysReg if that is an available physical register, otherwise any
    509 /// register. If register pressure is high, and it is possible, it tries to
    510 /// fold the load of the virtual register into the instruction itself. It
    511 /// avoids doing this if register pressure is low to improve the chance that
    512 /// subsequent instructions can use the reloaded value. This method returns
    513 /// the modified instruction.
    514 ///
    515 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
    516 unsigned OpNum,
    517 SmallSet &ReloadedRegs,
    518 unsigned PhysReg) {
    519 unsigned VirtReg = MI->getOperand(OpNum).getReg();
    520 unsigned SubIdx = MI->getOperand(OpNum).getSubReg();
    521
    522 // If the virtual register is already available, just update the instruction
    523 // and return.
    524 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
    525 if (SubIdx) {
    526 PR = TRI->getSubReg(PR, SubIdx);
    527 MI->getOperand(OpNum).setSubReg(0);
    528 }
    529 MI->getOperand(OpNum).setReg(PR); // Assign the input register
    530 if (!MI->isDebugValue()) {
    531 // Do not do these for DBG_VALUE as they can affect codegen.
    532 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
    533 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
    534 }
    535 return MI;
    536 }
    537
    538 // Otherwise, we need to fold it into the current instruction, or reload it.
    539 // If we have registers available to hold the value, use them.
    540 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
    541 // If we already have a PhysReg (this happens when the instruction is a
    542 // reg-to-reg copy with a PhysReg destination) use that.
    543 if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
    544 !isPhysRegAvailable(PhysReg))
    545 PhysReg = getFreeReg(RC);
    546 int FrameIndex = getStackSpaceFor(VirtReg, RC);
    547
    548 if (PhysReg) { // Register is available, allocate it!
    549 assignVirtToPhysReg(VirtReg, PhysReg);
    550 } else { // No registers available.
    551 // Force some poor hapless value out of the register file to
    552 // make room for the new register, and reload it.
    553 PhysReg = getReg(MBB, MI, VirtReg, true);
    554 }
    555
    556 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
    557
    558 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
    559 << TRI->getName(PhysReg) << "\n");
    560
    561 // Add move instruction(s)
    562 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
    563 ++NumLoads; // Update statistics
    564
    565 MF->getRegInfo().setPhysRegUsed(PhysReg);
    566 // Assign the input register.
    567 if (SubIdx) {
    568 MI->getOperand(OpNum).setSubReg(0);
    569 MI->getOperand(OpNum).setReg(TRI->getSubReg(PhysReg, SubIdx));
    570 } else
    571 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
    572 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
    573
    574 if (!ReloadedRegs.insert(PhysReg)) {
    575 std::string msg;
    576 raw_string_ostream Msg(msg);
    577 Msg << "Ran out of registers during register allocation!";
    578 if (MI->isInlineAsm()) {
    579 Msg << "\nPlease check your inline asm statement for invalid "
    580 << "constraints:\n";
    581 MI->print(Msg, TM);
    582 }
    583 report_fatal_error(Msg.str());
    584 }
    585 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
    586 *SubRegs; ++SubRegs) {
    587 if (ReloadedRegs.insert(*SubRegs)) continue;
    588
    589 std::string msg;
    590 raw_string_ostream Msg(msg);
    591 Msg << "Ran out of registers during register allocation!";
    592 if (MI->isInlineAsm()) {
    593 Msg << "\nPlease check your inline asm statement for invalid "
    594 << "constraints:\n";
    595 MI->print(Msg, TM);
    596 }
    597 report_fatal_error(Msg.str());
    598 }
    599
    600 return MI;
    601 }
    602
    603 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
    604 /// read/mod/write register, i.e. update partial register.
    605 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
    606 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    607 MachineOperand &MO = MI->getOperand(i);
    608 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
    609 MO.isDef() && !MO.isDead())
    610 return true;
    611 }
    612 return false;
    613 }
    614
    615 /// isReadModWriteImplicitDef - True if this is an implicit def for a
    616 /// read/mod/write register, i.e. update partial register.
    617 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
    618 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    619 MachineOperand &MO = MI->getOperand(i);
    620 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
    621 !MO.isDef() && MO.isKill())
    622 return true;
    623 }
    624 return false;
    625 }
    626
    627 // precedes - Helper function to determine with MachineInstr A
    628 // precedes MachineInstr B within the same MBB.
    629 static bool precedes(MachineBasicBlock::iterator A,
    630 MachineBasicBlock::iterator B) {
    631 if (A == B)
    632 return false;
    633
    634 MachineBasicBlock::iterator I = A->getParent()->begin();
    635 while (I != A->getParent()->end()) {
    636 if (I == A)
    637 return true;
    638 else if (I == B)
    639 return false;
    640
    641 ++I;
    642 }
    643
    644 return false;
    645 }
    646
    647 /// ComputeLocalLiveness - Computes liveness of registers within a basic
    648 /// block, setting the killed/dead flags as appropriate.
    649 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
    650 // Keep track of the most recently seen previous use or def of each reg,
    651 // so that we can update them with dead/kill markers.
    652 DenseMap > LastUseDef;
    653 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
    654 I != E; ++I) {
    655 if (I->isDebugValue())
    656 continue;
    657
    658 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
    659 MachineOperand &MO = I->getOperand(i);
    660 // Uses don't trigger any flags, but we need to save
    661 // them for later. Also, we have to process these
    662 // _before_ processing the defs, since an instr
    663 // uses regs before it defs them.
    664 if (!MO.isReg() || !MO.getReg() || !MO.isUse())
    665 continue;
    666
    667 // Ignore helpful kill flags from earlier passes.
    668 MO.setIsKill(false);
    669
    670 LastUseDef[MO.getReg()] = std::make_pair(I, i);
    671
    672 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
    673
    674 const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
    675 if (Aliases == 0)
    676 continue;
    677
    678 while (*Aliases) {
    679 DenseMap >::iterator
    680 alias = LastUseDef.find(*Aliases);
    681
    682 if (alias != LastUseDef.end() && alias->second.first != I)
    683 LastUseDef[*Aliases] = std::make_pair(I, i);
    684
    685 ++Aliases;
    686 }
    687 }
    688
    689 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
    690 MachineOperand &MO = I->getOperand(i);
    691 // Defs others than 2-addr redefs _do_ trigger flag changes:
    692 // - A def followed by a def is dead
    693 // - A use followed by a def is a kill
    694 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
    695
    696 unsigned SubIdx = MO.getSubReg();
    697 DenseMap >::iterator
    698 last = LastUseDef.find(MO.getReg());
    699 if (last != LastUseDef.end()) {
    700 // Check if this is a two address instruction. If so, then
    701 // the def does not kill the use.
    702 if (last->second.first == I && I->isRegTiedToUseOperand(i))
    703 continue;
    704
    705 MachineOperand &lastUD =
    706 last->second.first->getOperand(last->second.second);
    707 if (SubIdx && lastUD.getSubReg() != SubIdx)
    708 // Partial re-def, the last def is not dead.
    709 // %reg1024:5 =
    710 // %reg1024:6 =
    711 // or
    712 // %reg1024:5 = op %reg1024, 5
    713 continue;
    714
    715 if (lastUD.isDef())
    716 lastUD.setIsDead(true);
    717 else
    718 lastUD.setIsKill(true);
    719 }
    720
    721 LastUseDef[MO.getReg()] = std::make_pair(I, i);
    722 }
    723 }
    724
    725 // Live-out (of the function) registers contain return values of the function,
    726 // so we need to make sure they are alive at return time.
    727 MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
    728 bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
    729
    730 if (BBEndsInReturn)
    731 for (MachineRegisterInfo::liveout_iterator
    732 I = MF->getRegInfo().liveout_begin(),
    733 E = MF->getRegInfo().liveout_end(); I != E; ++I)
    734 if (!Ret->readsRegister(*I)) {
    735 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
    736 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
    737 }
    738
    739 // Finally, loop over the final use/def of each reg
    740 // in the block and determine if it is dead.
    741 for (DenseMap >::iterator
    742 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
    743 MachineInstr *MI = I->second.first;
    744 unsigned idx = I->second.second;
    745 MachineOperand &MO = MI->getOperand(idx);
    746
    747 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
    748
    749 // A crude approximation of "live-out" calculation
    750 bool usedOutsideBlock = isPhysReg ? false :
    751 UsedInMultipleBlocks.test(MO.getReg() -
    752 TargetRegisterInfo::FirstVirtualRegister);
    753
    754 // If the machine BB ends in a return instruction, then the value isn't used
    755 // outside of the BB.
    756 if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
    757 // DBG_VALUE complicates this: if the only refs of a register outside
    758 // this block are DBG_VALUE, we can't keep the reg live just for that,
    759 // as it will cause the reg to be spilled at the end of this block when
    760 // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
    761 // happens.
    762 bool UsedByDebugValueOnly = false;
    763 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
    764 UE = MRI->reg_end(); UI != UE; ++UI) {
    765 // Two cases:
    766 // - used in another block
    767 // - used in the same block before it is defined (loop)
    768 if (UI->getParent() == &MBB &&
    769 !(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
    770 continue;
    771
    772 if (UI->isDebugValue()) {
    773 UsedByDebugValueOnly = true;
    774 continue;
    775 }
    776
    777 // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
    778 UsedInMultipleBlocks.set(MO.getReg() -
    779 TargetRegisterInfo::FirstVirtualRegister);
    780 usedOutsideBlock = true;
    781 UsedByDebugValueOnly = false;
    782 break;
    783 }
    784
    785 if (UsedByDebugValueOnly)
    786 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
    787 UE = MRI->reg_end(); UI != UE; ++UI)
    788 if (UI->isDebugValue() &&
    789 (UI->getParent() != &MBB ||
    790 (MO.isDef() && precedes(&*UI, MI))))
    791 UI.getOperand().setReg(0U);
    792 }
    793
    794 // Physical registers and those that are not live-out of the block are
    795 // killed/dead at their last use/def within this block.
    796 if (isPhysReg || !usedOutsideBlock || BBEndsInReturn) {
    797 if (MO.isUse()) {
    798 // Don't mark uses that are tied to defs as kills.
    799 if (!MI->isRegTiedToDefOperand(idx))
    800 MO.setIsKill(true);
    801 } else {
    802 MO.setIsDead(true);
    803 }
    804 }
    805 }
    806 }
    807
    808 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
    809 // loop over each instruction
    810 MachineBasicBlock::iterator MII = MBB.begin();
    811
    812 DEBUG({
    813 const BasicBlock *LBB = MBB.getBasicBlock();
    814 if (LBB)
    815 dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
    816 });
    817
    818 // Add live-in registers as active.
    819 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
    820 E = MBB.livein_end(); I != E; ++I) {
    821 unsigned Reg = *I;
    822 MF->getRegInfo().setPhysRegUsed(Reg);
    823 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    824 AddToPhysRegsUseOrder(Reg);
    825 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
    826 *SubRegs; ++SubRegs) {
    827 if (PhysRegsUsed[*SubRegs] == -2) continue;
    828
    829 AddToPhysRegsUseOrder(*SubRegs);
    830 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
    831 MF->getRegInfo().setPhysRegUsed(*SubRegs);
    832 }
    833 }
    834
    835 ComputeLocalLiveness(MBB);
    836
    837 // Otherwise, sequentially allocate each instruction in the MBB.
    838 while (MII != MBB.end()) {
    839 MachineInstr *MI = MII++;
    840 const TargetInstrDesc &TID = MI->getDesc();
    841 DEBUG({
    842 dbgs() << "\nStarting RegAlloc of: " << *MI;
    843 dbgs() << " Regs have values: ";
    844 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
    845 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
    846 if (PhysRegsUsed[i] && isVirtRegModified(PhysRegsUsed[i]))
    847 dbgs() << "*";
    848 dbgs() << "[" << TRI->getName(i)
    849 << ",%reg" << PhysRegsUsed[i] << "] ";
    850 }
    851 dbgs() << '\n';
    852 });
    853
    854 // Determine whether this is a copy instruction. The cases where the
    855 // source or destination are phys regs are handled specially.
    856 unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
    857 unsigned SrcCopyPhysReg = 0U;
    858 bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
    859 SrcCopySubReg, DstCopySubReg) &&
    860 SrcCopySubReg == DstCopySubReg;
    861 if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
    862 SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
    863
    864 // Loop over the implicit uses, making sure that they are at the head of the
    865 // use order list, so they don't get reallocated.
    866 if (TID.ImplicitUses) {
    867 for (const unsigned *ImplicitUses = TID.ImplicitUses;
    868 *ImplicitUses; ++ImplicitUses)
    869 MarkPhysRegRecentlyUsed(*ImplicitUses);
    870 }
    871
    872 SmallVector Kills;
    873 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    874 MachineOperand &MO = MI->getOperand(i);
    875 if (!MO.isReg() || !MO.isKill()) continue;
    876
    877 if (!MO.isImplicit())
    878 Kills.push_back(MO.getReg());
    879 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
    880 // These are extra physical register kills when a sub-register
    881 // is defined (def of a sub-register is a read/mod/write of the
    882 // larger registers). Ignore.
    883 Kills.push_back(MO.getReg());
    884 }
    885
    886 // If any physical regs are earlyclobber, spill any value they might
    887 // have in them, then mark them unallocatable.
    888 // If any virtual regs are earlyclobber, allocate them now (before
    889 // freeing inputs that are killed).
    890 if (MI->isInlineAsm()) {
    891 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    892 MachineOperand &MO = MI->getOperand(i);
    893 if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
    894 !MO.getReg())
    895 continue;
    896
    897 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    898 unsigned DestVirtReg = MO.getReg();
    899 unsigned DestPhysReg;
    900
    901 // If DestVirtReg already has a value, use it.
    902 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
    903 DestPhysReg = getReg(MBB, MI, DestVirtReg);
    904 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
    905 markVirtRegModified(DestVirtReg);
    906 getVirtRegLastUse(DestVirtReg) =
    907 std::make_pair((MachineInstr*)0, 0);
    908 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
    909 << " to %reg" << DestVirtReg << "\n");
    910 if (unsigned DestSubIdx = MO.getSubReg()) {
    911 MO.setSubReg(0);
    912 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
    913 }
    914 MO.setReg(DestPhysReg); // Assign the earlyclobber register
    915 } else {
    916 unsigned Reg = MO.getReg();
    917 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
    918 // These are extra physical register defs when a sub-register
    919 // is defined (def of a sub-register is a read/mod/write of the
    920 // larger registers). Ignore.
    921 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
    922
    923 MF->getRegInfo().setPhysRegUsed(Reg);
    924 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
    925 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    926 AddToPhysRegsUseOrder(Reg);
    927
    928 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
    929 *SubRegs; ++SubRegs) {
    930 if (PhysRegsUsed[*SubRegs] == -2) continue;
    931 MF->getRegInfo().setPhysRegUsed(*SubRegs);
    932 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
    933 AddToPhysRegsUseOrder(*SubRegs);
    934 }
    935 }
    936 }
    937 }
    938
    939 // If a DBG_VALUE says something is located in a spilled register,
    940 // change the DBG_VALUE to be undef, which prevents the register
    941 // from being reloaded here. Doing that would change the generated
    942 // code, unless another use immediately follows this instruction.
    943 if (MI->isDebugValue() &&
    944 MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
    945 unsigned VirtReg = MI->getOperand(0).getReg();
    946 if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
    947 !getVirt2PhysRegMapSlot(VirtReg))
    948 MI->getOperand(0).setReg(0U);
    949 }
    950
    951 // Get the used operands into registers. This has the potential to spill
    952 // incoming values if we are out of registers. Note that we completely
    953 // ignore physical register uses here. We assume that if an explicit
    954 // physical register is referenced by the instruction, that it is guaranteed
    955 // to be live-in, or the input is badly hosed.
    956 //
    957 SmallSet ReloadedRegs;
    958 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
    959 MachineOperand &MO = MI->getOperand(i);
    960 // here we are looking for only used operands (never def&use)
    961 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
    962 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    963 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
    964 isCopy ? DstCopyReg : 0);
    965 }
    966
    967 // If this instruction is the last user of this register, kill the
    968 // value, freeing the register being used, so it doesn't need to be
    969 // spilled to memory.
    970 //
    971 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
    972 unsigned VirtReg = Kills[i];
    973 unsigned PhysReg = VirtReg;
    974 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    975 // If the virtual register was never materialized into a register, it
    976 // might not be in the map, but it won't hurt to zero it out anyway.
    977 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    978 PhysReg = PhysRegSlot;
    979 PhysRegSlot = 0;
    980 } else if (PhysRegsUsed[PhysReg] == -2) {
    981 // Unallocatable register dead, ignore.
    982 continue;
    983 } else {
    984 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
    985 "Silently clearing a virtual register?");
    986 }
    987
    988 if (!PhysReg) continue;
    989
    990 DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
    991 << "[%reg" << VirtReg <<"], removing it from live set\n");
    992 removePhysReg(PhysReg);
    993 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
    994 *SubRegs; ++SubRegs) {
    995 if (PhysRegsUsed[*SubRegs] != -2) {
    996 DEBUG(dbgs() << " Last use of "
    997 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
    998 <<"], removing it from live set\n");
    999 removePhysReg(*SubRegs);
    1000 }
    1001 }
    1002 }
    1003
    1004 // Loop over all of the operands of the instruction, spilling registers that
    1005 // are defined, and marking explicit destinations in the PhysRegsUsed map.
    1006 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    1007 MachineOperand &MO = MI->getOperand(i);
    1008 if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
    1009 MO.isEarlyClobber() ||
    1010 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
    1011 continue;
    1012
    1013 unsigned Reg = MO.getReg();
    1014 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
    1015 // These are extra physical register defs when a sub-register
    1016 // is defined (def of a sub-register is a read/mod/write of the
    1017 // larger registers). Ignore.
    1018 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
    1019
    1020 MF->getRegInfo().setPhysRegUsed(Reg);
    1021 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
    1022 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    1023 AddToPhysRegsUseOrder(Reg);
    1024
    1025 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
    1026 *SubRegs; ++SubRegs) {
    1027 if (PhysRegsUsed[*SubRegs] == -2) continue;
    1028
    1029 MF->getRegInfo().setPhysRegUsed(*SubRegs);
    1030 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
    1031 AddToPhysRegsUseOrder(*SubRegs);
    1032 }
    1033 }
    1034
    1035 // Loop over the implicit defs, spilling them as well.
    1036 if (TID.ImplicitDefs) {
    1037 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
    1038 *ImplicitDefs; ++ImplicitDefs) {
    1039 unsigned Reg = *ImplicitDefs;
    1040 if (PhysRegsUsed[Reg] != -2) {
    1041 spillPhysReg(MBB, MI, Reg, true);
    1042 AddToPhysRegsUseOrder(Reg);
    1043 PhysRegsUsed[Reg] = 0; // It is free and reserved now
    1044 }
    1045 MF->getRegInfo().setPhysRegUsed(Reg);
    1046 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
    1047 *SubRegs; ++SubRegs) {
    1048 if (PhysRegsUsed[*SubRegs] == -2) continue;
    1049
    1050 AddToPhysRegsUseOrder(*SubRegs);
    1051 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
    1052 MF->getRegInfo().setPhysRegUsed(*SubRegs);
    1053 }
    1054 }
    1055 }
    1056
    1057 SmallVector DeadDefs;
    1058 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    1059 MachineOperand &MO = MI->getOperand(i);
    1060 if (MO.isReg() && MO.isDead())
    1061 DeadDefs.push_back(MO.getReg());
    1062 }
    1063
    1064 // Okay, we have allocated all of the source operands and spilled any values
    1065 // that would be destroyed by defs of this instruction. Loop over the
    1066 // explicit defs and assign them to a register, spilling incoming values if
    1067 // we need to scavenge a register.
    1068 //
    1069 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    1070 MachineOperand &MO = MI->getOperand(i);
    1071 if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
    1072 MO.isEarlyClobber() ||
    1073 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    1074 continue;
    1075
    1076 unsigned DestVirtReg = MO.getReg();
    1077 unsigned DestPhysReg;
    1078
    1079 // If DestVirtReg already has a value, use it.
    1080 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
    1081 // If this is a copy try to reuse the input as the output;
    1082 // that will make the copy go away.
    1083 // If this is a copy, the source reg is a phys reg, and
    1084 // that reg is available, use that phys reg for DestPhysReg.
    1085 // If this is a copy, the source reg is a virtual reg, and
    1086 // the phys reg that was assigned to that virtual reg is now
    1087 // available, use that phys reg for DestPhysReg. (If it's now
    1088 // available that means this was the last use of the source.)
    1089 if (isCopy &&
    1090 TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
    1091 isPhysRegAvailable(SrcCopyReg)) {
    1092 DestPhysReg = SrcCopyReg;
    1093 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
    1094 } else if (isCopy &&
    1095 TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
    1096 SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
    1097 MF->getRegInfo().getRegClass(DestVirtReg)->
    1098 contains(SrcCopyPhysReg)) {
    1099 DestPhysReg = SrcCopyPhysReg;
    1100 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
    1101 } else
    1102 DestPhysReg = getReg(MBB, MI, DestVirtReg);
    1103 }
    1104 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
    1105 markVirtRegModified(DestVirtReg);
    1106 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
    1107 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
    1108 << " to %reg" << DestVirtReg << "\n");
    1109
    1110 if (unsigned DestSubIdx = MO.getSubReg()) {
    1111 MO.setSubReg(0);
    1112 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
    1113 }
    1114 MO.setReg(DestPhysReg); // Assign the output register
    1115 }
    1116
    1117 // If this instruction defines any registers that are immediately dead,
    1118 // kill them now.
    1119 //
    1120 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
    1121 unsigned VirtReg = DeadDefs[i];
    1122 unsigned PhysReg = VirtReg;
    1123 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
    1124 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
    1125 PhysReg = PhysRegSlot;
    1126 assert(PhysReg != 0);
    1127 PhysRegSlot = 0;
    1128 } else if (PhysRegsUsed[PhysReg] == -2) {
    1129 // Unallocatable register dead, ignore.
    1130 continue;
    1131 } else if (!PhysReg)
    1132 continue;
    1133
    1134 DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
    1135 << " [%reg" << VirtReg
    1136 << "] is never used, removing it from live set\n");
    1137 removePhysReg(PhysReg);
    1138 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
    1139 *AliasSet; ++AliasSet) {
    1140 if (PhysRegsUsed[*AliasSet] != -2) {
    1141 DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
    1142 << " [%reg" << *AliasSet
    1143 << "] is never used, removing it from live set\n");
    1144 removePhysReg(*AliasSet);
    1145 }
    1146 }
    1147 }
    1148
    1149 // If this instruction is a call, make sure there are no dirty registers. The
    1150 // call might throw an exception, and the landing pad expects to find all
    1151 // registers in stack slots.
    1152 if (TID.isCall())
    1153 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
    1154 if (PhysRegsUsed[i] <= 0) continue;
    1155 unsigned VirtReg = PhysRegsUsed[i];
    1156 if (!isVirtRegModified(VirtReg)) continue;
    1157 DEBUG(dbgs() << " Storing dirty %reg" << VirtReg);
    1158 storeVirtReg(MBB, MI, VirtReg, i, false);
    1159 markVirtRegModified(VirtReg, false);
    1160 DEBUG(dbgs() << " because the call might throw\n");
    1161 }
    1162
    1163 // Finally, if this is a noop copy instruction, zap it. (Except that if
    1164 // the copy is dead, it must be kept to avoid messing up liveness info for
    1165 // the register scavenger. See pr4100.)
    1166 if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
    1167 SrcCopySubReg, DstCopySubReg) &&
    1168 SrcCopyReg == DstCopyReg && SrcCopySubReg == DstCopySubReg &&
    1169 DeadDefs.empty()) {
    1170 ++NumCopies;
    1171 MBB.erase(MI);
    1172 }
    1173 }
    1174
    1175 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
    1176
    1177 // Spill all physical registers holding virtual registers now.
    1178 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
    1179 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
    1180 if (unsigned VirtReg = PhysRegsUsed[i])
    1181 spillVirtReg(MBB, MI, VirtReg, i);
    1182 else
    1183 removePhysReg(i);
    1184 }
    1185
    1186 #if 0
    1187 // This checking code is very expensive.
    1188 bool AllOk = true;
    1189 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
    1190 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
    1191 if (unsigned PR = Virt2PhysRegMap[i]) {
    1192 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
    1193 AllOk = false;
    1194 }
    1195 assert(AllOk && "Virtual registers still in phys regs?");
    1196 #endif
    1197
    1198 // Clear any physical register which appear live at the end of the basic
    1199 // block, but which do not hold any virtual registers. e.g., the stack
    1200 // pointer.
    1201 PhysRegsUseOrder.clear();
    1202 }
    1203
    1204 /// runOnMachineFunction - Register allocate the whole function
    1205 ///
    1206 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
    1207 DEBUG(dbgs() << "Machine Function\n");
    1208 MF = &Fn;
    1209 MRI = &Fn.getRegInfo();
    1210 TM = &Fn.getTarget();
    1211 TRI = TM->getRegisterInfo();
    1212 TII = TM->getInstrInfo();
    1213
    1214 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
    1215
    1216 // At various places we want to efficiently check to see whether a register
    1217 // is allocatable. To handle this, we mark all unallocatable registers as
    1218 // being pinned down, permanently.
    1219 {
    1220 BitVector Allocable = TRI->getAllocatableSet(Fn);
    1221 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
    1222 if (!Allocable[i])
    1223 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
    1224 }
    1225
    1226 // initialize the virtual->physical register map to have a 'null'
    1227 // mapping for all virtual registers
    1228 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
    1229 StackSlotForVirtReg.grow(LastVirtReg);
    1230 Virt2PhysRegMap.grow(LastVirtReg);
    1231 Virt2LastUseMap.grow(LastVirtReg);
    1232 VirtRegModified.resize(LastVirtReg+1 -
    1233 TargetRegisterInfo::FirstVirtualRegister);
    1234 UsedInMultipleBlocks.resize(LastVirtReg+1 -
    1235 TargetRegisterInfo::FirstVirtualRegister);
    1236
    1237 // Loop over all of the basic blocks, eliminating virtual register references
    1238 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
    1239 MBB != MBBe; ++MBB)
    1240 AllocateBasicBlock(*MBB);
    1241
    1242 StackSlotForVirtReg.clear();
    1243 PhysRegsUsed.clear();
    1244 VirtRegModified.clear();
    1245 UsedInMultipleBlocks.clear();
    1246 Virt2PhysRegMap.clear();
    1247 Virt2LastUseMap.clear();
    1248 return true;
    1249 }
    1250
    1251 FunctionPass *llvm::createLocalRegisterAllocator() {
    1252 return new RALocal();
    1253 }
    None ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local
    1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast
    21 ; PR1925
    32
    None ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local
    1 ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast
    21 ; PR1925
    32
    None ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
    1 ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast
    21 ; PR4100
    32 @.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
    None ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local
    1 ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast
    21 ; rdar://problem/7948106
    32 ;; This test would spill %R4 before the call to zz, but it forgot to move the
    None ; RUN: llc < %s -regalloc=local
    1 ; RUN: llc < %s -regalloc=fast
    21
    32 %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
    0 ; RUN: llc < %s | FileCheck %s
    1 ; RUN: llc < %s -regalloc=local | FileCheck %s
    21 ; RUN: llc < %s -regalloc=fast | FileCheck %s
    32 ; The first argument of subfc must not be the same as any other register.
    43
    None ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
    1 ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic
    21
    32 %struct.NSError = type opaque
    None ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
    1 ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic
    21
    32 %struct.NSError = type opaque
    None ; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local
    1 ; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=fast
    21
    32 define i32 @bork(i64 %foo, i64 %bar) {
    None ; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
    1 ; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o -
    21 ; PR1638
    32
    None ; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s
    1 ; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s
    21
    32 target triple = "thumbv6-apple-darwin10"
    None ; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local
    1 ; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=fast
    21
    32 define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) {
    None ; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi
    1 ; RUN: llc < %s -regalloc=fast -march=x86 -mattr=+mmx | grep esi
    21 ; PR2082
    32 ; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of
    0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin
    1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
    21 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=fast
    32 ; PR5534
    43
    None ; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local
    1 ; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=fast
    21
    32 @_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1]
    0 ; RUN: llc < %s -march=x86 | FileCheck %s
    1 ; RUN: llc < %s -march=x86 -regalloc=local | FileCheck %s
    21 ; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s
    32
    43 ; %0 must not be put in EAX or EDX.
    0 ; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
    1 ; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
    21 ; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
    32
    43 ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
    None ; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
    1 ; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim
    21 ; rdar://6538384
    32
    None ; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
    1 ; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil
    21 ; rdar://6787136
    32
    None ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
    1 ; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
    2 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
    0 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -relocation-model=pic > %t2
    31 ; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
    42 ; PR4004
    53
    None ; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s
    1 ; RUN: llc < %s -O0 -regalloc=fast -relocation-model=pic -disable-fp-elim | FileCheck %s
    21 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
    32 target triple = "i386-apple-darwin10.0.0"
    None ; RUN-XFAIL: llc < %s -O0 -regalloc=local | FileCheck %s
    1 ; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s
    21 ; PR6520
    32
    None ; RUN: llc -regalloc=local %s -o %t
    1 ; RUN: llc -regalloc=fast %s -o %t
    21 ; PR7066
    32
    None ; RUN: llc %s -O0 -fast-isel -regalloc=local -o -
    1 ; RUN: llc %s -O0 -fast-isel -regalloc=fast -o -
    21 ; PR4767
    32
    None ; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10
    1 ; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10
    21 ;
    32
    +0
    -31
    test/CodeGen/X86/local-liveness.ll less more
    None ; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx}
    1
    2 ; Local regalloc shouldn't assume that both the uses of the
    3 ; sub instruction are kills, because one of them is tied
    4 ; to an output. Previously, it was allocating both inputs
    5 ; in the same register.
    6
    7 define i32 @func_3() nounwind {
    8 entry:
    9 %retval = alloca i32 ; [#uses=2]
    10 %g_323 = alloca i8 ; [#uses=2]
    11 %p_5 = alloca i64, align 8 ; [#uses=2]
    12 %0 = alloca i32 ; [#uses=2]
    13 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
    14 store i64 0, i64* %p_5, align 8
    15 store i8 1, i8* %g_323, align 1
    16 %1 = load i8* %g_323, align 1 ; [#uses=1]
    17 %2 = sext i8 %1 to i64 ; [#uses=1]
    18 %3 = load i64* %p_5, align 8 ; [#uses=1]
    19 %4 = sub i64 %3, %2 ; [#uses=1]
    20 %5 = icmp sge i64 %4, 0 ; [#uses=1]
    21 %6 = zext i1 %5 to i32 ; [#uses=1]
    22 store i32 %6, i32* %0, align 4
    23 %7 = load i32* %0, align 4 ; [#uses=1]
    24 store i32 %7, i32* %retval, align 4
    25 br label %return
    26
    27 return: ; preds = %entry
    28 %retval1 = load i32* %retval ; [#uses=1]
    29 ret i32 %retval1
    30 }
    None ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
    1 ; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
    0 ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
    1 ; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
    22 ; CHECKed instructions should be the same with or without -O0.
    33
    44 @.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]