llvm.org GIT mirror llvm / 8a312fb
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
5 changed file(s) with 4 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
558558 break; // No prefix!
559559 }
560560
561
562 // Set the vector length to 256-bit if YMM0-YMM15 is used
563 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
564 if (!MI.getOperand(i).isReg())
565 continue;
566 unsigned SrcReg = MI.getOperand(i).getReg();
567 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
568 VEX_L = 1;
569 }
570561
571562 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
572563 unsigned NumOps = Desc.getNumOperands();
920920 }
921921
922922
923 // Set the vector length to 256-bit if YMM0-YMM15 is used
924 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
925 if (!MI.getOperand(i).isReg())
926 continue;
927 if (MI.getOperand(i).isImplicit())
928 continue;
929 unsigned SrcReg = MI.getOperand(i).getReg();
930 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
931 VEX_L = 1;
932 }
933
934923 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
935924 unsigned NumOps = Desc->getNumOperands();
936925 unsigned CurOp = 0;
26132613 OpSize, VEX;
26142614 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
26152615 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2616 SSEPackedSingle>, TB, VEX;
2616 SSEPackedSingle>, TB, VEX, VEX_L;
26172617 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
26182618 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
26192619 SSEPackedDouble>, TB,
2620 OpSize, VEX;
2620 OpSize, VEX, VEX_L;
26212621 }
26222622
26232623 defm MOVMSKPS : sse12_extr_sign_mask
243243 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
244244 (Name.find("CRC32") != Name.npos);
245245 HasFROperands = hasFROperands();
246 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
246 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
247247
248248 // Check for 64-bit inst which does not require REX
249249 Is32Bit = false;
478478 return false;
479479 }
480480
481 bool RecognizableInstr::has256BitOperands() const {
482 const std::vector &OperandList = *Operands;
483 unsigned numOperands = OperandList.size();
484
485 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
486 const std::string &recName = OperandList[operandIndex].Rec->getName();
487
488 if (!recName.compare("VR256")) {
489 return true;
490 }
491 }
492 return false;
493 }
494
495481 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
496482 unsigned &physicalOperandIndex,
497483 unsigned &numPhysicalOperands,
126126
127127 /// hasFROperands - Returns true if any operand is a FR operand.
128128 bool hasFROperands() const;
129
130 /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
131 bool has256BitOperands() const;
132
129
133130 /// typeFromString - Translates an operand type from the string provided in
134131 /// the LLVM tables to an OperandType for use in the operand specifier.
135132 ///