llvm.org GIT mirror llvm / 8a028a2
Merging r292712 and r292713: ------------------------------------------------------------------------ r292712 | ctopper | 2017-01-20 22:59:35 -0800 (Fri, 20 Jan 2017) | 1 line [X86] Add test cases that show bad commuting being allowed to create a phsub operation. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r292713 | ctopper | 2017-01-20 22:59:38 -0800 (Fri, 20 Jan 2017) | 3 lines [X86] Don't allow commuting to form phsub operations. Fixes PR31714. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293299 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
2 changed file(s) with 60 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
3369233692 }
3369333693 }
3369433694
33695 // Try to synthesize horizontal adds from adds of shuffles.
33695 // Try to synthesize horizontal subs from subs of shuffles.
3369633696 EVT VT = N->getValueType(0);
3369733697 if (((Subtarget.hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
3369833698 (Subtarget.hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
33699 isHorizontalBinOp(Op0, Op1, true))
33699 isHorizontalBinOp(Op0, Op1, false))
3370033700 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
3370133701
3370233702 return OptimizeConditionalInDecrement(N, DAG);
224224 %r = sub <4 x i32> %a, %b
225225 ret <4 x i32> %r
226226 }
227
228 define <8 x i16> @phsubw1_reverse(<8 x i16> %x, <8 x i16> %y) {
229 ; SSSE3-LABEL: phsubw1_reverse:
230 ; SSSE3: # BB#0:
231 ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15]
232 ; SSSE3-NEXT: movdqa %xmm1, %xmm4
233 ; SSSE3-NEXT: pshufb %xmm3, %xmm4
234 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
235 ; SSSE3-NEXT: pshufb %xmm3, %xmm2
236 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
237 ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
238 ; SSSE3-NEXT: pshufb %xmm3, %xmm1
239 ; SSSE3-NEXT: pshufb %xmm3, %xmm0
240 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
241 ; SSSE3-NEXT: psubw %xmm0, %xmm2
242 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
243 ; SSSE3-NEXT: retq
244 ;
245 ; AVX-LABEL: phsubw1_reverse:
246 ; AVX: # BB#0:
247 ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15]
248 ; AVX-NEXT: vpshufb %xmm2, %xmm1, %xmm3
249 ; AVX-NEXT: vpshufb %xmm2, %xmm0, %xmm2
250 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
251 ; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
252 ; AVX-NEXT: vpshufb %xmm3, %xmm1, %xmm1
253 ; AVX-NEXT: vpshufb %xmm3, %xmm0, %xmm0
254 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
255 ; AVX-NEXT: vpsubw %xmm0, %xmm2, %xmm0
256 ; AVX-NEXT: retq
257 %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32>
258 %b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32>
259 %r = sub <8 x i16> %a, %b
260 ret <8 x i16> %r
261 }
262
263 define <4 x i32> @phsubd1_reverse(<4 x i32> %x, <4 x i32> %y) {
264 ; SSSE3-LABEL: phsubd1_reverse:
265 ; SSSE3: # BB#0:
266 ; SSSE3-NEXT: movaps %xmm0, %xmm2
267 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
268 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
269 ; SSSE3-NEXT: psubd %xmm0, %xmm2
270 ; SSSE3-NEXT: movdqa %xmm2, %xmm0
271 ; SSSE3-NEXT: retq
272 ;
273 ; AVX-LABEL: phsubd1_reverse:
274 ; AVX: # BB#0:
275 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm0[1,3],xmm1[1,3]
276 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
277 ; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0
278 ; AVX-NEXT: retq
279 %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32>
280 %b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32>
281 %r = sub <4 x i32> %a, %b
282 ret <4 x i32> %r
283 }
284