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[AArch64][SVE2] Asm: add int halving add/sub (predicated) instructions Summary: This patch adds support for the predicated integer halving add/sub instructions: * SHADD, UHADD, SRHADD, URHADD * SHSUB, UHSUB, SHSUBR, UHSUBR The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D62000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361136 91177308-0d34-0410-b5e6-96231b3b80d8 Cullen Rhodes 6 months ago
18 changed file(s) with 811 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
11121112 defm SQDMLALBT_ZZZ : sve2_int_mla_long<0b00010, "sqdmlalbt">;
11131113 defm SQDMLSLBT_ZZZ : sve2_int_mla_long<0b00011, "sqdmlslbt">;
11141114
1115 // SVE2 integer halving add/subtract (predicated)
1116 defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd">;
1117 defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd">;
1118 defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub">;
1119 defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub">;
1120 defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd">;
1121 defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd">;
1122 defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr">;
1123 defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr">;
1124
11151125 // SVE2 integer multiply long
11161126 defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
11171127 defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
20572057 }
20582058
20592059 //===----------------------------------------------------------------------===//
2060 // SVE2 Integer - Predicated Group
2061 //===----------------------------------------------------------------------===//
2062
2063 class sve2_int_arith_pred sz, bits<6> opc, string asm,
2064 ZPRRegOp zprty>
2065 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2066 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
2067 bits<3> Pg;
2068 bits<5> Zm;
2069 bits<5> Zdn;
2070 let Inst{31-24} = 0b01000100;
2071 let Inst{23-22} = sz;
2072 let Inst{21-20} = 0b01;
2073 let Inst{20-16} = opc{5-1};
2074 let Inst{15-14} = 0b10;
2075 let Inst{13} = opc{0};
2076 let Inst{12-10} = Pg;
2077 let Inst{9-5} = Zm;
2078 let Inst{4-0} = Zdn;
2079
2080 let Constraints = "$Zdn = $_Zdn";
2081 let DestructiveInstType = Destructive;
2082 let ElementSize = zprty.ElementSize;
2083 }
2084
2085 multiclass sve2_int_arith_pred opc, string asm> {
2086 def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>;
2087 def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>;
2088 def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>;
2089 def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>;
2090 }
2091
2092 //===----------------------------------------------------------------------===//
20602093 // SVE2 Widening Integer Arithmetic Group
20612094 //===----------------------------------------------------------------------===//
20622095
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 shadd z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: shadd z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 shadd z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: shadd z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 shadd z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: shadd z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 shadd z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: shadd z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 shadd z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 shadd z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x10,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 10 44
14
15 shadd z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x50,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 50 44
20
21 shadd z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x90,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 90 44
26
27 shadd z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d0 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 shadd z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd0,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d0 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 shadd z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d0 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 shsub z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: shsub z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 shsub z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: shsub z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 shsub z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: shsub z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 shsub z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: shsub z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 shsub z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 shsub z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x12,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 12 44
14
15 shsub z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x52,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 52 44
20
21 shsub z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x92,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 92 44
26
27 shsub z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d2 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 shsub z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd2,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d2 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 shsub z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d2 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 shsubr z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: shsubr z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 shsubr z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: shsubr z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 shsubr z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: shsubr z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 shsubr z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: shsubr z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 shsubr z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 shsubr z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x16,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 16 44
14
15 shsubr z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x56,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 56 44
20
21 shsubr z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x96,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 96 44
26
27 shsubr z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d6 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 shsubr z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd6,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d6 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 shsubr z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d6 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 srhadd z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: srhadd z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 srhadd z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: srhadd z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 srhadd z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: srhadd z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 srhadd z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: srhadd z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 srhadd z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 srhadd z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x14,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 14 44
14
15 srhadd z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x54,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 54 44
20
21 srhadd z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x94,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 94 44
26
27 srhadd z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d4 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 srhadd z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd4,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d4 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 srhadd z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d4 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 uhadd z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: uhadd z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 uhadd z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: uhadd z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 uhadd z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: uhadd z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 uhadd z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: uhadd z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 uhadd z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 uhadd z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x11,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 11 44
14
15 uhadd z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x51,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 51 44
20
21 uhadd z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x91,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 91 44
26
27 uhadd z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d1 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 uhadd z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd1,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d1 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 uhadd z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d1 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 uhsub z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: uhsub z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 uhsub z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: uhsub z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 uhsub z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: uhsub z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 uhsub z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: uhsub z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 uhsub z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 uhsub z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x13,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 13 44
14
15 uhsub z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x53,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 53 44
20
21 uhsub z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x93,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 93 44
26
27 uhsub z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d3 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 uhsub z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd3,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d3 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 uhsub z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d3 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 uhsubr z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: uhsubr z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 uhsubr z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: uhsubr z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 uhsubr z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: uhsubr z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 uhsubr z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: uhsubr z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 uhsubr z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 uhsubr z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x17,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 17 44
14
15 uhsubr z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x57,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 57 44
20
21 uhsubr z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x97,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 97 44
26
27 uhsubr z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d7 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 uhsubr z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd7,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d7 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 uhsubr z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d7 44
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
1
2 // --------------------------------------------------------------------------//
3 // Source and Destination Registers must match
4
5 urhadd z0.b, p0/m, z1.b, z2.b
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
7 // CHECK-NEXT: urhadd z0.b, p0/m, z1.b, z2.b
8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9
10
11 // --------------------------------------------------------------------------//
12 // Element sizes must match
13
14 urhadd z0.b, p0/m, z0.d, z1.d
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
16 // CHECK-NEXT: urhadd z0.b, p0/m, z0.d, z1.d
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19 urhadd z0.b, p0/m, z0.b, z1.h
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: urhadd z0.b, p0/m, z0.b, z1.h
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24
25 // --------------------------------------------------------------------------//
26 // Invalid predicate
27
28 urhadd z0.b, p0/z, z0.b, z1.b
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30 // CHECK-NEXT: urhadd z0.b, p0/z, z0.b, z1.b
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32
33 urhadd z0.b, p8/m, z0.b, z1.b
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
35 // CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
1 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
3 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
7 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
8
9 urhadd z0.b, p0/m, z0.b, z1.b
10 // CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b
11 // CHECK-ENCODING: [0x20,0x80,0x15,0x44]
12 // CHECK-ERROR: instruction requires: sve2
13 // CHECK-UNKNOWN: 20 80 15 44
14
15 urhadd z0.h, p0/m, z0.h, z1.h
16 // CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h
17 // CHECK-ENCODING: [0x20,0x80,0x55,0x44]
18 // CHECK-ERROR: instruction requires: sve2
19 // CHECK-UNKNOWN: 20 80 55 44
20
21 urhadd z29.s, p7/m, z29.s, z30.s
22 // CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s
23 // CHECK-ENCODING: [0xdd,0x9f,0x95,0x44]
24 // CHECK-ERROR: instruction requires: sve2
25 // CHECK-UNKNOWN: dd 9f 95 44
26
27 urhadd z31.d, p7/m, z31.d, z30.d
28 // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
29 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
30 // CHECK-ERROR: instruction requires: sve2
31 // CHECK-UNKNOWN: df 9f d5 44
32
33 // --------------------------------------------------------------------------//
34 // Test compatibility with MOVPRFX instruction.
35
36 movprfx z31.d, p0/z, z6.d
37 // CHECK-INST: movprfx z31.d, p0/z, z6.d
38 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
39 // CHECK-ERROR: instruction requires: sve
40 // CHECK-UNKNOWN: df 20 d0 04
41
42 urhadd z31.d, p0/m, z31.d, z30.d
43 // CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d
44 // CHECK-ENCODING: [0xdf,0x83,0xd5,0x44]
45 // CHECK-ERROR: instruction requires: sve2
46 // CHECK-UNKNOWN: df 83 d5 44
47
48 movprfx z31, z6
49 // CHECK-INST: movprfx z31, z6
50 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
51 // CHECK-ERROR: instruction requires: sve
52 // CHECK-UNKNOWN: df bc 20 04
53
54 urhadd z31.d, p7/m, z31.d, z30.d
55 // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
56 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
57 // CHECK-ERROR: instruction requires: sve2
58 // CHECK-UNKNOWN: df 9f d5 44