llvm.org GIT mirror llvm / 88b6331
eliminateFrameIndex() bug when frame pointer is used as base register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33945 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 28 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
385385 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
386386 if (DestReg == ARM::SP)
387387 MIB.addReg(BaseReg).addReg(LdReg);
388 else if (isSub)
389 MIB.addReg(BaseReg).addReg(LdReg);
388390 else
389391 MIB.addReg(LdReg).addReg(BaseReg);
390392 if (DestReg == ARM::SP)
646648 // MI would expand into a large number of instructions. Don't try to
647649 // simplify the immediate.
648650 if (NumMIs > 2) {
649 emitThumbRegPlusImmediate(MBB, II, DestReg, ARM::SP, Offset, TII);
651 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
650652 MBB.erase(II);
651653 return;
652654 }
704706 case ARMII::AddrModeTs: {
705707 ImmIdx = i+1;
706708 InstrOffs = MI.getOperand(ImmIdx).getImm();
707 NumBits = 8;
709 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
708710 Scale = 4;
709711 break;
710712 }
721723 isSub = true;
722724 }
723725
724 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
725 int ImmedOffset = Offset / Scale;
726 unsigned Mask = (1 << NumBits) - 1;
727 if ((unsigned)Offset <= Mask * Scale) {
728 // Replace the FrameIndex with sp
729 MI.getOperand(i).ChangeToRegister(FrameReg, false);
726 if (!isSub || !isThumb) {
727 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
728 int ImmedOffset = Offset / Scale;
729 unsigned Mask = (1 << NumBits) - 1;
730 if ((unsigned)Offset <= Mask * Scale) {
731 // Replace the FrameIndex with sp
732 MI.getOperand(i).ChangeToRegister(FrameReg, false);
733 if (isSub)
734 ImmedOffset |= 1 << NumBits;
735 ImmOp.ChangeToImmediate(ImmedOffset);
736 return;
737 }
738
739 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
740 if (AddrMode == ARMII::AddrModeTs) {
741 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
742 // a different base register.
743 NumBits = 5;
744 Mask = (1 << NumBits) - 1;
745 }
746
747 ImmedOffset = ImmedOffset & Mask;
730748 if (isSub)
731749 ImmedOffset |= 1 << NumBits;
732750 ImmOp.ChangeToImmediate(ImmedOffset);
733 return;
734 }
735
736 // Otherwise, it didn't fit. Pull in what we can to simplify the immediate.
737 if (AddrMode == ARMII::AddrModeTs) {
738 // Thumb tLDRspi, tSTRspi. These will change to instructions that use a
739 // different base register.
740 NumBits = 5;
741 Mask = (1 << NumBits) - 1;
742 }
743
744 ImmedOffset = ImmedOffset & Mask;
745 if (isSub)
746 ImmedOffset |= 1 << NumBits;
747 ImmOp.ChangeToImmediate(ImmedOffset);
748 Offset &= ~(Mask*Scale);
751 Offset &= ~(Mask*Scale);
752 }
749753 }
750754
751755 // If we get here, the immediate doesn't fit into the instruction. We folded