llvm.org GIT mirror llvm / 88afd08
[ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293348 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
11 changed file(s) with 305 addition(s) and 178 deletion(s). Raw diff Collapse all Expand all
1212
1313 #include "ARMConstantPoolValue.h"
1414 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringRef.h"
1516 #include "llvm/CodeGen/MachineBasicBlock.h"
1617 #include "llvm/IR/Constant.h"
1718 #include "llvm/IR/Constants.h"
1819 #include "llvm/IR/GlobalValue.h"
1920 #include "llvm/IR/Type.h"
21 #include "llvm/Support/Casting.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/ErrorHandling.h"
2024 #include "llvm/Support/raw_ostream.h"
21 #include
25
2226 using namespace llvm;
2327
2428 //===----------------------------------------------------------------------===//
4347 LabelId(id), Kind(kind), PCAdjust(PCAdj), Modifier(modifier),
4448 AddCurrentAddress(addCurrentAddress) {}
4549
46 ARMConstantPoolValue::~ARMConstantPoolValue() {}
50 ARMConstantPoolValue::~ARMConstantPoolValue() = default;
4751
4852 StringRef ARMConstantPoolValue::getModifierText() const {
4953 switch (Modifier) {
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H
1414 #define LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H
1515
16 #include "llvm/ADT/StringRef.h"
1617 #include "llvm/CodeGen/MachineConstantPool.h"
1718 #include "llvm/Support/Casting.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include <cstddef>
19 #include <string>
20 #include
2021
2122 namespace llvm {
2223
2829 class MachineBasicBlock;
2930
3031 namespace ARMCP {
32
3133 enum ARMCPKind {
3234 CPValue,
3335 CPExtSymbol,
4648 SECREL, /// Section Relative (Windows TLS)
4749 SBREL, /// Static Base Relative (RWPI)
4850 };
49 }
51
52 } // end namespace ARMCP
5053
5154 /// ARMConstantPoolValue - ARM specific constantpool value. This is used to
5255 /// represent PC-relative displacement between the address of the load
168171
169172 const GlobalValue *getGV() const;
170173 const BlockAddress *getBlockAddress() const;
174
171175 const GlobalVariable *getPromotedGlobal() const {
172176 return dyn_cast_or_null(GVar);
173177 }
178
174179 const Constant *getPromotedGlobalInit() const {
175180 return CVal;
176181 }
185190 void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
186191
187192 void print(raw_ostream &O) const override;
193
188194 static bool classof(const ARMConstantPoolValue *APV) {
189195 return APV->isGlobalValue() || APV->isBlockAddress() || APV->isLSDA() ||
190196 APV->isPromotedGlobal();
266272 }
267273 };
268274
269 } // End llvm namespace
270
271 #endif
275 } // end namespace llvm
276
277 #endif // LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #include "ARMISelLowering.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
1516 #include "ARMCallingConv.h"
1617 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
1719 #include "ARMMachineFunctionInfo.h"
1820 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSelectionDAGInfo.h"
1923 #include "ARMSubtarget.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
2224 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMBaseInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
2333 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
2435 #include "llvm/ADT/StringExtras.h"
2536 #include "llvm/ADT/StringSwitch.h"
37 #include "llvm/ADT/StringRef.h"
38 #include "llvm/ADT/Triple.h"
39 #include "llvm/ADT/Twine.h"
2640 #include "llvm/CodeGen/CallingConvLower.h"
41 #include "llvm/CodeGen/ISDOpcodes.h"
2742 #include "llvm/CodeGen/IntrinsicLowering.h"
2843 #include "llvm/CodeGen/MachineBasicBlock.h"
44 #include "llvm/CodeGen/MachineConstantPool.h"
2945 #include "llvm/CodeGen/MachineFrameInfo.h"
3046 #include "llvm/CodeGen/MachineFunction.h"
47 #include "llvm/CodeGen/MachineInstr.h"
3148 #include "llvm/CodeGen/MachineInstrBuilder.h"
3249 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
50 #include "llvm/CodeGen/MachineMemOperand.h"
51 #include "llvm/CodeGen/MachineOperand.h"
3452 #include "llvm/CodeGen/MachineRegisterInfo.h"
53 #include "llvm/CodeGen/MachineValueType.h"
54 #include "llvm/CodeGen/RuntimeLibcalls.h"
3555 #include "llvm/CodeGen/SelectionDAG.h"
56 #include "llvm/CodeGen/SelectionDAGNodes.h"
57 #include "llvm/CodeGen/ValueTypes.h"
58 #include "llvm/IR/Attributes.h"
3659 #include "llvm/IR/CallingConv.h"
60 #include "llvm/IR/Constant.h"
3761 #include "llvm/IR/Constants.h"
3862 #include "llvm/IR/Function.h"
39 #include "llvm/IR/DebugInfoMetadata.h"
63 #include "llvm/IR/DataLayout.h"
64 #include "llvm/IR/DebugLoc.h"
65 #include "llvm/IR/DerivedTypes.h"
66 #include "llvm/IR/Function.h"
67 #include "llvm/IR/GlobalAlias.h"
4068 #include "llvm/IR/GlobalValue.h"
69 #include "llvm/IR/GlobalVariable.h"
4170 #include "llvm/IR/IRBuilder.h"
71 #include "llvm/IR/InlineAsm.h"
4272 #include "llvm/IR/Instruction.h"
4373 #include "llvm/IR/Instructions.h"
4474 #include "llvm/IR/IntrinsicInst.h"
4575 #include "llvm/IR/Intrinsics.h"
76 #include "llvm/IR/Module.h"
4677 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
78 #include "llvm/IR/User.h"
79 #include "llvm/IR/Value.h"
80 #include "llvm/MC/MCInstrDesc.h"
81 #include "llvm/MC/MCInstrItineraries.h"
82 #include "llvm/MC/MCRegisterInfo.h"
83 #include "llvm/MC/MCSchedule.h"
84 #include "llvm/Support/AtomicOrdering.h"
85 #include "llvm/Support/BranchProbability.h"
86 #include "llvm/Support/Casting.h"
87 #include "llvm/Support/CodeGen.h"
4888 #include "llvm/Support/CommandLine.h"
89 #include "llvm/Support/Compiler.h"
4990 #include "llvm/Support/Debug.h"
5091 #include "llvm/Support/ErrorHandling.h"
5192 #include "llvm/Support/MathExtras.h"
5293 #include "llvm/Support/raw_ostream.h"
94 #include "llvm/Target/TargetInstrInfo.h"
95 #include "llvm/Target/TargetMachine.h"
5396 #include "llvm/Target/TargetOptions.h"
97 #include
98 #include
99 #include
100 #include
101 #include
102 #include
103 #include
104 #include
54105 #include
106 #include
107
55108 using namespace llvm;
56109
57110 #define DEBUG_TYPE "arm-isel"
82135 cl::init(128));
83136
84137 namespace {
138
85139 class ARMCCState : public CCState {
86140 public:
87141 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
94148 CallOrPrologue = PC;
95149 }
96150 };
97 }
151
152 } // end anonymous namespace
98153
99154 // The APCS parameter registers.
100155 static const MCPhysReg GPRArgRegs[] = {
21462201 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
21472202 const TargetInstrInfo *TII) {
21482203 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2149 int FI = INT_MAX;
2204 int FI = std::numeric_limits::max();
21502205 if (Arg.getOpcode() == ISD::CopyFromReg) {
21512206 unsigned VR = cast(Arg.getOperand(1))->getReg();
21522207 if (!TargetRegisterInfo::isVirtualRegister(VR))
21762231 } else
21772232 return false;
21782233
2179 assert(FI != INT_MAX);
2234 assert(FI != std::numeric_limits::max());
21802235 if (!MFI.isFixedObjectIndex(FI))
21812236 return false;
21822237 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
35903645 InVals.push_back(ArgValue);
35913646
35923647 } else { // VA.isRegLoc()
3593
35943648 // sanity check
35953649 assert(VA.isMemLoc());
35963650 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
38033857 return std::make_pair(Value, OverflowCmp);
38043858 }
38053859
3806
38073860 SDValue
38083861 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
38093862 // Let legalize expand this if it isn't a legal type yet.
38263879 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
38273880 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
38283881 }
3829
38303882
38313883 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
38323884 SDValue Cond = Op.getOperand(0);
40204072 // Additionally, the variable is returned in parameter V and the constant in K.
40214073 static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
40224074 uint64_t &K) {
4023
40244075 SDValue LHS1 = Op.getOperand(0);
40254076 SDValue RHS1 = Op.getOperand(1);
40264077 SDValue TrueVal1 = Op.getOperand(2);
40414092 // in each conditional
40424093 SDValue *K1 = isa(LHS1) ? &LHS1 : isa(RHS1)
40434094 ? &RHS1
4044 : NULL;
4095 : nullptr;
40454096 SDValue *K2 = isa(LHS2) ? &LHS2 : isa(RHS2)
40464097 ? &RHS2
4047 : NULL;
4098 : nullptr;
40484099 SDValue K2Tmp = isa(TrueVal2) ? TrueVal2 : FalseVal2;
40494100 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
40504101 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
40684119 const SDValue *LowerCheckOp =
40694120 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
40704121 ? &Op
4071 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) ? &Op2
4072 : NULL;
4122 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4123 ? &Op2
4124 : nullptr;
40734125 const SDValue *UpperCheckOp =
40744126 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
40754127 ? &Op
4076 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) ? &Op2
4077 : NULL;
4128 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4129 ? &Op2
4130 : nullptr;
40784131
40794132 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
40804133 return false;
40994152 }
41004153
41014154 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4102
41034155 EVT VT = Op.getValueType();
41044156 SDLoc dl(Op);
41054157
55795631 return true;
55805632 }
55815633
5582
55835634 static bool isVEXTMask(ArrayRef M, EVT VT,
55845635 bool &ReverseVEXT, unsigned &Imm) {
55855636 unsigned NumElts = VT.getVectorNumElements();
60226073 }
60236074 if (ValueCounts.size() != 1)
60246075 usesOnlyOneValue = false;
6025 if (!Value.getNode() && ValueCounts.size() > 0)
6076 if (!Value.getNode() && !ValueCounts.empty())
60266077 Value = ValueCounts.begin()->first;
60276078
6028 if (ValueCounts.size() == 0)
6079 if (ValueCounts.empty())
60296080 return DAG.getUNDEF(VT);
60306081
60316082 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
61776228
61786229 struct ShuffleSourceInfo {
61796230 SDValue Vec;
6180 unsigned MinElt;
6181 unsigned MaxElt;
6231 unsigned MinElt = std::numeric_limits::max();
6232 unsigned MaxElt = 0;
61826233
61836234 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
61846235 // be compatible with the shuffle we intend to construct. As a result
61876238
61886239 // Code should guarantee that element i in Vec starts at element "WindowBase
61896240 // + i * WindowScale in ShuffleVec".
6190 int WindowBase;
6191 int WindowScale;
6241 int WindowBase = 0;
6242 int WindowScale = 1;
6243
6244 ShuffleSourceInfo(SDValue Vec) : Vec(Vec), ShuffleVec(Vec) {}
61926245
61936246 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
6194 ShuffleSourceInfo(SDValue Vec)
6195 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
6196 WindowScale(1) {}
61976247 };
61986248
61996249 // First gather all vectors used as an immediate source for this BUILD_VECTOR
62156265
62166266 // Add this element source to the list if it's not already there.
62176267 SDValue SourceVec = V.getOperand(0);
6218 auto Source = find(Sources, SourceVec);
6268 auto Source = llvm::find(Sources, SourceVec);
62196269 if (Source == Sources.end())
62206270 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
62216271
63316381 if (Entry.isUndef())
63326382 continue;
63336383
6334 auto Src = find(Sources, Entry.getOperand(0));
6384 auto Src = llvm::find(Sources, Entry.getOperand(0));
63356385 int EltNo = cast(Entry.getOperand(1))->getSExtValue();
63366386
63376387 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
66286678 EVT SubVT = SubV1.getValueType();
66296679
66306680 // We expect these to have been canonicalized to -1.
6631 assert(all_of(ShuffleMask, [&](int i) {
6681 assert(llvm::all_of(ShuffleMask, [&](int i) {
66326682 return i < (int)VT.getVectorNumElements();
66336683 }) && "Unexpected shuffle index into UNDEF operand!");
66346684
77967846
77977847 // Get a mapping of the call site numbers to all of the landing pads they're
77987848 // associated with.
7799 DenseMap > CallSiteNumToLPad;
7849 DenseMap> CallSiteNumToLPad;
78007850 unsigned MaxCSNum = 0;
78017851 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
78027852 ++BB) {
93799429 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
93809430 TargetLowering::DAGCombinerInfo &DCI,
93819431 const ARMSubtarget *Subtarget) {
9382
93839432 // Look for multiply add opportunities.
93849433 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
93859434 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
95929641 static SDValue PerformADDCCombine(SDNode *N,
95939642 TargetLowering::DAGCombinerInfo &DCI,
95949643 const ARMSubtarget *Subtarget) {
9595
95969644 if (Subtarget->isThumb1Only()) return SDValue();
95979645
95989646 // Only perform the checks after legalize when the pattern is available.
97909838 static SDValue PerformANDCombine(SDNode *N,
97919839 TargetLowering::DAGCombinerInfo &DCI,
97929840 const ARMSubtarget *Subtarget) {
9793
97949841 // Attempt to use immediate-form VBIC
97959842 BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1));
97969843 SDLoc dl(N);
1292912976 return true;
1293012977 }
1293112978 case Intrinsic::arm_stlexd:
12932 case Intrinsic::arm_strexd: {
12979 case Intrinsic::arm_strexd:
1293312980 Info.opc = ISD::INTRINSIC_W_CHAIN;
1293412981 Info.memVT = MVT::i64;
1293512982 Info.ptrVal = I.getArgOperand(2);
1293912986 Info.readMem = false;
1294012987 Info.writeMem = true;
1294112988 return true;
12942 }
12989
1294312990 case Intrinsic::arm_ldaexd:
12944 case Intrinsic::arm_ldrexd: {
12991 case Intrinsic::arm_ldrexd:
1294512992 Info.opc = ISD::INTRINSIC_W_CHAIN;
1294612993 Info.memVT = MVT::i64;
1294712994 Info.ptrVal = I.getArgOperand(0);
1295112998 Info.readMem = true;
1295212999 Info.writeMem = false;
1295313000 return true;
12954 }
13001
1295513002 default:
1295613003 break;
1295713004 }
1298913036 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
1299013037 // here.
1299113038 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
12992 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
13039 Function *MCR = Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
1299313040 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
1299413041 Builder.getInt32(0), Builder.getInt32(7),
1299513042 Builder.getInt32(10), Builder.getInt32(5)};
1300013047 llvm_unreachable("makeDMB on a target so old that it has no barriers");
1300113048 }
1300213049 } else {
13003 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
13050 Function *DMB = Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
1300413051 // Only a full system barrier exists in the M-class architectures.
1300513052 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
1300613053 Constant *CDomain = Builder.getInt32(Domain);
1315713204 if (ValTy->getPrimitiveSizeInBits() == 64) {
1315813205 Intrinsic::ID Int =
1315913206 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
13160 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
13207 Function *Ldrex = Intrinsic::getDeclaration(M, Int);
1316113208
1316213209 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
1316313210 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
1317413221
1317513222 Type *Tys[] = { Addr->getType() };
1317613223 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
13177 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
13224 Function *Ldrex = Intrinsic::getDeclaration(M, Int, Tys);
1317813225
1317913226 return Builder.CreateTruncOrBitCast(
1318013227 Builder.CreateCall(Ldrex, Addr),
1318613233 if (!Subtarget->hasV7Ops())
1318713234 return;
1318813235 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
13189 Builder.CreateCall(llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
13236 Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
1319013237 }
1319113238
1319213239 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1212
1313 #include "ARMSubtarget.h"
1414 #include "ARMFrameLowering.h"
15 #include "ARMISelLowering.h"
1615 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSelectionDAGInfo.h"
1916 #include "ARMSubtarget.h"
2017 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
2119 #include "Thumb1FrameLowering.h"
2220 #include "Thumb1InstrInfo.h"
2321 #include "Thumb2InstrInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Attributes.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/CodeGen/MachineFunction.h"
2626 #include "llvm/IR/Function.h"
2727 #include "llvm/IR/GlobalValue.h"
2828 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCTargetOptions.h"
2930 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
3131 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Support/CodeGen.h"
3333 #include "llvm/Support/TargetParser.h"
34 #include
35 #include
3436
3537 using namespace llvm;
3638
103105 : !isThumb()
104106 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
105107 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
106 TLInfo(TM, *this), GISel() {}
108 TLInfo(TM, *this) {}
107109
108110 const CallLowering *ARMSubtarget::getCallLowering() const {
109111 assert(GISel && "Access to GlobalISel APIs not set");
147149
148150 if (isTargetDarwin()) {
149151 StringRef ArchName = TargetTriple.getArchName();
150 unsigned ArchKind = llvm::ARM::parseArch(ArchName);
151 if (ArchKind == llvm::ARM::AK_ARMV7S)
152 unsigned ArchKind = ARM::parseArch(ArchName);
153 if (ArchKind == ARM::AK_ARMV7S)
152154 // Default to the Swift CPU when targeting armv7s/thumbv7s.
153155 CPUString = "swift";
154 else if (ArchKind == llvm::ARM::AK_ARMV7K)
156 else if (ArchKind == ARM::AK_ARMV7K)
155157 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
156158 // ARMv7k does not use SjLj exception handling.
157159 CPUString = "cortex-a7";
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
1414 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
1515
16
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
1718 #include "ARMFrameLowering.h"
1819 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
2020 #include "ARMSelectionDAGInfo.h"
21 #include "ARMSubtarget.h"
22 #include "MCTargetDesc/ARMMCTargetDesc.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
2621 #include "llvm/ADT/Triple.h"
2722 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
28 #include "llvm/IR/DataLayout.h"
23 #include "llvm/CodeGen/MachineFunction.h"
2924 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/MC/MCSchedule.h"
26 #include "llvm/Target/TargetOptions.h"
3027 #include "llvm/Target/TargetSubtargetInfo.h"
28 #include
3129 #include
3230
3331 #define GET_SUBTARGETINFO_HEADER
3432 #include "ARMGenSubtargetInfo.inc"
3533
3634 namespace llvm {
35
36 class ARMBaseTargetMachine;
3737 class GlobalValue;
3838 class StringRef;
39 class TargetOptions;
40 class ARMBaseTargetMachine;
4139
4240 class ARMSubtarget : public ARMGenSubtargetInfo {
4341 protected:
361359 unsigned getMaxInlineSizeThreshold() const {
362360 return 64;
363361 }
362
364363 /// ParseSubtargetFeatures - Parses features string setting specified
365364 /// subtarget options. Definition of function is auto generated by tblgen.
366365 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
372371 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
373372 return &TSInfo;
374373 }
374
375375 const ARMBaseInstrInfo *getInstrInfo() const override {
376376 return InstrInfo.get();
377377 }
378
378379 const ARMTargetLowering *getTargetLowering() const override {
379380 return &TLInfo;
380381 }
382
381383 const ARMFrameLowering *getFrameLowering() const override {
382384 return FrameLowering.get();
383385 }
386
384387 const ARMBaseRegisterInfo *getRegisterInfo() const override {
385388 return &InstrInfo->getRegisterInfo();
386389 }
450453 bool hasCRC() const { return HasCRC; }
451454 bool hasRAS() const { return HasRAS; }
452455 bool hasVirtualization() const { return HasVirtualization; }
456
453457 bool useNEONForSinglePrecisionFP() const {
454458 return hasNEON() && UseNEONForSinglePrecisionFP;
455459 }
460464 bool hasDataBarrier() const { return HasDataBarrier; }
461465 bool hasV7Clrex() const { return HasV7Clrex; }
462466 bool hasAcquireRelease() const { return HasAcquireRelease; }
467
463468 bool hasAnyDataBarrier() const {
464469 return HasDataBarrier || (hasV6Ops() && !isThumb());
465470 }
471
466472 bool useMulOps() const { return UseMulOps; }
467473 bool useFPVMLx() const { return !SlowFPVMLx; }
468474 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
560566 TargetTriple.getEnvironment() == Triple::EABIHF ||
561567 isTargetWindows() || isAAPCS16_ABI();
562568 }
569
563570 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
564571
565 virtual bool isXRaySupported() const override;
572 bool isXRaySupported() const override;
566573
567574 bool isAPCS_ABI() const;
568575 bool isAAPCS_ABI() const;
587594 bool useR7AsFramePointer() const {
588595 return isTargetDarwin() || (!isTargetWindows() && isThumb());
589596 }
597
590598 /// Returns true if the frame setup is split into two separate pushes (first
591599 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
592600 /// to lr. This is always required on Thumb1-only targets, as the push and
655663 /// True if fast-isel is used.
656664 bool useFastISel() const;
657665 };
658 } // End llvm namespace
659
660 #endif // ARMSUBTARGET_H
666
667 } // end namespace llvm
668
669 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
66 //
77 //===----------------------------------------------------------------------===//
88
9 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
109 #include "MCTargetDesc/ARMAddressingModes.h"
1110 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
11 #include "MCTargetDesc/ARMMCTargetDesc.h"
1312 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
13 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
1514 #include "llvm/MC/MCFixedLenDisassembler.h"
1615 #include "llvm/MC/MCInst.h"
1716 #include "llvm/MC/MCInstrDesc.h"
1817 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/Debug.h"
18 #include "llvm/MC/SubtargetFeature.h"
19 #include "llvm/Support/Compiler.h"
2020 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/LEB128.h"
21 #include "llvm/Support/MathExtras.h"
22 #include "llvm/Support/raw_ostream.h"
2223 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include
25 #include
26 #include
2427 #include
2528
2629 using namespace llvm;
3033 typedef MCDisassembler::DecodeStatus DecodeStatus;
3134
3235 namespace {
36
3337 // Handles the condition code status of instructions in IT blocks
3438 class ITStatus
3539 {
8084 private:
8185 std::vector ITStates;
8286 };
83 }
84
85 namespace {
87
8688 /// ARM disassembler for all ARM platforms.
8789 class ARMDisassembler : public MCDisassembler {
8890 public:
9092 MCDisassembler(STI, Ctx) {
9193 }
9294
93 ~ARMDisassembler() override {}
95 ~ARMDisassembler() override = default;
9496
9597 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
9698 ArrayRef Bytes, uint64_t Address,
105107 MCDisassembler(STI, Ctx) {
106108 }
107109
108 ~ThumbDisassembler() override {}
110 ~ThumbDisassembler() override = default;
109111
110112 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
111113 ArrayRef Bytes, uint64_t Address,
117119 DecodeStatus AddThumbPredicate(MCInst&) const;
118120 void UpdateThumbVFPPredicate(MCInst&) const;
119121 };
120 }
122
123 } // end anonymous namespace
121124
122125 static bool Check(DecodeStatus &Out, DecodeStatus In) {
123126 switch (In) {
133136 }
134137 llvm_unreachable("Invalid DecodeStatus!");
135138 }
136
137139
138140 // Forward declare these because the autogenerated code will reference them.
139141 // Definitions are further down.
318320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
319321 uint64_t Address, const void *Decoder);
320322
321
322323 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
323324 uint64_t Address, const void *Decoder);
324325 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
394395
395396 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
396397 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
398 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
398399 uint64_t Address, const void *Decoder);
400
399401 #include "ARMGenDisassemblerTables.inc"
400402
401403 static MCDisassembler *createARMDisassembler(const Target &T,
415417 uint64_t Address, raw_ostream &OS,
416418 raw_ostream &CS,
417419 uint32_t Insn,
418 DecodeStatus Result)
419 {
420 DecodeStatus Result) {
420421 switch (MI.getOpcode()) {
421422 case ARM::HVC: {
422423 // HVC is undefined if condition = 0xf otherwise upredictable
526527 }
527528
528529 namespace llvm {
530
529531 extern const MCInstrDesc ARMInsts[];
530 }
532
533 } // end namespace llvm
531534
532535 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
533536 /// immediate Value in the MCInst. The immediate Value has had any PC
858861 return MCDisassembler::Fail;
859862 }
860863
861
862864 extern "C" void LLVMInitializeARMDisassembler() {
863865 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
864866 createARMDisassembler);
10541056 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
10551057 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
10561058 };
1057
10581059
10591060 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
10601061 uint64_t Address, const void *Decoder) {
16751676 case ARM::LDRD:
16761677 case ARM::LDRD_PRE:
16771678 case ARM::LDRD_POST:
1678 if (type && Rn == 15){
1679 if (type && Rn == 15) {
16791680 if (Rt2 == 15)
16801681 S = MCDisassembler::SoftFail;
16811682 break;
16921693 case ARM::LDRH:
16931694 case ARM::LDRH_PRE:
16941695 case ARM::LDRH_POST:
1695 if (type && Rn == 15){
1696 if (type && Rn == 15) {
16961697 if (Rt == 15)
16971698 S = MCDisassembler::SoftFail;
16981699 break;
17101711 case ARM::LDRSB:
17111712 case ARM::LDRSB_PRE:
17121713 case ARM::LDRSB_POST:
1713 if (type && Rn == 15){
1714 if (type && Rn == 15) {
17141715 if (Rt == 15)
17151716 S = MCDisassembler::SoftFail;
17161717 break;
23072308
23082309 return S;
23092310 }
2310
23112311
23122312 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
23132313 uint64_t Address, const void *Decoder) {
37473747 return MCDisassembler::Success;
37483748 }
37493749
3750
37513750 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
37523751 uint64_t Address, const void *Decoder) {
37533752 DecodeStatus S = MCDisassembler::Success;
40724071
40734072 static DecodeStatus
40744073 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4075 uint64_t Address, const void *Decoder){
4074 uint64_t Address, const void *Decoder) {
40764075 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
40774076 true, 2, Inst, Decoder))
40784077 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
40804079 }
40814080
40824081 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4083 uint64_t Address, const void *Decoder){
4082 uint64_t Address,
4083 const void *Decoder) {
40844084 // Val is passed in as S:J1:J2:imm10:imm11
40854085 // Note no trailing zero after imm11. Also the J1 and J2 values are from
40864086 // the encoded instruction. So here change to I1 and I2 values via:
42464246 }
42474247
42484248 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4249 uint64_t Address, const void *Decoder){
4249 uint64_t Address,
4250 const void *Decoder) {
42504251 DecodeStatus S = MCDisassembler::Success;
42514252
42524253 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
43214322
43224323 return S;
43234324 }
4324
43254325
43264326 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
43274327 uint64_t Address, const void *Decoder) {
45054505 return S;
45064506 }
45074507
4508
45094508 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
45104509 uint64_t Address, const void *Decoder) {
45114510 DecodeStatus S = MCDisassembler::Success;
46364635 return S;
46374636 }
46384637
4639
46404638 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
46414639 uint64_t Address, const void *Decoder) {
46424640 DecodeStatus S = MCDisassembler::Success;
47694767
47704768 return S;
47714769 }
4772
47734770
47744771 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
47754772 uint64_t Address, const void *Decoder) {
52655262 return S;
52665263 }
52675264
5268 static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
5265 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
52695266 uint64_t Address, const void *Decoder) {
5270
52715267 DecodeStatus S = MCDisassembler::Success;
52725268
52735269 unsigned CRm = fieldFromInstruction(Val, 0, 4);
66 //
77 //===----------------------------------------------------------------------===//
88
9 #include "MCTargetDesc/ARMFixupKinds.h"
910 #include "MCTargetDesc/ARMMCTargetDesc.h"
10 #include "MCTargetDesc/ARMFixupKinds.h"
11 #include "llvm/ADT/Statistic.h"
12 #include "llvm/ADT/StringSwitch.h"
1311 #include "llvm/MC/MCELFObjectWriter.h"
1412 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCSectionELF.h"
13 #include "llvm/MC/MCFixup.h"
1614 #include "llvm/MC/MCValue.h"
17 #include "llvm/Support/Debug.h"
15 #include "llvm/Support/ELF.h"
1816 #include "llvm/Support/ErrorHandling.h"
1917 #include "llvm/Support/raw_ostream.h"
18 #include
2019
2120 using namespace llvm;
2221
2322 namespace {
23
2424 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
2525 enum { DefaultEABIVersion = 0x05000000U };
26
2627 unsigned GetRelocTypeInner(const MCValue &Target,
2728 const MCFixup &Fixup,
2829 bool IsPCRel) const;
2930
30
3131 public:
3232 ARMELFObjectWriter(uint8_t OSABI);
3333
34 ~ARMELFObjectWriter() override;
34 ~ARMELFObjectWriter() override = default;
3535
3636 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
3737 const MCFixup &Fixup, bool IsPCRel) const override;
3939 bool needsRelocateWithSymbol(const MCSymbol &Sym,
4040 unsigned Type) const override;
4141 };
42 }
42
43 } // end anonymous namespace
4344
4445 ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI)
4546 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI,
4647 ELF::EM_ARM,
4748 /*HasRelocationAddend*/ false) {}
48
49 ARMELFObjectWriter::~ARMELFObjectWriter() {}
5049
5150 bool ARMELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
5251 unsigned Type) const {
1414
1515 #include "ARMRegisterInfo.h"
1616 #include "ARMUnwindOpAsm.h"
17 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Triple.h"
1822 #include "llvm/ADT/Twine.h"
1923 #include "llvm/MC/MCAsmBackend.h"
2024 #include "llvm/MC/MCAsmInfo.h"
2327 #include "llvm/MC/MCContext.h"
2428 #include "llvm/MC/MCELFStreamer.h"
2529 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCFixup.h"
31 #include "llvm/MC/MCFragment.h"
2632 #include "llvm/MC/MCInst.h"
2733 #include "llvm/MC/MCInstPrinter.h"
28 #include "llvm/MC/MCObjectFileInfo.h"
29 #include "llvm/MC/MCObjectStreamer.h"
3034 #include "llvm/MC/MCRegisterInfo.h"
3135 #include "llvm/MC/MCSection.h"
3236 #include "llvm/MC/MCSectionELF.h"
3337 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSubtargetInfo.h"
39 #include "llvm/MC/MCSymbol.h"
3440 #include "llvm/MC/MCSymbolELF.h"
35 #include "llvm/MC/MCValue.h"
41 #include "llvm/MC/SectionKind.h"
3642 #include "llvm/Support/ARMBuildAttributes.h"
3743 #include "llvm/Support/ARMEHABI.h"
38 #include "llvm/Support/TargetParser.h"
39 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/Casting.h"
4045 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/ErrorHandling.h"
4147 #include "llvm/Support/FormattedStream.h"
4248 #include "llvm/Support/LEB128.h"
4349 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Support/TargetParser.h"
4451 #include
52 #include
53 #include
54 #include
55 #include
56 #include
4557
4658 using namespace llvm;
4759
100112 bool VerboseAsm)
101113 : ARMTargetStreamer(S), OS(OS), InstPrinter(InstPrinter),
102114 IsVerboseAsm(VerboseAsm) {}
115
103116 void ARMTargetAsmStreamer::emitFnStart() { OS << "\t.fnstart\n"; }
104117 void ARMTargetAsmStreamer::emitFnEnd() { OS << "\t.fnend\n"; }
105118 void ARMTargetAsmStreamer::emitCantUnwind() { OS << "\t.cantunwind\n"; }
119
106120 void ARMTargetAsmStreamer::emitPersonality(const MCSymbol *Personality) {
107121 OS << "\t.personality " << Personality->getName() << '\n';
108122 }
123
109124 void ARMTargetAsmStreamer::emitPersonalityIndex(unsigned Index) {
110125 OS << "\t.personalityindex " << Index << '\n';
111126 }
127
112128 void ARMTargetAsmStreamer::emitHandlerData() { OS << "\t.handlerdata\n"; }
129
113130 void ARMTargetAsmStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
114131 int64_t Offset) {
115132 OS << "\t.setfp\t";
120137 OS << ", #" << Offset;
121138 OS << '\n';
122139 }
140
123141 void ARMTargetAsmStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
124142 assert((Reg != ARM::SP && Reg != ARM::PC) &&
125143 "the operand of .movsp cannot be either sp or pc");
130148 OS << ", #" << Offset;
131149 OS << '\n';
132150 }
151
133152 void ARMTargetAsmStreamer::emitPad(int64_t Offset) {
134153 OS << "\t.pad\t#" << Offset << '\n';
135154 }
155
136156 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl &RegList,
137157 bool isVector) {
138158 assert(RegList.size() && "RegList should not be empty");
150170
151171 OS << "}\n";
152172 }
153 void ARMTargetAsmStreamer::switchVendor(StringRef Vendor) {
154 }
173
174 void ARMTargetAsmStreamer::switchVendor(StringRef Vendor) {}
175
155176 void ARMTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
156177 OS << "\t.eabi_attribute\t" << Attribute << ", " << Twine(Value);
157178 if (IsVerboseAsm) {
161182 }
162183 OS << "\n";
163184 }
185
164186 void ARMTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
165187 StringRef String) {
166188 switch (Attribute) {
178200 }
179201 OS << "\n";
180202 }
203
181204 void ARMTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
182205 unsigned IntValue,
183206 StringRef StringValue) {
193216 }
194217 OS << "\n";
195218 }
219
196220 void ARMTargetAsmStreamer::emitArch(unsigned Arch) {
197221 OS << "\t.arch\t" << ARM::getArchName(Arch) << "\n";
198222 }
223
199224 void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) {
200225 OS << "\t.arch_extension\t" << ARM::getArchExtName(ArchExt) << "\n";
201226 }
227
202228 void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) {
203229 OS << "\t.object_arch\t" << ARM::getArchName(Arch) << '\n';
204230 }
231
205232 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
206233 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n";
207234 }
208 void ARMTargetAsmStreamer::finishAttributeSection() {
209 }
235
236 void ARMTargetAsmStreamer::finishAttributeSection() {}
237
210238 void
211239 ARMTargetAsmStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *S) {
212240 OS << "\t.tlsdescseq\t" << S->getSymbol().getName();
273301 };
274302
275303 StringRef CurrentVendor;
276 unsigned FPU;
277 unsigned Arch;
278 unsigned EmittedArch;
304 unsigned FPU = ARM::FK_INVALID;
305 unsigned Arch = ARM::AK_INVALID;
306 unsigned EmittedArch = ARM::AK_INVALID;
279307 SmallVector Contents;
280308
281 MCSection *AttributeSection;
309 MCSection *AttributeSection = nullptr;
282310
283311 AttributeItem *getAttributeItem(unsigned Attribute) {
284312 for (size_t i = 0; i < Contents.size(); ++i)
392420
393421 public:
394422 ARMTargetELFStreamer(MCStreamer &S)
395 : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID),
396 Arch(ARM::AK_INVALID), EmittedArch(ARM::AK_INVALID),
397 AttributeSection(nullptr) {}
423 : ARMTargetStreamer(S), CurrentVendor("aeabi") {}
398424 };
399425
400426 /// Extend the generic ELFStreamer class so that it can emit mapping symbols at
415441
416442 ARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS,
417443 MCCodeEmitter *Emitter, bool IsThumb)
418 : MCELFStreamer(Context, TAB, OS, Emitter), IsThumb(IsThumb),
419 MappingSymbolCounter(0), LastEMS(EMS_None) {
444 : MCELFStreamer(Context, TAB, OS, Emitter), IsThumb(IsThumb) {
420445 EHReset();
421446 }
422447
423 ~ARMELFStreamer() {}
448 ~ARMELFStreamer() override = default;
424449
425450 void FinishImpl() override;
426451
598623 void EmitFixup(const MCExpr *Expr, MCFixupKind Kind);
599624
600625 bool IsThumb;
601 int64_t MappingSymbolCounter;
626 int64_t MappingSymbolCounter = 0;
602627
603628 DenseMap LastMappingSymbols;
604 ElfMappingSymbol LastEMS;
629 ElfMappingSymbol LastEMS = EMS_None;
605630
606631 // ARM Exception Handling Frame Information
607632 MCSymbol *ExTab;
617642 SmallVector Opcodes;
618643 UnwindOpcodeAssembler UnwindOpAsm;
619644 };
645
620646 } // end anonymous namespace
621647
622648 ARMELFStreamer &ARMTargetELFStreamer::getStreamer() {
626652 void ARMTargetELFStreamer::emitFnStart() { getStreamer().emitFnStart(); }
627653 void ARMTargetELFStreamer::emitFnEnd() { getStreamer().emitFnEnd(); }
628654 void ARMTargetELFStreamer::emitCantUnwind() { getStreamer().emitCantUnwind(); }
655
629656 void ARMTargetELFStreamer::emitPersonality(const MCSymbol *Personality) {
630657 getStreamer().emitPersonality(Personality);
631658 }
659
632660 void ARMTargetELFStreamer::emitPersonalityIndex(unsigned Index) {
633661 getStreamer().emitPersonalityIndex(Index);
634662 }
663
635664 void ARMTargetELFStreamer::emitHandlerData() {
636665 getStreamer().emitHandlerData();
637666 }
667
638668 void ARMTargetELFStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
639669 int64_t Offset) {
640670 getStreamer().emitSetFP(FpReg, SpReg, Offset);
641671 }
672
642673 void ARMTargetELFStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
643674 getStreamer().emitMovSP(Reg, Offset);
644675 }
676
645677 void ARMTargetELFStreamer::emitPad(int64_t Offset) {
646678 getStreamer().emitPad(Offset);
647679 }
680
648681 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl &RegList,
649682 bool isVector) {
650683 getStreamer().emitRegSave(RegList, isVector);
651684 }
685
652686 void ARMTargetELFStreamer::emitUnwindRaw(int64_t Offset,
653687 const SmallVectorImpl &Opcodes) {
654688 getStreamer().emitUnwindRaw(Offset, Opcodes);
655689 }
690
656691 void ARMTargetELFStreamer::switchVendor(StringRef Vendor) {
657692 assert(!Vendor.empty() && "Vendor cannot be empty.");
658693
667702 CurrentVendor = Vendor;
668703
669704 }
705
670706 void ARMTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
671707 setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
672708 }
709
673710 void ARMTargetELFStreamer::emitTextAttribute(unsigned Attribute,
674711 StringRef Value) {
675712 setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
676713 }
714
677715 void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
678716 unsigned IntValue,
679717 StringRef StringValue) {
680718 setAttributeItems(Attribute, IntValue, StringValue,
681719 /* OverwriteExisting= */ true);
682720 }
721
683722 void ARMTargetELFStreamer::emitArch(unsigned Value) {
684723 Arch = Value;
685724 }
725
686726 void ARMTargetELFStreamer::emitObjectArch(unsigned Value) {
687727 EmittedArch = Value;
688728 }
729
689730 void ARMTargetELFStreamer::emitArchDefaultAttributes() {
690731 using namespace ARMBuildAttrs;
691732
785826 break;
786827 }
787828 }
829
788830 void ARMTargetELFStreamer::emitFPU(unsigned Value) {
789831 FPU = Value;
790832 }
833
791834 void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
792835 switch (FPU) {
793836 case ARM::FK_VFP:
919962 break;
920963 }
921964 }
965
922966 size_t ARMTargetELFStreamer::calculateContentSize() const {
923967 size_t Result = 0;
924968 for (size_t i = 0; i < Contents.size(); ++i) {
943987 }
944988 return Result;
945989 }
990
946991 void ARMTargetELFStreamer::finishAttributeSection() {
947992 //
948993 // [ "vendor-name"
11131158 ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER,
11141159 SectionKind::getData(), FnStart);
11151160 }
1161
11161162 void ARMELFStreamer::EmitFixup(const MCExpr *Expr, MCFixupKind Kind) {
11171163 MCDataFragment *Frag = getOrCreateDataFragment();
11181164 Frag->getFixups().push_back(MCFixup::create(Frag->getContents().size(), Expr,
13951441 if (RelaxAll)
13961442 S->getAssembler().setRelaxAll(true);
13971443 return S;
1398 }
1399
1400 }
1401
1402
1444 }
1445
1446 } // end namespace llvm
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "MCTargetDesc/ARMMCTargetDesc.h"
1413 #include "MCTargetDesc/ARMAddressingModes.h"
1514 #include "MCTargetDesc/ARMBaseInfo.h"
1615 #include "MCTargetDesc/ARMFixupKinds.h"
1716 #include "MCTargetDesc/ARMMCExpr.h"
1817 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
1920 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
2022 #include "llvm/MC/MCCodeEmitter.h"
2123 #include "llvm/MC/MCContext.h"
2224 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
2326 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
2428 #include "llvm/MC/MCInstrInfo.h"
2529 #include "llvm/MC/MCRegisterInfo.h"
2630 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
2733 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
2835 #include "llvm/Support/raw_ostream.h"
36 #include
37 #include
38 #include
39 #include
2940
3041 using namespace llvm;
3142
3546 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
3647
3748 namespace {
49
3850 class ARMMCCodeEmitter : public MCCodeEmitter {
39 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
40 void operator=(const ARMMCCodeEmitter &) = delete;
4151 const MCInstrInfo &MCII;
4252 const MCContext &CTX;
4353 bool IsLittleEndian;
4656 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
4757 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
4858 }
49
50 ~ARMMCCodeEmitter() override {}
59 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61 ~ARMMCCodeEmitter() override = default;
5162
5263 bool isThumb(const MCSubtargetInfo &STI) const {
5364 return STI.getFeatureBits()[ARM::ModeThumb];
5465 }
66
5567 bool isThumb2(const MCSubtargetInfo &STI) const {
5668 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
5769 }
70
5871 bool isTargetMachO(const MCSubtargetInfo &STI) const {
5972 const Triple &TT = STI.getTargetTriple();
6073 return TT.isOSBinFormatMachO();
199212 case ARM_AM::ib: return 3;
200213 }
201214 }
215
202216 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
203217 ///
204218 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
272286 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
273287 SmallVectorImpl &Fixups,
274288 const MCSubtargetInfo &STI) const {
275
276289 const MCOperand &MO = MI.getOperand(Op);
277290
278291 // We expect MO to be an immediate or an expression,
431444
432445 } // end anonymous namespace
433446
434 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
435 const MCRegisterInfo &MRI,
436 MCContext &Ctx) {
437 return new ARMMCCodeEmitter(MCII, Ctx, true);
438 }
439
440 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
441 const MCRegisterInfo &MRI,
442 MCContext &Ctx) {
443 return new ARMMCCodeEmitter(MCII, Ctx, false);
444 }
445
446447 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
447448 /// instructions, and rewrite them to their Thumb2 form if we are currently in
448449 /// Thumb2 mode.
549550 bool ARMMCCodeEmitter::
550551 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
551552 unsigned &Imm, SmallVectorImpl &Fixups,
552 const MCSubtargetInfo &STI) const {
553 const MCSubtargetInfo &STI) const {
553554 const MCOperand &MO = MI.getOperand(OpIdx);
554555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
555556
15141515 uint32_t v = ~MO.getImm();
15151516 uint32_t lsb = countTrailingZeros(v);
15161517 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1517 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1518 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
15181519 return lsb | (msb << 5);
15191520 }
15201521
16991700 }
17001701
17011702 #include "ARMGenMCCodeEmitter.inc"
1703
1704 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
1705 const MCRegisterInfo &MRI,
1706 MCContext &Ctx) {
1707 return new ARMMCCodeEmitter(MCII, Ctx, true);
1708 }
1709
1710 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
1711 const MCRegisterInfo &MRI,
1712 MCContext &Ctx) {
1713 return new ARMMCCodeEmitter(MCII, Ctx, false);
1714 }
99 // This file implements the ARMTargetStreamer class.
1010 //
1111 //===----------------------------------------------------------------------===//
12 #include "llvm/ADT/MapVector.h"
12
1313 #include "llvm/MC/ConstantPools.h"
14 #include "llvm/MC/MCContext.h"
1514 #include "llvm/MC/MCExpr.h"
1615 #include "llvm/MC/MCStreamer.h"
1716
1817 using namespace llvm;
18
1919 //
2020 // ARMTargetStreamer Implemenation
2121 //
22
2223 ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)
2324 : MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
2425
25 ARMTargetStreamer::~ARMTargetStreamer() {}
26 ARMTargetStreamer::~ARMTargetStreamer() = default;
2627
2728 // The constant pool handling is shared by all ARMTargetStreamer
2829 // implementations.
7273 void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {}
7374 void
7475 ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
75
7676 void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
99 #include "MCTargetDesc/ARMFixupKinds.h"
1010 #include "llvm/ADT/Twine.h"
1111 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCExpr.h"
1213 #include "llvm/MC/MCFixup.h"
1314 #include "llvm/MC/MCFixupKindInfo.h"
1415 #include "llvm/MC/MCValue.h"
1516 #include "llvm/MC/MCWinCOFFObjectWriter.h"
1617 #include "llvm/Support/COFF.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include
1821
1922 using namespace llvm;
2023
2124 namespace {
25
2226 class ARMWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter {
2327 public:
2428 ARMWinCOFFObjectWriter(bool Is64Bit)
2529 : MCWinCOFFObjectTargetWriter(COFF::IMAGE_FILE_MACHINE_ARMNT) {
2630 assert(!Is64Bit && "AArch64 support not yet implemented");
2731 }
28 ~ARMWinCOFFObjectWriter() override {}
32
33 ~ARMWinCOFFObjectWriter() override = default;
2934
3035 unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
3136 bool IsCrossSection,
3338
3439 bool recordRelocation(const MCFixup &) const override;
3540 };
41
42 } // end anonymous namespace
3643
3744 unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
3845 const MCFixup &Fixup,
7885 bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
7986 return static_cast(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
8087 }
81 }
8288
8389 namespace llvm {
90
8491 MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS,
8592 bool Is64Bit) {
8693 MCWinCOFFObjectTargetWriter *MOTW = new ARMWinCOFFObjectWriter(Is64Bit);
8794 return createWinCOFFObjectWriter(MOTW, OS);
8895 }
89 }
9096
97 } // end namespace llvm