llvm.org GIT mirror llvm / 88a7ff4
Make TargetInstrInfo::isPredicable take a const reference, NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296901 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 3 years ago
13 changed file(s) with 17 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
11411141 /// Return true if the specified instruction can be predicated.
11421142 /// By default, this returns true for every instruction with a
11431143 /// PredicateOperand.
1144 virtual bool isPredicable(MachineInstr &MI) const {
1144 virtual bool isPredicable(const MachineInstr &MI) const {
11451145 return MI.getDesc().isPredicable();
11461146 }
11471147
868868 }
869869 }
870870
871 bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
871 bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
872872 // XXX: KILL* instructions can be predicated, but they must be the last
873873 // instruction in a clause, so this means any instructions after them cannot
874874 // be predicated. Until we have proper support for instruction clauses in the
879879 } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
880880 // If the clause start in the middle of MBB then the MBB has more
881881 // than a single clause, unable to predicate several clauses.
882 if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
882 if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI))
883883 return false;
884884 // TODO: We don't support KC merging atm
885885 return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
176176
177177 bool isPredicated(const MachineInstr &MI) const override;
178178
179 bool isPredicable(MachineInstr &MI) const override;
179 bool isPredicable(const MachineInstr &MI) const override;
180180
181181 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
182182 BranchProbability Probability) const override;
596596 /// isPredicable - Return true if the specified instruction can be predicated.
597597 /// By default, this returns true for every instruction with a
598598 /// PredicateOperand.
599 bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
599 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
600600 if (!MI.isPredicable())
601601 return false;
602602
606606 if (!isEligibleForITBlock(&MI))
607607 return false;
608608
609 ARMFunctionInfo *AFI =
609 const ARMFunctionInfo *AFI =
610610 MI.getParent()->getParent()->getInfo();
611611
612612 if (AFI->isThumb2Function()) {
622622
623623 namespace llvm {
624624
625 template <> bool IsCPSRDead(MachineInstr *MI) {
625 template <> bool IsCPSRDead(const MachineInstr *MI) {
626626 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
627627 const MachineOperand &MO = MI->getOperand(i);
628628 if (!MO.isReg() || MO.isUndef() || MO.isUse())
162162 bool DefinesPredicate(MachineInstr &MI,
163163 std::vector &Pred) const override;
164164
165 bool isPredicable(MachineInstr &MI) const override;
165 bool isPredicable(const MachineInstr &MI) const override;
166166
167167 /// GetInstSize - Returns the size of the specified MachineInstr.
168168 ///
1818 namespace llvm {
1919
2020 template // could be MachineInstr or MCInst
21 bool IsCPSRDead(InstrType *Instr);
21 bool IsCPSRDead(const InstrType *Instr);
2222
2323 template // could be MachineInstr or MCInst
24 inline bool isV8EligibleForIT(InstrType *Instr) {
24 inline bool isV8EligibleForIT(const InstrType *Instr) {
2525 switch (Instr->getOpcode()) {
2626 default:
2727 return false;
89848984 }
89858985
89868986 namespace llvm {
8987 template <> inline bool IsCPSRDead(MCInst *Instr) {
8987 template <> inline bool IsCPSRDead(const MCInst *Instr) {
89888988 return true; // In an assembly source, no need to second-guess
89898989 }
89908990 }
14331433 return false;
14341434 }
14351435
1436 bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
1436 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
14371437 return MI.getDesc().isPredicable();
14381438 }
14391439
234234 /// Return true if the specified instruction can be predicated.
235235 /// By default, this returns true for every instruction with a
236236 /// PredicateOperand.
237 bool isPredicable(MachineInstr &MI) const override;
237 bool isPredicable(const MachineInstr &MI) const override;
238238
239239 /// Test if the given instruction should be considered a scheduling boundary.
240240 /// This primarily includes labels and terminators.
14921492 return Found;
14931493 }
14941494
1495 bool PPCInstrInfo::isPredicable(MachineInstr &MI) const {
1495 bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
14961496 unsigned OpC = MI.getOpcode();
14971497 switch (OpC) {
14981498 default:
252252 bool DefinesPredicate(MachineInstr &MI,
253253 std::vector &Pred) const override;
254254
255 bool isPredicable(MachineInstr &MI) const override;
255 bool isPredicable(const MachineInstr &MI) const override;
256256
257257 // Comparison optimization.
258258
726726 return true;
727727 }
728728
729 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
729 bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
730730 unsigned Opcode = MI.getOpcode();
731731 if (Opcode == SystemZ::Return ||
732732 Opcode == SystemZ::Trap ||
214214 unsigned FalseReg) const override;
215215 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
216216 MachineRegisterInfo *MRI) const override;
217 bool isPredicable(MachineInstr &MI) const override;
217 bool isPredicable(const MachineInstr &MI) const override;
218218 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
219219 unsigned ExtraPredCycles,
220220 BranchProbability Probability) const override;