llvm.org GIT mirror llvm / 885280f
UpdateTestChecks: hexagon support Summary: These tests are being affected by an upcoming patch, so having an understandable (autogenerated) diff is helpful. This target, again, prefers `-march`: ``` llvm/test/CodeGen/Hexagon$ grep -r triple | wc -l 467 llvm/test/CodeGen/Hexagon$ grep -r march | wc -l 1167 ``` Reviewers: RKSimon, kparzysz Reviewed By: kparzysz Subscribers: xbolva00, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62867 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362605 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev 1 year, 5 months ago
4 changed file(s) with 130 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
12
23 @data1 = external global [2 x [31 x i8]], align 8
34 @data2 = external global [2 x [91 x i8]], align 8
45
6 define i32 @Prefer_M4_or_andn(i32 %a0, i32 %a1, i32 %a2) #0 {
57 ; CHECK-LABEL: Prefer_M4_or_andn:
6 ; CHECK: r2 |= and(r0,~r1)
7 define i32 @Prefer_M4_or_andn(i32 %a0, i32 %a1, i32 %a2) #0 {
8 ; CHECK: // %bb.0: // %b3
9 ; CHECK-NEXT: {
10 ; CHECK-NEXT: r2 = asl(r2,#5)
11 ; CHECK-NEXT: }
12 ; CHECK-NEXT: {
13 ; CHECK-NEXT: r2 |= and(r0,~r1)
14 ; CHECK-NEXT: }
15 ; CHECK-NEXT: {
16 ; CHECK-NEXT: r0 = r2
17 ; CHECK-NEXT: }
18 ; CHECK-NEXT: {
19 ; CHECK-NEXT: jumpr r31
20 ; CHECK-NEXT: }
821 b3:
922 %v4 = xor i32 %a1, -1
1023 %v5 = shl i32 %a2, 5
1326 ret i32 %v7
1427 }
1528
29 define i32 @Prefer_M4_mpyri_addi(i32 %a0) #0 {
1630 ; CHECK-LABEL: Prefer_M4_mpyri_addi:
17 ; CHECK: add(##data1,mpyi(r0,#31))
18 define i32 @Prefer_M4_mpyri_addi(i32 %a0) #0 {
31 ; CHECK: // %bb.0: // %b1
32 ; CHECK-NEXT: {
33 ; CHECK-NEXT: r0 = add(##data1,mpyi(r0,#31))
34 ; CHECK-NEXT: }
35 ; CHECK-NEXT: {
36 ; CHECK-NEXT: jumpr r31
37 ; CHECK-NEXT: }
1938 b1:
2039 %v2 = getelementptr inbounds [2 x [31 x i8]], [2 x [31 x i8]]* @data1, i32 0, i32 %a0
2140 %v3 = ptrtoint [31 x i8]* %v2 to i32
2241 ret i32 %v3
2342 }
2443
44 define i32 @Prefer_M4_mpyrr_addi(i32 %a0) #0 {
2545 ; CHECK-LABEL: Prefer_M4_mpyrr_addi:
26 ; CHECK: add(##data2,mpyi(r0,r1))
27 define i32 @Prefer_M4_mpyrr_addi(i32 %a0) #0 {
46 ; CHECK: // %bb.0: // %b1
47 ; CHECK-NEXT: {
48 ; CHECK-NEXT: r1 = #91
49 ; CHECK-NEXT: }
50 ; CHECK-NEXT: {
51 ; CHECK-NEXT: r0 = add(##data2,mpyi(r0,r1))
52 ; CHECK-NEXT: }
53 ; CHECK-NEXT: {
54 ; CHECK-NEXT: jumpr r31
55 ; CHECK-NEXT: }
2856 b1:
2957 %v2 = getelementptr inbounds [2 x [91 x i8]], [2 x [91 x i8]]* @data2, i32 0, i32 %a0
3058 %v3 = ptrtoint [91 x i8]* %v2 to i32
3159 ret i32 %v3
3260 }
3361
62 define i32 @Prefer_S2_tstbit_r(i32 %a0, i32 %a1) #0 {
3463 ; CHECK-LABEL: Prefer_S2_tstbit_r:
35 ; CHECK: p0 = tstbit(r0,r1)
36 define i32 @Prefer_S2_tstbit_r(i32 %a0, i32 %a1) #0 {
64 ; CHECK: // %bb.0: // %b2
65 ; CHECK-NEXT: {
66 ; CHECK-NEXT: p0 = tstbit(r0,r1)
67 ; CHECK-NEXT: }
68 ; CHECK-NEXT: {
69 ; CHECK-NEXT: r0 = mux(p0,#1,#0)
70 ; CHECK-NEXT: }
71 ; CHECK-NEXT: {
72 ; CHECK-NEXT: jumpr r31
73 ; CHECK-NEXT: }
3774 b2:
3875 %v3 = shl i32 1, %a1
3976 %v4 = and i32 %a0, %v3
4279 ret i32 %v6
4380 }
4481
82 define i32 @Prefer_S2_ntstbit_r(i32 %a0, i32 %a1) #0 {
4583 ; CHECK-LABEL: Prefer_S2_ntstbit_r:
46 ; CHECK: p0 = !tstbit(r0,r1)
47 define i32 @Prefer_S2_ntstbit_r(i32 %a0, i32 %a1) #0 {
84 ; CHECK: // %bb.0: // %b2
85 ; CHECK-NEXT: {
86 ; CHECK-NEXT: p0 = !tstbit(r0,r1)
87 ; CHECK-NEXT: }
88 ; CHECK-NEXT: {
89 ; CHECK-NEXT: r0 = mux(p0,#1,#0)
90 ; CHECK-NEXT: }
91 ; CHECK-NEXT: {
92 ; CHECK-NEXT: jumpr r31
93 ; CHECK-NEXT: }
4894 b2:
4995 %v3 = shl i32 1, %a1
5096 %v4 = and i32 %a0, %v3
5399 ret i32 %v6
54100 }
55101
102 define i64 @Prefer_L2_loadrub_io(i8* %a0) #0 {
56103 ; CHECK-LABEL: Prefer_L2_loadrub_io:
57 ; CHECK: memub(r0+#65)
58 define i64 @Prefer_L2_loadrub_io(i8* %a0) #0 {
104 ; CHECK: // %bb.0: // %b1
105 ; CHECK-NEXT: {
106 ; CHECK-NEXT: r0 = memub(r0+#65)
107 ; CHECK-NEXT: }
108 ; CHECK-NEXT: {
109 ; CHECK-NEXT: r1:0 = combine(#0,r0)
110 ; CHECK-NEXT: }
111 ; CHECK-NEXT: {
112 ; CHECK-NEXT: jumpr r31
113 ; CHECK-NEXT: }
59114 b1:
60115 %v2 = getelementptr i8, i8* %a0, i32 65
61116 %v3 = load i8, i8* %v2
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
1 ; CHECK: !tstbit
22
33 ; Function Attrs: nounwind
44 define i32 @f0(i32 %a0, i32 %a1, i32 %a2) #0 {
5 ; CHECK-LABEL: f0:
6 ; CHECK: // %bb.0: // %b0
7 ; CHECK-NEXT: {
8 ; CHECK-NEXT: p0 = !tstbit(r1,r2)
9 ; CHECK-NEXT: r17:16 = combine(r0,r1)
10 ; CHECK-NEXT: memd(r29+#-16) = r17:16
11 ; CHECK-NEXT: allocframe(#8)
12 ; CHECK-NEXT: } // 8-byte Folded Spill
13 ; CHECK-NEXT: {
14 ; CHECK-NEXT: if (p0) jump:nt .LBB0_2
15 ; CHECK-NEXT: }
16 ; CHECK-NEXT: // %bb.1: // %b1
17 ; CHECK-NEXT: {
18 ; CHECK-NEXT: call f1
19 ; CHECK-NEXT: }
20 ; CHECK-NEXT: {
21 ; CHECK-NEXT: jump .LBB0_3
22 ; CHECK-NEXT: }
23 ; CHECK-NEXT: .LBB0_2: // %b2
24 ; CHECK-NEXT: {
25 ; CHECK-NEXT: call f2
26 ; CHECK-NEXT: }
27 ; CHECK-NEXT: .LBB0_3: // %b3
28 ; CHECK-NEXT: {
29 ; CHECK-NEXT: call f3
30 ; CHECK-NEXT: r1 = add(r16,#2)
31 ; CHECK-NEXT: r0 = r17
32 ; CHECK-NEXT: }
33 ; CHECK-NEXT: {
34 ; CHECK-NEXT: r0 = #0
35 ; CHECK-NEXT: r17:16 = memd(r29+#0)
36 ; CHECK-NEXT: dealloc_return
37 ; CHECK-NEXT: } // 8-byte Folded Reload
538 b0:
639 %v0 = shl i32 1, %a2
740 %v1 = and i32 %v0, %a1
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
1 ; CHECK: tstbit
22
33 ; Function Attrs: nounwind readnone
44 define i32 @f0(i32 %a0, i32 %a1) #0 {
5 ; CHECK-LABEL: f0:
6 ; CHECK: // %bb.0: // %b0
7 ; CHECK-NEXT: {
8 ; CHECK-NEXT: p0 = tstbit(r0,r1)
9 ; CHECK-NEXT: }
10 ; CHECK-NEXT: {
11 ; CHECK-NEXT: r0 = mux(p0,#1,#0)
12 ; CHECK-NEXT: jumpr r31
13 ; CHECK-NEXT: }
514 b0:
615 %v0 = shl i32 1, %a1
716 %v1 = and i32 %v0, %a0
3636
3737 ASM_FUNCTION_AMDGPU_RE = re.compile(
3838 r'^_?(?P[^:]+):[ \t]*;+[ \t]*@(?P=func)\n[^:]*?'
39 r'(?P.*?)\n' # (body of the function)
40 # This list is incomplete
41 r'.Lfunc_end[0-9]+:\n',
42 flags=(re.M | re.S))
43
44 ASM_FUNCTION_HEXAGON_RE = re.compile(
45 r'^_?(?P[^:]+):[ \t]*//[ \t]*@(?P=func)\n[^:]*?'
3946 r'(?P.*?)\n' # (body of the function)
4047 # This list is incomplete
4148 r'.Lfunc_end[0-9]+:\n',
160167 asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
161168 return asm
162169
170 def scrub_asm_hexagon(asm, args):
171 # Scrub runs of whitespace out of the assembly, but leave the leading
172 # whitespace in place.
173 asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
174 # Expand the tabs used for indentation.
175 asm = string.expandtabs(asm, 2)
176 # Strip trailing whitespace.
177 asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
178 return asm
179
163180 def scrub_asm_powerpc(asm, args):
164181 # Scrub runs of whitespace out of the assembly, but leave the leading
165182 # whitespace in place.
238255 'r600': 'r600',
239256 'mips': 'mips',
240257 'sparc': 'sparc',
258 'hexagon': 'hexagon',
241259 }
242260 for prefix, triple in triples.items():
243261 if march.startswith(prefix):
253271 'i386': (scrub_asm_x86, ASM_FUNCTION_X86_RE),
254272 'arm64-eabi': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
255273 'aarch64': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
274 'hexagon': (scrub_asm_hexagon, ASM_FUNCTION_HEXAGON_RE),
256275 'r600': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
257276 'amdgcn': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
258277 'arm-eabi': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),