llvm.org GIT mirror llvm / 880ae36
Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57034 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 12 years ago
4 changed file(s) with 33 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
13041304 return SelectAtomic64(Node, X86::ATOMNAND6432);
13051305 case X86ISD::ATOMAND64_DAG:
13061306 return SelectAtomic64(Node, X86::ATOMAND6432);
1307 case X86ISD::ATOMSWAP64_DAG:
1308 return SelectAtomic64(Node, X86::ATOMSWAP6432);
13071309
13081310 case ISD::SMUL_LOHI:
13091311 case ISD::UMUL_LOHI: {
60686068 case ISD::ATOMIC_LOAD_SUB_16:
60696069 case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
60706070 case ISD::ATOMIC_LOAD_SUB_64: return (Subtarget->is64Bit()) ?
6071 LowerLOAD_SUB(Op,DAG) :
6072 LowerATOMIC_BINARY_64(Op,DAG,
6071 LowerLOAD_SUB(Op,DAG) :
6072 LowerATOMIC_BINARY_64(Op,DAG,
60736073 X86ISD::ATOMSUB64_DAG);
60746074 case ISD::ATOMIC_LOAD_AND_64: return LowerATOMIC_BINARY_64(Op,DAG,
60756075 X86ISD::ATOMAND64_DAG);
6076 case ISD::ATOMIC_LOAD_OR_64: return LowerATOMIC_BINARY_64(Op, DAG,
6076 case ISD::ATOMIC_LOAD_OR_64: return LowerATOMIC_BINARY_64(Op, DAG,
60776077 X86ISD::ATOMOR64_DAG);
60786078 case ISD::ATOMIC_LOAD_XOR_64: return LowerATOMIC_BINARY_64(Op,DAG,
60796079 X86ISD::ATOMXOR64_DAG);
6080 case ISD::ATOMIC_LOAD_NAND_64: return LowerATOMIC_BINARY_64(Op,DAG,
6080 case ISD::ATOMIC_LOAD_NAND_64:return LowerATOMIC_BINARY_64(Op,DAG,
60816081 X86ISD::ATOMNAND64_DAG);
60826082 case ISD::ATOMIC_LOAD_ADD_64: return LowerATOMIC_BINARY_64(Op,DAG,
60836083 X86ISD::ATOMADD64_DAG);
6084 case ISD::ATOMIC_SWAP_64: return LowerATOMIC_BINARY_64(Op,DAG,
6085 X86ISD::ATOMSWAP64_DAG);
60846086 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
60856087 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
60866088 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
64326434 // newMBB:
64336435 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
64346436 // op t5, t6 <- out1, out2, [bitinstr.val]
6437 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
64356438 // mov ECX, EBX <- t5, t6
64366439 // mov EAX, EDX <- t1, t2
64376440 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
64856488 (*MIB).addOperand(*argOpers[i]);
64866489 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
64876490 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6488 // add 4 to displacement. getImm verifies it's immediate.
6491 // add 4 to displacement.
64896492 for (int i=0; i <= lastAddrIndx-1; ++i)
64906493 (*MIB).addOperand(*argOpers[i]);
6491 MachineOperand newOp3 = MachineOperand::CreateImm(argOpers[3]->getImm()+4);
6494 MachineOperand newOp3 = *(argOpers[3]);
6495 if (newOp3.isImm())
6496 newOp3.setImm(newOp3.getImm()+4);
6497 else
6498 newOp3.setOffset(newOp3.getOffset()+4);
64926499 (*MIB).addOperand(newOp3);
64936500
64946501 // t3/4 are defined later, at the bottom of the loop
65176524 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
65186525 else
65196526 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6520 MIB.addReg(tt1);
6527 if (regOpcL != X86::MOV32rr)
6528 MIB.addReg(tt1);
65216529 (*MIB).addOperand(*argOpers[4]);
65226530 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
65236531 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
65256533 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
65266534 else
65276535 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6528 MIB.addReg(tt2);
6536 if (regOpcH != X86::MOV32rr)
6537 MIB.addReg(tt2);
65296538 (*MIB).addOperand(*argOpers[5]);
65306539
65316540 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
69426951 X86::AND32rr, X86::AND32rr,
69436952 X86::AND32ri, X86::AND32ri,
69446953 true);
6945 // FIXME carry
69466954 case X86::ATOMADD6432:
69476955 return EmitAtomicBit6432WithCustomInserter(MI, BB,
69486956 X86::ADD32rr, X86::ADC32rr,
69496957 X86::ADD32ri, X86::ADC32ri,
69506958 false);
6951 // FIXME carry
69526959 case X86::ATOMSUB6432:
69536960 return EmitAtomicBit6432WithCustomInserter(MI, BB,
69546961 X86::SUB32rr, X86::SBB32rr,
69556962 X86::SUB32ri, X86::SBB32ri,
6963 false);
6964 case X86::ATOMSWAP6432:
6965 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6966 X86::MOV32rr, X86::MOV32rr,
6967 X86::MOV32ri, X86::MOV32ri,
69566968 false);
69576969 }
69586970 }
199199 LCMPXCHG8_DAG,
200200
201201 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
202 // ATOMXOR64_DAG, ATOMNAND64_DAG - Atomic 64-bit binary operations.
202 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
203 // Atomic 64-bit binary operations.
203204 ATOMADD64_DAG,
204205 ATOMSUB64_DAG,
205206 ATOMOR64_DAG,
206207 ATOMXOR64_DAG,
207208 ATOMAND64_DAG,
208209 ATOMNAND64_DAG,
210 ATOMSWAP64_DAG,
209211
210212 // FNSTCW16m - Store FP control world into i16 memory.
211213 FNSTCW16m,
9696 [SDNPHasChain, SDNPMayStore,
9797 SDNPMayLoad, SDNPMemOperand]>;
9898 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
99 [SDNPHasChain, SDNPMayStore,
100 SDNPMayLoad, SDNPMemOperand]>;
101 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
99102 [SDNPHasChain, SDNPMayStore,
100103 SDNPMayLoad, SDNPMemOperand]>;
101104 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
27712774 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
27722775 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
27732776 "#ATOMSUB6432 PSUEDO!", []>;
2777 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2778 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2779 "#ATOMSWAP6432 PSUEDO!", []>;
27742780 }
27752781
27762782 //===----------------------------------------------------------------------===//