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Merging r314897: ------------------------------------------------------------------------ r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines [AVR] Factor out mayLoad in tablegen patterns Patch by Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315835 91177308-0d34-0410-b5e6-96231b3b80d8 Dylan McKay 1 year, 10 months ago
1 changed file(s) with 2 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
14161416 // Load program memory operations.
14171417 let canFoldAsLoad = 1,
14181418 isReMaterializable = 1,
1419 mayLoad = 1,
14191420 hasSideEffects = 0 in
14201421 {
14211422 let Defs = [R0],
14361437 Requires<[HasLPMX]>;
14371438
14381439 // Load program memory, while postincrementing the Z register.
1439 let mayLoad = 1,
1440 Defs = [R31R30] in
1440 let Defs = [R31R30] in
14411441 {
14421442 def LPMRdZPi : FLPMX<0,
14431443 1,