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AMDGPU: Add baseline test for future patch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359893 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 9 months ago
1 changed file(s) with 231 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
2
3 ---
4
5 # First operand is FI is in a VGPR, other operand is a VGPR
6 name: shrink_vgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
7 tracksRegLiveness: true
8 stack:
9 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
10 body: |
11 bb.0:
12 liveins: $vgpr0
13
14 ; GCN-LABEL: name: shrink_vgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
15 ; GCN: liveins: $vgpr0
16 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
17 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
19 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
20 %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
21 %1:vgpr_32 = COPY $vgpr0
22 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
23 S_ENDPGM 0, implicit %2
24
25 ...
26
27 ---
28
29 # First operand is a VGPR, other operand FI is in a VGPR
30 name: shrink_vgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
31 tracksRegLiveness: true
32 stack:
33 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
34 body: |
35 bb.0:
36 liveins: $vgpr0
37
38 ; GCN-LABEL: name: shrink_vgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
39 ; GCN: liveins: $vgpr0
40 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
42 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
43 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
44 %0:vgpr_32 = COPY $vgpr0
45 %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
46 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
47 S_ENDPGM 0, implicit %2
48
49 ...
50
51 ---
52
53 # First operand is FI is in an SGPR, other operand is a VGPR
54 name: shrink_vgpr_fi_sgpr_v_add_i32_e64_no_carry_out_use
55 tracksRegLiveness: true
56 stack:
57 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
58 body: |
59 bb.0:
60 liveins: $sgpr0
61
62 ; GCN-LABEL: name: shrink_vgpr_fi_sgpr_v_add_i32_e64_no_carry_out_use
63 ; GCN: liveins: $sgpr0
64 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
65 ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
66 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
67 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
68 %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
69 %1:sreg_32_xm0 = COPY $sgpr0
70 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
71 S_ENDPGM 0, implicit %2
72
73 ...
74
75 ---
76
77 # First operand is an SGPR, other operand FI is in a VGPR
78 name: shrink_sgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
79 tracksRegLiveness: true
80 stack:
81 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
82 body: |
83 bb.0:
84 liveins: $sgpr0
85
86 ; GCN-LABEL: name: shrink_sgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
87 ; GCN: liveins: $sgpr0
88 ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
89 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
90 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
91 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
92 %0:sreg_32_xm0 = COPY $sgpr0
93 %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
94 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
95 S_ENDPGM 0, implicit %2
96
97 ...
98
99 ---
100
101 # First operand is FI is in an SGPR, other operand is a VGPR
102 name: shrink_sgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
103 tracksRegLiveness: true
104 stack:
105 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
106 body: |
107 bb.0:
108 liveins: $vgpr0
109
110 ; GCN-LABEL: name: shrink_sgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
111 ; GCN: liveins: $vgpr0
112 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
113 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
114 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[COPY]], 0, implicit $exec
115 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
116 %0:sreg_32_xm0 = S_MOV_B32 %stack.0
117 %1:vgpr_32 = COPY $vgpr0
118 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
119 S_ENDPGM 0, implicit %2
120
121 ...
122
123 ---
124
125 # First operand is a VGPR, other operand FI is in an SGPR
126 name: shrink_vgpr_sgpr_fi_v_add_i32_e64_no_carry_out_use
127 tracksRegLiveness: true
128 stack:
129 - { id: 0, type: default, offset: 0, size: 64, alignment: 16}
130 body: |
131 bb.0:
132 liveins: $vgpr0
133
134 ; GCN-LABEL: name: shrink_vgpr_sgpr_fi_v_add_i32_e64_no_carry_out_use
135 ; GCN: liveins: $vgpr0
136 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
137 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
138 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[COPY]], [[S_MOV_B32_]], 0, implicit $exec
139 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
140 %0:vgpr_32 = COPY $vgpr0
141 %1:sreg_32_xm0 = S_MOV_B32 %stack.0
142 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
143 S_ENDPGM 0, implicit %2
144
145 ...
146
147 ---
148
149 # First operand is FI is in a VGPR, other operand is an inline imm in a VGPR
150 name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
151 tracksRegLiveness: true
152 stack:
153 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
154 body: |
155 bb.0:
156
157 ; GCN-LABEL: name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
158 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
159 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], 16, 0, implicit $exec
160 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
161 %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
162 %1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
163 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
164 S_ENDPGM 0, implicit %2
165
166 ...
167
168 ---
169
170 # First operand is an inline imm in a VGPR, other operand FI is in a VGPR
171 name: shrink_vgpr_imm_vgpr_fi_v_add_i32_e64_no_carry_out_use
172 tracksRegLiveness: true
173 stack:
174 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
175 body: |
176 bb.0:
177
178 ; GCN-LABEL: name: shrink_vgpr_imm_vgpr_fi_v_add_i32_e64_no_carry_out_use
179 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
180 ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 16, [[V_MOV_B32_e32_]], 0, implicit $exec
181 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
182 %0:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
183 %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
184 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
185 S_ENDPGM 0, implicit %2
186
187 ...
188
189 ---
190
191 # First operand is FI is in a VGPR, other operand is an literal constant in a VGPR
192 name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
193 tracksRegLiveness: true
194 stack:
195 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
196 body: |
197 bb.0:
198
199 ; GCN-LABEL: name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
200 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
201 ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
202 ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit-def $vcc, implicit $exec
203 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
204 %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
205 %1:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
206 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
207 S_ENDPGM 0, implicit %2
208
209 ...
210
211 ---
212
213 # First operand is a literal constant in a VGPR, other operand FI is in a VGPR
214 name: shrink_vgpr_k_vgpr_fi_v_add_i32_e64_no_carry_out_use
215 tracksRegLiveness: true
216 stack:
217 - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
218 body: |
219 bb.0:
220
221 ; GCN-LABEL: name: shrink_vgpr_k_vgpr_fi_v_add_i32_e64_no_carry_out_use
222 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
223 ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 %stack.0, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
224 ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
225 %0:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
226 %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
227 %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
228 S_ENDPGM 0, implicit %2
229
230 ...