llvm.org GIT mirror llvm / 87b02fc
[llvm-mca] Simplify code in class Scheduler. NFCI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347985 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 9 months ago
4 changed file(s) with 18 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
2323 namespace mca {
2424
2525 class InstRef;
26 class Scheduler;
2627
2728 /// A Load/Store Unit implementing a load and store queues.
2829 ///
109110 //
110111 // This class doesn't know about the latency of a load instruction. So, it
111112 // conservatively/pessimistically assumes that the latency of a load opcode
112 // matches the instruction latency.
113 // matches the instruction latency.
113114 //
114115 // FIXME: In the absence of cache misses (i.e. L1I/L1D/iTLB/dTLB hits/misses),
115116 // and load/store conflicts, the latency of a load is determined by the depth
194195 // becomes available to the users. At that point, the load no longer needs to
195196 // be tracked by the load queue.
196197 // FIXME: For simplicity, we optimistically assume a similar behavior for
197 // store instructions. In practice, store operation don't tend to leave the
198 // store instructions. In practice, store operations don't tend to leave the
198199 // store queue until they reach the 'Retired' stage (See PR39830).
199200 void onInstructionExecuted(const InstRef &IR);
200201 };
8484 /// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
8585 /// leaves the IssuedSet when it reaches the write-back stage.
8686 class Scheduler : public HardwareUnit {
87 LSUnit *LSU;
87 LSUnit &LSU;
8888
8989 // Instruction selection strategy for this Scheduler.
9090 std::unique_ptr Strategy;
116116 void promoteToReadySet(SmallVectorImpl &Ready);
117117
118118 public:
119 Scheduler(const MCSchedModel &Model, LSUnit *Lsu)
120 : LSU(Lsu), Resources(make_unique(Model)) {
121 initializeStrategy(nullptr);
122 }
123 Scheduler(const MCSchedModel &Model, LSUnit *Lsu,
119 Scheduler(const MCSchedModel &Model, LSUnit &Lsu)
120 : Scheduler(Model, Lsu, nullptr) {}
121
122 Scheduler(const MCSchedModel &Model, LSUnit &Lsu,
124123 std::unique_ptr SelectStrategy)
125 : LSU(Lsu), Resources(make_unique(Model)) {
126 initializeStrategy(std::move(SelectStrategy));
127 }
128 Scheduler(std::unique_ptr RM, LSUnit *Lsu,
124 : Scheduler(make_unique(Model), Lsu,
125 std::move(SelectStrategy)) {}
126
127 Scheduler(std::unique_ptr RM, LSUnit &Lsu,
129128 std::unique_ptr SelectStrategy)
130129 : LSU(Lsu), Resources(std::move(RM)) {
131130 initializeStrategy(std::move(SelectStrategy));
3636 auto PRF = llvm::make_unique(SM, MRI, Opts.RegisterFileSize);
3737 auto LSU = llvm::make_unique(SM, Opts.LoadQueueSize,
3838 Opts.StoreQueueSize, Opts.AssumeNoAlias);
39 auto HWS = llvm::make_unique(SM, LSU.get());
39 auto HWS = llvm::make_unique(SM, *LSU);
4040
4141 // Create the pipeline stages.
4242 auto Fetch = llvm::make_unique(SrcMgr);
5050 }
5151
5252 // Give lower priority to LSUnit stall events.
53 switch (LSU->isAvailable(IR)) {
53 switch (LSU.isAvailable(IR)) {
5454 case LSUnit::LSU_LQUEUE_FULL:
5555 return Scheduler::SC_LOAD_QUEUE_FULL;
5656 case LSUnit::LSU_SQUEUE_FULL:
7979 if (IS->isExecuting())
8080 IssuedSet.emplace_back(IR);
8181 else if (IS->isExecuted())
82 LSU->onInstructionExecuted(IR);
82 LSU.onInstructionExecuted(IR);
8383 }
8484
8585 // Release the buffered resources and issue the instruction.
169169 }
170170
171171 // Instruction IR has completed execution.
172 LSU->onInstructionExecuted(IR);
172 LSU.onInstructionExecuted(IR);
173173 Executed.emplace_back(IR);
174174 ++RemovedElements;
175175 IR.invalidate();
212212 // If necessary, reserve queue entries in the load-store unit (LSU).
213213 bool IsMemOp = Desc.MayLoad || Desc.MayStore;
214214 if (IsMemOp)
215 LSU->dispatch(IR);
215 LSU.dispatch(IR);
216216
217217 if (!isReady(IR)) {
218218 LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
237237 bool Scheduler::isReady(const InstRef &IR) const {
238238 const InstrDesc &Desc = IR.getInstruction()->getDesc();
239239 bool IsMemOp = Desc.MayLoad || Desc.MayStore;
240 return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
240 return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR));
241241 }
242242
243243 } // namespace mca