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Merging r260495: ------------------------------------------------------------------------ r260495 | Matthew.Arsenault | 2016-02-10 22:15:39 -0800 (Wed, 10 Feb 2016) | 9 lines AMDGPU: Fix constant bus use check with subregisters If the two operands to an instruction were both subregisters of the same super register, it would incorrectly think this counted as the same constant bus use. This fixes the verifier error in fmin_legacy.ll which was missing -verify-machineinstrs. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271640 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
3 changed file(s) with 37 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
18061806 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
18071807 const MachineOperand *MO) const {
18081808 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1809 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1809 const MCInstrDesc &InstDesc = MI->getDesc();
18101810 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
18111811 const TargetRegisterClass *DefinedRC =
18121812 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
18151815
18161816 if (isVALU(*MI) &&
18171817 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1818 unsigned SGPRUsed =
1819 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1818
1819 RegSubRegPair SGPRUsed;
1820 if (MO->isReg())
1821 SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg());
1822
18201823 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
18211824 if (i == OpIdx)
18221825 continue;
18231826 const MachineOperand &Op = MI->getOperand(i);
1824 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1827 if (Op.isReg() &&
1828 (Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) &&
18251829 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
18261830 return false;
18271831 }
None ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
1 ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
1 ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
22 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
33
44 ; FIXME: Should replace unsafe-fp-math with no signed zeros.
None ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
1 ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
1 ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
22 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
33
44 ; FIXME: Should replace unsafe-fp-math with no signed zeros.
55
66 declare i32 @llvm.r600.read.tidig.x() #1
77
8 ; FUNC-LABEL: @test_fmin_legacy_f32
8 ; The two inputs to the instruction are different SGPRs from the same
9 ; super register, so we can't fold both SGPR operands even though they
10 ; are both the same register.
11
12 ; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32:
913 ; EG: MIN *
10 ; SI-SAFE: v_min_legacy_f32_e64
11 ; SI-NONAN: v_min_f32_e64
12 define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {
14 ; SI-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
15 ; SI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
16 define void @s_test_fmin_legacy_subreg_inputs_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {
1317 %r0 = extractelement <4 x float> %reg0, i32 0
1418 %r1 = extractelement <4 x float> %reg0, i32 1
1519 %r2 = fcmp uge float %r0, %r1
1923 ret void
2024 }
2125
26 ; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:
27 ; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
28 ; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
29
30 ; SI-SAFE-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]
31 ; SI-NONAN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
32
33 ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[VA]]
34 ; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[VB]]
35
36 define void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 {
37 %cmp = fcmp ule float %a, %b
38 %val = select i1 %cmp, float %a, float %b
39 store float %val, float addrspace(1)* %out, align 4
40 ret void
41 }
42
2243 ; FUNC-LABEL: @test_fmin_legacy_ule_f32
2344 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
2445 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4