llvm.org GIT mirror llvm / 870f78a
Merging r226597: ------------------------------------------------------------------------ r226597 | thomas.stellard | 2015-01-20 14:33:04 -0500 (Tue, 20 Jan 2015) | 5 lines R600/SI: Add subtarget feature to enable VGPR spilling for all shader types This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@226728 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
9 changed file(s) with 36 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
9090 "FlatAddressSpace",
9191 "true",
9292 "Support flat address space">;
93
94 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
95 "EnableVGPRSpilling",
96 "true",
97 "Enable spilling of VGPRs to scratch memory">;
9398
9499 class SubtargetFeatureFetchLimit :
95100 SubtargetFeature <"fetch"#Value,
420420
421421 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
422422 const SIProgramInfo &KernelInfo) {
423 const AMDGPUSubtarget &STM = TM.getSubtarget();
423424 const SIMachineFunctionInfo *MFI = MF.getInfo();
424425 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
425426
440441 OutStreamer.EmitIntValue(RsrcReg, 4);
441442 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
442443 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
444 if (STM.isVGPRSpillingEnabled(MFI)) {
445 OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
446 OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
447 }
443448 }
444449
445450 if (MFI->getShaderType() == ShaderType::PIXEL) {
1717 #include "R600MachineScheduler.h"
1818 #include "SIISelLowering.h"
1919 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
2021 #include "llvm/ADT/SmallString.h"
2122
2223 using namespace llvm;
7778 FlatAddressSpace(false), EnableIRStructurizer(true),
7879 EnablePromoteAlloca(false), EnableIfCvt(true),
7980 EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
81 EnableVGPRSpilling(false),
8082 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
8183 FrameLowering(TargetFrameLowering::StackGrowsUp,
8284 64 * 16, // Maximum stack alignment (long16)
112114 case SEA_ISLANDS: return 12;
113115 }
114116 }
117
118 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
119 const SIMachineFunctionInfo *MFI) const {
120 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
121 }
2828 #include "AMDGPUGenSubtargetInfo.inc"
2929
3030 namespace llvm {
31
32 class SIMachineFunctionInfo;
3133
3234 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
3335
6264 unsigned WavefrontSize;
6365 bool CFALUBug;
6466 int LocalMemorySize;
67 bool EnableVGPRSpilling;
6568
6669 const DataLayout DL;
6770 AMDGPUFrameLowering FrameLowering;
223226 bool isAmdHsaOS() const {
224227 return TargetTriple.getOS() == Triple::AMDHSA;
225228 }
229 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
226230 };
227231
228232 } // End namespace llvm
162162 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
163163 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
164164
165 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
166 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
167
165168
166169 #endif
586586 }
587587
588588 InVals.push_back(Val);
589 }
590
591 if (Info->getShaderType() != ShaderType::COMPUTE) {
592 unsigned ScratchIdx = CCInfo.getFirstUnallocated(
593 AMDGPU::SGPR_32RegClass.begin(), AMDGPU::SGPR_32RegClass.getNumRegs());
594 Info->ScratchOffsetReg = AMDGPU::SGPR_32RegClass.getRegister(ScratchIdx);
589595 }
590596 return Chain;
591597 }
429429 return AMDGPU::COPY;
430430 }
431431
432 static bool shouldTryToSpillVGPRs(MachineFunction *MF) {
433
434 SIMachineFunctionInfo *MFI = MF->getInfo();
435
436 // FIXME: Implement spilling for other shader types.
437 return MFI->getShaderType() == ShaderType::COMPUTE;
438
439 }
440
441432 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
442433 MachineBasicBlock::iterator MI,
443434 unsigned SrcReg, bool isKill,
461452 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
462453 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
463454 }
464 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
455 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
465456 MFI->setHasSpilledVGPRs();
466457
467458 switch(RC->getSize() * 8) {
498489 const TargetRegisterClass *RC,
499490 const TargetRegisterInfo *TRI) const {
500491 MachineFunction *MF = MBB.getParent();
492 const SIMachineFunctionInfo *MFI = MF->getInfo();
501493 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
502494 DebugLoc DL = MBB.findDebugLoc(MI);
503495 int Opcode = -1;
510502 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
511503 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
512504 }
513 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
505 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
514506 switch(RC->getSize() * 8) {
515507 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
516508 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
4949 unsigned NumUserSGPRs;
5050 std::map LaneVGPRs;
5151 unsigned LDSWaveSpillSize;
52 unsigned ScratchOffsetReg;
5253 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
5354 unsigned getTIDReg() const { return TIDReg; };
5455 void setTIDReg(unsigned Reg) { TIDReg = Reg; }
423423 case SIRegisterInfo::TGID_Z:
424424 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
425425 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
426 if (MFI->getShaderType() != ShaderType::COMPUTE)
427 return MFI->ScratchOffsetReg;
426428 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
427429 case SIRegisterInfo::SCRATCH_PTR:
428430 return AMDGPU::SGPR2_SGPR3;