llvm.org GIT mirror llvm / 86e5f7b
It's ok to spill a tGPR register as long as it's still allocated a low register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
2 changed file(s) with 54 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
9090 case ARM::tMOVgpr2gpr: {
9191 if (OpNum == 0) { // move -> store
9292 unsigned SrcReg = MI->getOperand(1).getReg();
93 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
93 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
94 !isARMLowRegister(SrcReg))
9495 // tSpill cannot take a high register operand.
9596 return false;
9697 } else { // move -> load
9798 unsigned DstReg = MI->getOperand(0).getReg();
98 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
99 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
100 !isARMLowRegister(DstReg))
99101 // tRestore cannot target a high register operand.
100102 return false;
101103 }
113115 DebugLoc DL = DebugLoc::getUnknownLoc();
114116 if (I != MBB.end()) DL = I->getDebugLoc();
115117
116 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
118 assert((RC == ARM::tGPRRegisterClass ||
119 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
120 isARMLowRegister(SrcReg))) && "Unknown regclass!");
117121
118122 if (RC == ARM::tGPRRegisterClass) {
119123 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
129133 DebugLoc DL = DebugLoc::getUnknownLoc();
130134 if (I != MBB.end()) DL = I->getDebugLoc();
131135
132 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
136 assert((RC == ARM::tGPRRegisterClass ||
137 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
138 isARMLowRegister(DestReg))) && "Unknown regclass!");
133139
134140 if (RC == ARM::tGPRRegisterClass) {
135141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
211217 if (OpNum == 0) { // move -> store
212218 unsigned SrcReg = MI->getOperand(1).getReg();
213219 bool isKill = MI->getOperand(1).isKill();
214 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
220 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
221 !isARMLowRegister(SrcReg))
215222 // tSpill cannot take a high register operand.
216223 break;
217224 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
219226 .addFrameIndex(FI).addImm(0));
220227 } else { // move -> load
221228 unsigned DstReg = MI->getOperand(0).getReg();
222 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
229 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
230 !isARMLowRegister(DstReg))
223231 // tRestore cannot target a high register operand.
224232 break;
225233 bool isDead = MI->getOperand(0).isDead();
0 ; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin
1
2 %struct.vorbis_comment = type { i8**, i32*, i32, i8* }
3 @.str16 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1]
4
5 declare arm_apcscc i8* @__strcpy_chk(i8*, i8*, i32) nounwind
6
7 declare arm_apcscc i8* @__strcat_chk(i8*, i8*, i32) nounwind
8
9 define arm_apcscc i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind {
10 entry:
11 %0 = alloca i8, i32 undef, align 4 ; [#uses=2]
12 %1 = call arm_apcscc i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; [#uses=0]
13 %2 = call arm_apcscc i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; [#uses=0]
14 %3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; [#uses=1]
15 br label %bb11
16
17 bb6: ; preds = %bb11
18 %4 = load i8*** %3, align 4 ; [#uses=1]
19 %scevgep = getelementptr i8** %4, i32 %8 ; [#uses=1]
20 %5 = load i8** %scevgep, align 4 ; [#uses=1]
21 br label %bb3.i
22
23 bb3.i: ; preds = %bb3.i, %bb6
24 %scevgep7.i = getelementptr i8* %5, i32 0 ; [#uses=1]
25 %6 = load i8* %scevgep7.i, align 1 ; [#uses=0]
26 br i1 undef, label %bb3.i, label %bb10
27
28 bb10: ; preds = %bb3.i
29 %7 = add i32 %8, 1 ; [#uses=1]
30 br label %bb11
31
32 bb11: ; preds = %bb10, %entry
33 %8 = phi i32 [ %7, %bb10 ], [ 0, %entry ] ; [#uses=3]
34 %9 = icmp sgt i32 undef, %8 ; [#uses=1]
35 br i1 %9, label %bb6, label %bb13
36
37 bb13: ; preds = %bb11
38 ret i8* null
39 }