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Merging r276435: ------------------------------------------------------------------------ r276435 | arsenm | 2016-07-22 10:01:21 -0700 (Fri, 22 Jul 2016) | 4 lines AMDGPU: Fix i1 fp_to_int R600's i1 fp_to_uint selected but was incorrect according to what instcombine constant folds to. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277082 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 4 years ago
8 changed file(s) with 131 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
419419 int PI = 0x40490fdb;
420420 int TWO_PI_INV = 0x3e22f983;
421421 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
422 int FP32_ONE = 0x3f800000;
422423 int FP32_NEG_ONE = 0xbf800000;
423 int FP32_ONE = 0x3f800000;
424424 int FP64_ONE = 0x3ff0000000000000;
425 int FP64_NEG_ONE = 0xbff0000000000000;
425426 }
426427 def CONST : Constants;
427428
121121 setOperationAction(ISD::SETCC, MVT::i32, Expand);
122122 setOperationAction(ISD::SETCC, MVT::f32, Expand);
123123 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
124 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
124125 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
125126 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
126127
831832 return;
832833 case ISD::FP_TO_UINT:
833834 if (N->getValueType(0) == MVT::i1) {
834 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
835 Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));
835836 return;
836837 }
837838 // Fall-through. Since we don't care about out of bounds values
838839 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
839840 // considers some extra cases which are not necessary here.
840841 case ISD::FP_TO_SINT: {
842 if (N->getValueType(0) == MVT::i1) {
843 Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));
844 return;
845 }
846
841847 SDValue Result;
842848 if (expandFP_TO_SINT(N, Result, DAG))
843849 Results.push_back(Result);
10511057 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
10521058 }
10531059
1054 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1060 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
10551061 SDLoc DL(Op);
10561062 return DAG.getNode(
10571063 ISD::SETCC,
10581064 DL,
10591065 MVT::i1,
1060 Op, DAG.getConstantFP(0.0f, DL, MVT::f32),
1061 DAG.getCondCode(ISD::SETNE)
1062 );
1066 Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
1067 DAG.getCondCode(ISD::SETEQ));
1068 }
1069
1070 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
1071 SDLoc DL(Op);
1072 return DAG.getNode(
1073 ISD::SETCC,
1074 DL,
1075 MVT::i1,
1076 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
1077 DAG.getCondCode(ISD::SETEQ));
10631078 }
10641079
10651080 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
7171
7272 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
7373 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
74 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
7576
7677 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
7778 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
33903390 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
33913391 >;
33923392
3393 class FPToI1Pat : Pat <
3394 (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
3395 (i1 (Inst 0, KOne, $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))
3396 >;
3397
3398 def : FPToI1Pat;
3399 def : FPToI1Pat;
3400 def : FPToI1Pat;
3401 def : FPToI1Pat;
3402
33933403 // If we need to perform a logical operation on i1 values, we need to
33943404 // use vector comparisons since there is only one SCC register. Vector
33953405 // comparisions still write to a pair of SGPRs, so treat these as
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
11 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
22
3 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
3 declare i32 @llvm.amdgcn.workitem.id.x() #1
4 declare double @llvm.fabs.f64(double) #1
45
56 ; FUNC-LABEL: @fp_to_sint_f64_i32
67 ; SI: v_cvt_i32_f64_e32
5354 store i64 %cast, i64 addrspace(1)* %out, align 8
5455 ret void
5556 }
57
58 ; FUNC-LABEL: {{^}}fp_to_sint_f64_to_i1:
59 ; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{\[[0-9]+:[0-9]+\]}}
60 define void @fp_to_sint_f64_to_i1(i1 addrspace(1)* %out, double %in) #0 {
61 %conv = fptosi double %in to i1
62 store i1 %conv, i1 addrspace(1)* %out
63 ret void
64 }
65
66 ; FUNC-LABEL: {{^}}fp_to_sint_fabs_f64_to_i1:
67 ; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, |s{{\[[0-9]+:[0-9]+\]}}|
68 define void @fp_to_sint_fabs_f64_to_i1(i1 addrspace(1)* %out, double %in) #0 {
69 %in.fabs = call double @llvm.fabs.f64(double %in)
70 %conv = fptosi double %in.fabs to i1
71 store i1 %conv, i1 addrspace(1)* %out
72 ret void
73 }
74
75 attributes #0 = { nounwind }
76 attributes #1 = { nounwind readnone }
11 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
22 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
33
4 declare float @llvm.fabs.f32(float) #0
4 declare float @llvm.fabs.f32(float) #1
55
66 ; FUNC-LABEL: {{^}}fp_to_sint_i32:
77 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
1616 ; FUNC-LABEL: {{^}}fp_to_sint_i32_fabs:
1717 ; SI: v_cvt_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
1818 define void @fp_to_sint_i32_fabs(i32 addrspace(1)* %out, float %in) {
19 %in.fabs = call float @llvm.fabs.f32(float %in) #0
19 %in.fabs = call float @llvm.fabs.f32(float %in)
2020 %conv = fptosi float %in.fabs to i32
2121 store i32 %conv, i32 addrspace(1)* %out
2222 ret void
226226 ret void
227227 }
228228
229 attributes #0 = { nounwind readnone }
229 ; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i1:
230 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
231
232 ; EG: AND_INT
233 ; EG: SETE_DX10 {{[*]?}} T{{[0-9]+}}.{{[XYZW]}}, KC0[2].Z, literal.y,
234 ; EG-NEXT: -1082130432(-1.000000e+00)
235 define void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
236 %conv = fptosi float %in to i1
237 store i1 %conv, i1 addrspace(1)* %out
238 ret void
239 }
240
241 ; FUNC-LABEL: {{^}}fp_to_uint_fabs_f32_to_i1:
242 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, |s{{[0-9]+}}|
243 define void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
244 %in.fabs = call float @llvm.fabs.f32(float %in)
245 %conv = fptosi float %in.fabs to i1
246 store i1 %conv, i1 addrspace(1)* %out
247 ret void
248 }
249
250 attributes #0 = { nounwind }
251 attributes #1 = { nounwind readnone }
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
11 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
22
3 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
3 declare i32 @llvm.amdgcn.workitem.id.x() #1
4 declare double @llvm.fabs.f64(double) #1
45
56 ; SI-LABEL: {{^}}fp_to_uint_i32_f64:
67 ; SI: v_cvt_u32_f64_e32
6768 store <4 x i64> %cast, <4 x i64> addrspace(1)* %out, align 32
6869 ret void
6970 }
71
72 ; FUNC-LABEL: {{^}}fp_to_uint_f64_to_i1:
73 ; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{\[[0-9]+:[0-9]+\]}}
74 define void @fp_to_uint_f64_to_i1(i1 addrspace(1)* %out, double %in) #0 {
75 %conv = fptoui double %in to i1
76 store i1 %conv, i1 addrspace(1)* %out
77 ret void
78 }
79
80 ; FUNC-LABEL: {{^}}fp_to_uint_fabs_f64_to_i1:
81 ; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, |s{{\[[0-9]+:[0-9]+\]}}|
82 define void @fp_to_uint_fabs_f64_to_i1(i1 addrspace(1)* %out, double %in) #0 {
83 %in.fabs = call double @llvm.fabs.f64(double %in)
84 %conv = fptoui double %in.fabs to i1
85 store i1 %conv, i1 addrspace(1)* %out
86 ret void
87 }
88
89 attributes #0 = { nounwind }
90 attributes #1 = { nounwind readnone }
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC
1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
3
4 declare float @llvm.fabs.f32(float) #1
35
46 ; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i32:
57 ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
214216 store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
215217 ret void
216218 }
219
220
221 ; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i1:
222 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
223
224 ; EG: AND_INT
225 ; EG: SETE_DX10 {{[*]?}} T{{[0-9]+}}.{{[XYZW]}}, KC0[2].Z, 1.0,
226 define void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
227 %conv = fptoui float %in to i1
228 store i1 %conv, i1 addrspace(1)* %out
229 ret void
230 }
231
232 ; FUNC-LABEL: {{^}}fp_to_uint_fabs_f32_to_i1:
233 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, |s{{[0-9]+}}|
234 define void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
235 %in.fabs = call float @llvm.fabs.f32(float %in)
236 %conv = fptoui float %in.fabs to i1
237 store i1 %conv, i1 addrspace(1)* %out
238 ret void
239 }
240
241 attributes #0 = { nounwind }
242 attributes #1 = { nounwind readnone }