llvm.org GIT mirror llvm / 86aef0a
On PowerPC64, integer return values (as well as arguments) are supposed to be extended to a full register. This is modeled in the IR by marking the return value (or argument) with a signext or zeroext attribute. However, while these attributes are respected for function arguments, they are currently ignored for function return values by the PowerPC back-end. This patch updates PPCCallingConv.td to ask for the promotion to i64, and fixes LowerReturn and LowerCallResult to implement it. The new test case verifies that both arguments and return values are properly extended when passing them; and also that the optimizers understand incoming argument and return values are in fact guaranteed by the ABI to be extended. The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll, since the test case used a "ret" instruction to create a use of an i32 value at the end of the function (to set up data flow as required for what the test is intended to test). Since there's now an implicit promotion to i64, that data flow no longer works as expected. To fix this, this patch now adds an extra "add" to ensure we have an appropriate use of the i32 value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167396 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 7 years ago
4 changed file(s) with 149 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 /// CCIfSubtarget - Match if the current subtarget has a feature F.
15 class CCIfSubtarget
16 : CCIf().", F), A>;
17
1418 //===----------------------------------------------------------------------===//
1519 // Return Value Calling Convention
1620 //===----------------------------------------------------------------------===//
1721
1822 // Return-value convention for PowerPC
1923 def RetCC_PPC : CallingConv<[
24 // On PPC64, integer return values are always promoted to i64
25 CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType>>,
26
2027 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
2128 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
2229
31763176 // Copy all of the result registers out of their specified physreg.
31773177 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
31783178 CCValAssign &VA = RVLocs[i];
3179 EVT VT = VA.getValVT();
31803179 assert(VA.isRegLoc() && "Can only return in registers!");
3181 Chain = DAG.getCopyFromReg(Chain, dl,
3182 VA.getLocReg(), VT, InFlag).getValue(1);
3183 InVals.push_back(Chain.getValue(0));
3184 InFlag = Chain.getValue(2);
3180
3181 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3182 VA.getLocReg(), VA.getLocVT(), InFlag);
3183 Chain = Val.getValue(1);
3184 InFlag = Val.getValue(2);
3185
3186 switch (VA.getLocInfo()) {
3187 default: llvm_unreachable("Unknown loc info!");
3188 case CCValAssign::Full: break;
3189 case CCValAssign::AExt:
3190 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3191 break;
3192 case CCValAssign::ZExt:
3193 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3194 DAG.getValueType(VA.getValVT()));
3195 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3196 break;
3197 case CCValAssign::SExt:
3198 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3199 DAG.getValueType(VA.getValVT()));
3200 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3201 break;
3202 }
3203
3204 InVals.push_back(Val);
31853205 }
31863206
31873207 return Chain;
43154335 for (unsigned i = 0; i != RVLocs.size(); ++i) {
43164336 CCValAssign &VA = RVLocs[i];
43174337 assert(VA.isRegLoc() && "Can only return in registers!");
4318 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
4319 OutVals[i], Flag);
4338
4339 SDValue Arg = OutVals[i];
4340
4341 switch (VA.getLocInfo()) {
4342 default: llvm_unreachable("Unknown loc info!");
4343 case CCValAssign::Full: break;
4344 case CCValAssign::AExt:
4345 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4346 break;
4347 case CCValAssign::ZExt:
4348 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4349 break;
4350 case CCValAssign::SExt:
4351 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4352 break;
4353 }
4354
4355 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
43204356 Flag = Chain.getValue(1);
43214357 }
43224358
1212 store volatile i32 %D, i32* %P
1313 ; Reuse low bits of extended register, don't extend live range of SUM.
1414 ; CHECK: stw [[EXT]]
15 ret i32 %D
15 %R = add i32 %D, %D
16 ret i32 %R
1617 }
0 ; Verify that i32 argument/return values are extended to i64
1
2 ; RUN: llc < %s | FileCheck %s
3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
4 target triple = "powerpc64-unknown-linux-gnu"
5
6 @si = common global i32 0, align 4
7 @ui = common global i32 0, align 4
8
9 declare void @arg_si(i32 signext)
10 declare void @arg_ui(i32 zeroext)
11
12 declare signext i32 @ret_si()
13 declare zeroext i32 @ret_ui()
14
15 define void @pass_arg_si() nounwind {
16 entry:
17 %0 = load i32* @si, align 4
18 tail call void @arg_si(i32 signext %0) nounwind
19 ret void
20 }
21 ; CHECK: @pass_arg_si
22 ; CHECK: lwa 3,
23 ; CHECK: bl arg_si
24
25 define void @pass_arg_ui() nounwind {
26 entry:
27 %0 = load i32* @ui, align 4
28 tail call void @arg_ui(i32 zeroext %0) nounwind
29 ret void
30 }
31 ; CHECK: @pass_arg_ui
32 ; CHECK: lwz 3,
33 ; CHECK: bl arg_ui
34
35 define i64 @use_arg_si(i32 signext %x) nounwind readnone {
36 entry:
37 %conv = sext i32 %x to i64
38 ret i64 %conv
39 }
40 ; CHECK: @use_arg_si
41 ; CHECK: %entry
42 ; CHECK-NEXT: blr
43
44 define i64 @use_arg_ui(i32 zeroext %x) nounwind readnone {
45 entry:
46 %conv = zext i32 %x to i64
47 ret i64 %conv
48 }
49 ; CHECK: @use_arg_ui
50 ; CHECK: %entry
51 ; CHECK-NEXT: blr
52
53 define signext i32 @pass_ret_si() nounwind readonly {
54 entry:
55 %0 = load i32* @si, align 4
56 ret i32 %0
57 }
58 ; CHECK: @pass_ret_si
59 ; CHECK: lwa 3,
60 ; CHECK: blr
61
62 define zeroext i32 @pass_ret_ui() nounwind readonly {
63 entry:
64 %0 = load i32* @ui, align 4
65 ret i32 %0
66 }
67 ; CHECK: @pass_ret_ui
68 ; CHECK: lwz 3,
69 ; CHECK: blr
70
71 define i64 @use_ret_si() nounwind {
72 entry:
73 %call = tail call signext i32 @ret_si() nounwind
74 %conv = sext i32 %call to i64
75 ret i64 %conv
76 }
77 ; CHECK: @use_ret_si
78 ; CHECK: bl ret_si
79 ; This is to verify the return register (3) set up by the ret_si
80 ; call is passed on unmodified as return value of use_ret_si.
81 ; CHECK-NOT: 3
82 ; CHECK: blr
83
84 define i64 @use_ret_ui() nounwind {
85 entry:
86 %call = tail call zeroext i32 @ret_ui() nounwind
87 %conv = zext i32 %call to i64
88 ret i64 %conv
89 }
90 ; CHECK: @use_ret_ui
91 ; CHECK: bl ret_ui
92 ; This is to verify the return register (3) set up by the ret_ui
93 ; call is passed on unmodified as return value of use_ret_ui.
94 ; CHECK-NOT: 3
95 ; CHECK: blr
96