llvm.org GIT mirror llvm / 86a87d9
Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a" because it breaks some buildbots. This reverts commit 180816. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8 Adrian Prantl 7 years ago
14 changed file(s) with 45 addition(s) and 222 deletion(s). Raw diff Collapse all Expand all
334334 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
335335 }
336336
337 /// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
338 /// for either a value in a register or a register-indirect+offset
339 /// address. The convention is that a DBG_VALUE is indirect iff the
340 /// second operand is an immediate.
341 ///
342 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
343 DebugLoc DL,
344 const MCInstrDesc &MCID,
345 bool IsIndirect,
346 unsigned Reg,
347 unsigned Offset,
348 const MDNode *MD) {
349 if (IsIndirect)
350 return BuildMI(MF, DL, MCID)
351 .addReg(Reg, RegState::Debug)
352 .addImm(Offset)
353 .addMetadata(MD);
354 else {
355 assert(Offset == 0 && "A direct address cannot have an offset.");
356 return BuildMI(MF, DL, MCID)
357 .addReg(Reg, RegState::Debug)
358 .addReg(0U, RegState::Debug)
359 .addMetadata(MD);
360 }
361 }
362
363 /// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
364 /// for either a value in a register or a register-indirect+offset
365 /// address and inserts it at position I.
366 ///
367 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
368 MachineBasicBlock::iterator I,
369 DebugLoc DL,
370 const MCInstrDesc &MCID,
371 bool IsIndirect,
372 unsigned Reg,
373 unsigned Offset,
374 const MDNode *MD) {
375 MachineFunction &MF = *BB.getParent();
376 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);
377 BB.insert(I, MI);
378 return MachineInstrBuilder(MF, MI);
379 }
380
381
382337 inline unsigned getDefRegState(bool B) {
383338 return B ? RegState::Define : 0;
384339 }
596596 OS << AP.TM.getRegisterInfo()->getName(MI->getOperand(0).getReg());
597597 }
598598
599 // It's only an offset if it's an immediate.
600 if (MI->getOperand(1).isImm())
601 OS << '+' << MI->getOperand(1).getImm();
599 OS << '+' << MI->getOperand(1).getImm();
602600 // NOTE: Want this comment at start of line, don't emit with AddComment.
603601 AP.OutStreamer.EmitRawText(OS.str());
604602 return true;
11141114 assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
11151115 return MI->getNumOperands() == 3 &&
11161116 MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
1117 (MI->getOperand(1).isImm() ||
1118 (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));
1117 MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
11191118 }
11201119
11211120 // Get .debug_loc entry for the instruction range starting at MI.
11291128 MachineLocation MLoc = Asm->getDebugValueLocation(MI);
11301129 return DotDebugLocEntry(FLabel, SLabel, MLoc, Var);
11311130 }
1132 if (MI->getOperand(0).isReg()) {
1131 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {
11331132 MachineLocation MLoc;
1134 // If the second operand is an immediate, this is a
1135 // register-indirect address.
1136 if (!MI->getOperand(1).isImm())
1133 // TODO: Currently an offset of 0 in a DBG_VALUE means
1134 // we need to generate a direct register value.
1135 // There is no way to specify an indirect value with offset 0.
1136 if (MI->getOperand(1).getImm() == 0)
11371137 MLoc.set(MI->getOperand(0).getReg());
11381138 else
11391139 MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
107107 class UserValue {
108108 const MDNode *variable; ///< The debug info variable we are part of.
109109 unsigned offset; ///< Byte offset into variable.
110 bool Indirect; ///< true if this is a register-indirect+offset value.
111110 DebugLoc dl; ///< The debug location for the variable. This is
112111 ///< used by dwarf writer to find lexical scope.
113112 UserValue *leader; ///< Equivalence class leader.
134133
135134 public:
136135 /// UserValue - Create a new UserValue.
137 UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L,
136 UserValue(const MDNode *var, unsigned o, DebugLoc L,
138137 LocMap::Allocator &alloc)
139 : variable(var), offset(o), Indirect(i), dl(L), leader(this),
140 next(0), locInts(alloc)
138 : variable(var), offset(o), dl(L), leader(this), next(0), locInts(alloc)
141139 {}
142140
143141 /// getLeader - Get the leader of this value's equivalence class.
300298 UVMap userVarMap;
301299
302300 /// getUserValue - Find or create a UserValue.
303 UserValue *getUserValue(const MDNode *Var, unsigned Offset,
304 bool Indirect, DebugLoc DL);
301 UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc DL);
305302
306303 /// lookupVirtReg - Find the EC leader for VirtReg or null.
307304 UserValue *lookupVirtReg(unsigned VirtReg);
416413 }
417414
418415 UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,
419 bool Indirect, DebugLoc DL) {
416 DebugLoc DL) {
420417 UserValue *&Leader = userVarMap[Var];
421418 if (Leader) {
422419 UserValue *UV = Leader->getLeader();
426423 return UV;
427424 }
428425
429 UserValue *UV = new UserValue(Var, Offset, Indirect, DL, allocator);
426 UserValue *UV = new UserValue(Var, Offset, DL, allocator);
430427 userValues.push_back(UV);
431428 Leader = UserValue::merge(Leader, UV);
432429 return UV;
447444 bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
448445 // DBG_VALUE loc, offset, variable
449446 if (MI->getNumOperands() != 3 ||
450 !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) ||
451 !MI->getOperand(2).isMetadata()) {
447 !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
452448 DEBUG(dbgs() << "Can't handle " << *MI);
453449 return false;
454450 }
455451
456452 // Get or create the UserValue for (variable,offset).
457 bool Indirect = MI->getOperand(1).isImm();
458 unsigned Offset = Indirect ? MI->getOperand(1).getImm() : 0;
453 unsigned Offset = MI->getOperand(1).getImm();
459454 const MDNode *Var = MI->getOperand(2).getMetadata();
460 UserValue *UV = getUserValue(Var, Offset, Indirect, MI->getDebugLoc());
455 UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());
461456 UV->addDef(Idx, MI->getOperand(0));
462457 return true;
463458 }
928923 // Frame index locations may require a target callback.
929924 if (Loc.isFI()) {
930925 MachineInstr *MI = TII.emitFrameIndexDebugValue(*MBB->getParent(),
931 Loc.getIndex(),
932 offset, variable,
926 Loc.getIndex(), offset, variable,
933927 findDebugLoc());
934928 if (MI) {
935929 MBB->insert(I, MI);
937931 }
938932 }
939933 // This is not a frame index, or the target is happy with a standard FI.
940
941 if (Loc.isReg())
942 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
943 Indirect, Loc.getReg(), offset, variable);
944 else
945 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
946 .addOperand(Loc).addImm(offset).addMetadata(variable);
934 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
935 .addOperand(Loc).addImm(offset).addMetadata(variable);
947936 }
948937
949938 void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
640640 Reg = FuncInfo.InitializeRegForValue(Address);
641641
642642 if (Reg)
643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
644 TII.get(TargetOpcode::DBG_VALUE),
645 DI->getAddress()->getType()->isPointerTy(),
646 Reg, Offset, DI->getVariable());
647 else
643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
644 TII.get(TargetOpcode::DBG_VALUE))
645 .addReg(Reg, RegState::Debug).addImm(Offset)
646 .addMetadata(DI->getVariable());
647 else
648648 // We can't yet handle anything else here because it would require
649649 // generating code, thus altering codegen because of debug info.
650650 DEBUG(dbgs() << "Dropping debug info for " << DI);
675675 .addFPImm(CF).addImm(DI->getOffset())
676676 .addMetadata(DI->getVariable());
677677 } else if (unsigned Reg = lookUpRegForValue(V)) {
678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, DI->getOffset() != 0,
679 Reg, DI->getOffset(), DI->getVariable());
678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
679 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
680 .addMetadata(DI->getVariable());
680681 } else {
681682 // We can't yet handle anything else here because it would require
682683 // generating code, thus altering codegen because of debug info.
677677 MIB.addReg(0U);
678678 }
679679
680 if (Offset != 0) // Indirect addressing.
681 MIB.addImm(Offset);
682 else
683 MIB.addReg(0U, RegState::Debug);
684
685 MIB.addMetadata(MDPtr);
686
680 MIB.addImm(Offset).addMetadata(MDPtr);
687681 return &*MIB;
688682 }
689683
44124412 return false;
44134413
44144414 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4415 TII->get(TargetOpcode::DBG_VALUE),
4416 Offset != 0,
4417 Reg, Offset, Variable);
4415 TII->get(TargetOpcode::DBG_VALUE))
4416 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
44184417 FuncInfo.ArgDbgValues.push_back(&*MIB);
44194418 return true;
44204419 }
417417 MachineBasicBlock::iterator InsertPos = Def;
418418 const MDNode *Variable =
419419 MI->getOperand(MI->getNumOperands()-1).getMetadata();
420 unsigned Offset = 0;
421 if (MI->getOperand(1).isImm())
422 Offset = MI->getOperand(1).getImm();
420 unsigned Offset = MI->getOperand(1).getImm();
423421 // Def is never a terminator here, so it is ok to increment InsertPos.
424422 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
425 TII.get(TargetOpcode::DBG_VALUE),
426 MI->getOperand(1).isReg(),
427 LDI->second, Offset, Variable);
423 TII.get(TargetOpcode::DBG_VALUE))
424 .addReg(LDI->second, RegState::Debug)
425 .addImm(Offset).addMetadata(Variable);
428426
429427 // If this vreg is directly copied into an exported register then
430428 // that COPY instructions also need DBG_VALUE, if it is the only
443441 if (CopyUseMI) {
444442 MachineInstr *NewMI =
445443 BuildMI(*MF, CopyUseMI->getDebugLoc(),
446 TII.get(TargetOpcode::DBG_VALUE),
447 Offset!=0,
448 CopyUseMI->getOperand(0).getReg(),
449 Offset, Variable);
444 TII.get(TargetOpcode::DBG_VALUE))
445 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
446 .addImm(Offset).addMetadata(Variable);
450447 MachineBasicBlock::iterator Pos = CopyUseMI;
451448 EntryMBB->insertAfter(Pos, NewMI);
452449 }
44 ;CHECK: vadd.f32 q4, q8, q8
55 ;CHECK-NEXT: LBB0_1
66
7 ;CHECK:@DEBUG_VALUE: x <- Q4
8 ;CHECK-NEXT:@DEBUG_VALUE: y <- Q4
7 ;CHECK:@DEBUG_VALUE: x <- Q4+0
8 ;CHECK-NEXT:@DEBUG_VALUE: y <- Q4+0
99
1010
1111 @.str = external constant [13 x i8]
77 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.foo*, i32)* @_ZN3foo3bazEi to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
88
99 define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 {
10 ;CHECK: DEBUG_VALUE: baz:this <- RDI
10 ;CHECK: DEBUG_VALUE: baz:this <- RDI+0
1111 entry:
1212 tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !15)
1313 tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !16)
1515 call void @llvm.dbg.value(metadata !12, i64 0, metadata !13), !dbg !14
1616 %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15
1717 %tmp3 = add i32 0, %tmp2, !dbg !15
18 ; CHECK: ##DEBUG_VALUE: idx <- EAX
18 ; CHECK: ##DEBUG_VALUE: idx <- EAX+0
1919 call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !13), !dbg
2020 !15
2121 %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16
3939 !21 = metadata !{metadata !6, metadata !11}
4040 !22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"}
4141
42 ; Check that variable bar:b value range is appropriately truncated in debug info.
42 ; Check that variable bar:b value range is appropriately trucated in debug info.
4343 ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'
4444 ; Here Ltmp7 is the end of the location range.
4545
5353 ;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}
5454 ;CHECK-NEXT: .short Lset
5555 ;CHECK-NEXT: Ltmp
56 ;CHECK-NEXT: .byte 85 ## DW_OP_reg
56 ;CHECK-NEXT: .byte 85
5757 ;CHECK-NEXT: Ltmp
5858 ;CHECK-NEXT: .quad 0
5959 ;CHECK-NEXT: .quad 0
0 ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj
1 ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s -check-prefix=DW-CHECK
1 ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
22
3 ; DW-CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
3 ; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
44 ; FIXME: The location here needs to be fixed, but llvm-dwarfdump doesn't handle
55 ; DW_AT_location lists yet.
6 ; DW-CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)
7
8 ; Unfortunately llvm-dwarfdump can't unparse a list of DW_AT_locations
9 ; right now, so we check the asm output:
10 ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK
11 ; vla should have a register-indirect address at one point.
12 ; ASM-CHECK: DEBUG_VALUE: vla <- RCX+0
6 ; CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)
137
148 define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {
159 entry:
+0
-104
test/DebugInfo/X86/vla.ll less more
None ; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s
1 ; Ensure that we generate a breg+0 location for the variable length array a.
2 ; CHECK: ##DEBUG_VALUE: vla:a <- RDX+0
3 ; rdar://problem/13658587
4 ;
5 ; generated from:
6 ;
7 ; int vla(int n) {
8 ; int a[n];
9 ; a[0] = 42;
10 ; return a[n-1];
11 ; }
12 ;
13 ; int main(int argc, char** argv) {
14 ; return vla(argc);
15 ; }
16
17 ; ModuleID = 'vla.c'
18 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
19 target triple = "x86_64-apple-macosx10.8.0"
20
21 ; Function Attrs: nounwind ssp uwtable
22 define i32 @vla(i32 %n) nounwind ssp uwtable {
23 entry:
24 %n.addr = alloca i32, align 4
25 %saved_stack = alloca i8*
26 %cleanup.dest.slot = alloca i32
27 store i32 %n, i32* %n.addr, align 4
28 call void @llvm.dbg.declare(metadata !{i32* %n.addr}, metadata !15), !dbg !16
29 %0 = load i32* %n.addr, align 4, !dbg !17
30 %1 = zext i32 %0 to i64, !dbg !17
31 %2 = call i8* @llvm.stacksave(), !dbg !17
32 store i8* %2, i8** %saved_stack, !dbg !17
33 %vla = alloca i32, i64 %1, align 16, !dbg !17
34 call void @llvm.dbg.declare(metadata !{i32* %vla}, metadata !18), !dbg !17
35 %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22
36 store i32 42, i32* %arrayidx, align 4, !dbg !22
37 %3 = load i32* %n.addr, align 4, !dbg !23
38 %sub = sub nsw i32 %3, 1, !dbg !23
39 %idxprom = sext i32 %sub to i64, !dbg !23
40 %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
41 %4 = load i32* %arrayidx1, align 4, !dbg !23
42 store i32 1, i32* %cleanup.dest.slot
43 %5 = load i8** %saved_stack, !dbg !24
44 call void @llvm.stackrestore(i8* %5), !dbg !24
45 ret i32 %4, !dbg !23
46 }
47
48 ; Function Attrs: nounwind readnone
49 declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
50
51 ; Function Attrs: nounwind
52 declare i8* @llvm.stacksave() nounwind
53
54 ; Function Attrs: nounwind
55 declare void @llvm.stackrestore(i8*) nounwind
56
57 ; Function Attrs: nounwind ssp uwtable
58 define i32 @main(i32 %argc, i8** %argv) nounwind ssp uwtable {
59 entry:
60 %retval = alloca i32, align 4
61 %argc.addr = alloca i32, align 4
62 %argv.addr = alloca i8**, align 8
63 store i32 0, i32* %retval
64 store i32 %argc, i32* %argc.addr, align 4
65 call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !25), !dbg !26
66 store i8** %argv, i8*** %argv.addr, align 8
67 call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !27), !dbg !26
68 %0 = load i32* %argc.addr, align 4, !dbg !28
69 %call = call i32 @vla(i32 %0), !dbg !28
70 ret i32 %call, !dbg !28
71 }
72
73 !llvm.dbg.cu = !{!0}
74
75 !0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/vla.c] [DW_LANG_C99]
76 !1 = metadata !{metadata !"vla.c", metadata !""}
77 !2 = metadata !{i32 0}
78 !3 = metadata !{metadata !4, metadata !9}
79 !4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"vla", metadata !"vla", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @vla, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [vla]
80 !5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/vla.c]
81 !6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
82 !7 = metadata !{metadata !8, metadata !8}
83 !8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
84 !9 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
85 !10 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
86 !11 = metadata !{metadata !8, metadata !8, metadata !12}
87 !12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
88 !13 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
89 !14 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
90 !15 = metadata !{i32 786689, metadata !4, metadata !"n", metadata !5, i32 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [n] [line 1]
91 !16 = metadata !{i32 1, i32 0, metadata !4, null}
92 !17 = metadata !{i32 2, i32 0, metadata !4, null}
93 !18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 2, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2]
94 !19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !8, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
95 !20 = metadata !{metadata !21}
96 !21 = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] [unbounded]
97 !22 = metadata !{i32 3, i32 0, metadata !4, null}
98 !23 = metadata !{i32 4, i32 0, metadata !4, null}
99 !24 = metadata !{i32 5, i32 0, metadata !4, null}
100 !25 = metadata !{i32 786689, metadata !9, metadata !"argc", metadata !5, i32 16777223, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 7]
101 !26 = metadata !{i32 7, i32 0, metadata !9, null}
102 !27 = metadata !{i32 786689, metadata !9, metadata !"argv", metadata !5, i32 33554439, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 7]
103 !28 = metadata !{i32 8, i32 0, metadata !9, null}