llvm.org GIT mirror llvm / 8651125
Replaces uses of unsigned for indexes in LiveInterval and VNInfo with a new class, MachineInstrIndex, which hides arithmetic details from most clients. This is a step towards allowing the register allocator to update/insert code during allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81040 91177308-0d34-0410-b5e6-96231b3b80d8 Lang Hames 11 years ago
12 changed file(s) with 964 addition(s) and 628 deletion(s). Raw diff Collapse all Expand all
2020 #ifndef LLVM_CODEGEN_LIVEINTERVAL_H
2121 #define LLVM_CODEGEN_LIVEINTERVAL_H
2222
23 #include "llvm/ADT/DenseMapInfo.h"
2324 #include "llvm/ADT/SmallVector.h"
2425 #include "llvm/Support/Allocator.h"
2526 #include "llvm/Support/AlignOf.h"
3132 class MachineRegisterInfo;
3233 class TargetRegisterInfo;
3334 class raw_ostream;
35
36 /// MachineInstrIndex - An opaque wrapper around machine indexes.
37 class MachineInstrIndex {
38 friend class VNInfo;
39 friend class LiveInterval;
40 friend class LiveIntervals;
41 friend struct DenseMapInfo;
42
43 public:
44
45 enum Slot { LOAD, USE, DEF, STORE, NUM };
46
47 private:
48
49 unsigned index;
50
51 static const unsigned PHI_BIT = 1 << 31;
52
53 public:
54
55 /// Construct a default MachineInstrIndex pointing to a reserved index.
56 MachineInstrIndex() : index(0) {}
57
58 /// Construct an index from the given index, pointing to the given slot.
59 MachineInstrIndex(MachineInstrIndex m, Slot s)
60 : index((m.index / NUM) * NUM + s) {}
61
62 /// Print this index to the given raw_ostream.
63 void print(raw_ostream &os) const;
64
65 /// Print this index to the given std::ostream.
66 void print(std::ostream &os) const;
67
68 /// Compare two MachineInstrIndex objects for equality.
69 bool operator==(MachineInstrIndex other) const {
70 return ((index & ~PHI_BIT) == (other.index & ~PHI_BIT));
71 }
72 /// Compare two MachineInstrIndex objects for inequality.
73 bool operator!=(MachineInstrIndex other) const {
74 return ((index & ~PHI_BIT) != (other.index & ~PHI_BIT));
75 }
76
77 /// Compare two MachineInstrIndex objects. Return true if the first index
78 /// is strictly lower than the second.
79 bool operator<(MachineInstrIndex other) const {
80 return ((index & ~PHI_BIT) < (other.index & ~PHI_BIT));
81 }
82 /// Compare two MachineInstrIndex objects. Return true if the first index
83 /// is lower than, or equal to, the second.
84 bool operator<=(MachineInstrIndex other) const {
85 return ((index & ~PHI_BIT) <= (other.index & ~PHI_BIT));
86 }
87
88 /// Compare two MachineInstrIndex objects. Return true if the first index
89 /// is greater than the second.
90 bool operator>(MachineInstrIndex other) const {
91 return ((index & ~PHI_BIT) > (other.index & ~PHI_BIT));
92 }
93
94 /// Compare two MachineInstrIndex objects. Return true if the first index
95 /// is greater than, or equal to, the second.
96 bool operator>=(MachineInstrIndex other) const {
97 return ((index & ~PHI_BIT) >= (other.index & ~PHI_BIT));
98 }
99
100 /// Returns true if this index represents a load.
101 bool isLoad() const {
102 return ((index % NUM) == LOAD);
103 }
104
105 /// Returns true if this index represents a use.
106 bool isUse() const {
107 return ((index % NUM) == USE);
108 }
109
110 /// Returns true if this index represents a def.
111 bool isDef() const {
112 return ((index % NUM) == DEF);
113 }
114
115 /// Returns true if this index represents a store.
116 bool isStore() const {
117 return ((index % NUM) == STORE);
118 }
119
120 /// Returns the slot for this MachineInstrIndex.
121 Slot getSlot() const {
122 return static_cast(index % NUM);
123 }
124
125 /// Returns true if this index represents a non-PHI use/def.
126 bool isNonPHIIndex() const {
127 return ((index & PHI_BIT) == 0);
128 }
129
130 /// Returns true if this index represents a PHI use/def.
131 bool isPHIIndex() const {
132 return ((index & PHI_BIT) == PHI_BIT);
133 }
134
135 private:
136
137 /// Construct an index from the given index, with its PHI kill marker set.
138 MachineInstrIndex(bool phi, MachineInstrIndex o) : index(o.index) {
139 if (phi)
140 index |= PHI_BIT;
141 else
142 index &= ~PHI_BIT;
143 }
144
145 explicit MachineInstrIndex(unsigned idx)
146 : index(idx & ~PHI_BIT) {}
147
148 MachineInstrIndex(bool phi, unsigned idx)
149 : index(idx & ~PHI_BIT) {
150 if (phi)
151 index |= PHI_BIT;
152 }
153
154 MachineInstrIndex(bool phi, unsigned idx, Slot slot)
155 : index(((idx / NUM) * NUM + slot) & ~PHI_BIT) {
156 if (phi)
157 index |= PHI_BIT;
158 }
159
160 MachineInstrIndex nextSlot() const {
161 assert((index & PHI_BIT) == ((index + 1) & PHI_BIT) &&
162 "Index out of bounds.");
163 return MachineInstrIndex(index + 1);
164 }
165
166 MachineInstrIndex nextIndex() const {
167 assert((index & PHI_BIT) == ((index + NUM) & PHI_BIT) &&
168 "Index out of bounds.");
169 return MachineInstrIndex(index + NUM);
170 }
171
172 MachineInstrIndex prevSlot() const {
173 assert((index & PHI_BIT) == ((index - 1) & PHI_BIT) &&
174 "Index out of bounds.");
175 return MachineInstrIndex(index - 1);
176 }
177
178 MachineInstrIndex prevIndex() const {
179 assert((index & PHI_BIT) == ((index - NUM) & PHI_BIT) &&
180 "Index out of bounds.");
181 return MachineInstrIndex(index - NUM);
182 }
183
184 int distance(MachineInstrIndex other) const {
185 return (other.index & ~PHI_BIT) - (index & ~PHI_BIT);
186 }
187
188 /// Returns an unsigned number suitable as an index into a
189 /// vector over all instructions.
190 unsigned getVecIndex() const {
191 return (index & ~PHI_BIT) / NUM;
192 }
193
194 /// Scale this index by the given factor.
195 MachineInstrIndex scale(unsigned factor) const {
196 unsigned i = (index & ~PHI_BIT) / NUM,
197 o = (index % ~PHI_BIT) % NUM;
198 assert(index <= (~0U & ~PHI_BIT) / (factor * NUM) &&
199 "Rescaled interval would overflow");
200 return MachineInstrIndex(i * NUM * factor, o);
201 }
202
203 static MachineInstrIndex emptyKey() {
204 return MachineInstrIndex(true, 0x7fffffff);
205 }
206
207 static MachineInstrIndex tombstoneKey() {
208 return MachineInstrIndex(true, 0x7ffffffe);
209 }
210
211 static unsigned getHashValue(const MachineInstrIndex &v) {
212 return v.index * 37;
213 }
214
215 };
216
217 inline raw_ostream& operator<<(raw_ostream &os, MachineInstrIndex mi) {
218 mi.print(os);
219 return os;
220 }
221
222 inline std::ostream& operator<<(std::ostream &os, MachineInstrIndex mi) {
223 mi.print(os);
224 return os;
225 }
226
227 /// Densemap specialization for MachineInstrIndex.
228 template <>
229 struct DenseMapInfo {
230 static inline MachineInstrIndex getEmptyKey() {
231 return MachineInstrIndex::emptyKey();
232 }
233 static inline MachineInstrIndex getTombstoneKey() {
234 return MachineInstrIndex::tombstoneKey();
235 }
236 static inline unsigned getHashValue(const MachineInstrIndex &v) {
237 return MachineInstrIndex::getHashValue(v);
238 }
239 static inline bool isEqual(const MachineInstrIndex &LHS,
240 const MachineInstrIndex &RHS) {
241 return (LHS == RHS);
242 }
243 static inline bool isPod() { return true; }
244 };
245
34246
35247 /// VNInfo - Value Number Information.
36248 /// This class holds information about a machine level values, including
64276 } cr;
65277
66278 public:
67 /// Holds information about individual kills.
68 struct KillInfo {
69 bool isPHIKill : 1;
70 unsigned killIdx : 31;
71
72 KillInfo(bool isPHIKill, unsigned killIdx)
73 : isPHIKill(isPHIKill), killIdx(killIdx) {
74
75 assert(killIdx != 0 && "Zero kill indices are no longer permitted.");
76 }
77
78 };
79
80 typedef SmallVector KillSet;
279
280 typedef SmallVector KillSet;
81281
82282 /// The ID number of this value.
83283 unsigned id;
84284
85285 /// The index of the defining instruction (if isDefAccurate() returns true).
86 unsigned def;
286 MachineInstrIndex def;
87287
88288 KillSet kills;
89289
90290 VNInfo()
91 : flags(IS_UNUSED), id(~1U), def(0) { cr.copy = 0; }
291 : flags(IS_UNUSED), id(~1U) { cr.copy = 0; }
92292
93293 /// VNInfo constructor.
94294 /// d is presumed to point to the actual defining instr. If it doesn't
95295 /// setIsDefAccurate(false) should be called after construction.
96 VNInfo(unsigned i, unsigned d, MachineInstr *c)
296 VNInfo(unsigned i, MachineInstrIndex d, MachineInstr *c)
97297 : flags(IS_DEF_ACCURATE), id(i), def(d) { cr.copy = c; }
98298
99299 /// VNInfo construtor, copies values from orig, except for the value number.
133333
134334 /// Returns true if one or more kills are PHI nodes.
135335 bool hasPHIKill() const { return flags & HAS_PHI_KILL; }
336 /// Set the PHI kill flag on this value.
136337 void setHasPHIKill(bool hasKill) {
137338 if (hasKill)
138339 flags |= HAS_PHI_KILL;
143344 /// Returns true if this value is re-defined by an early clobber somewhere
144345 /// during the live range.
145346 bool hasRedefByEC() const { return flags & REDEF_BY_EC; }
347 /// Set the "redef by early clobber" flag on this value.
146348 void setHasRedefByEC(bool hasRedef) {
147349 if (hasRedef)
148350 flags |= REDEF_BY_EC;
153355 /// Returns true if this value is defined by a PHI instruction (or was,
154356 /// PHI instrucions may have been eliminated).
155357 bool isPHIDef() const { return flags & IS_PHI_DEF; }
358 /// Set the "phi def" flag on this value.
156359 void setIsPHIDef(bool phiDef) {
157360 if (phiDef)
158361 flags |= IS_PHI_DEF;
162365
163366 /// Returns true if this value is unused.
164367 bool isUnused() const { return flags & IS_UNUSED; }
368 /// Set the "is unused" flag on this value.
165369 void setIsUnused(bool unused) {
166370 if (unused)
167371 flags |= IS_UNUSED;
171375
172376 /// Returns true if the def is accurate.
173377 bool isDefAccurate() const { return flags & IS_DEF_ACCURATE; }
378 /// Set the "is def accurate" flag on this value.
174379 void setIsDefAccurate(bool defAccurate) {
175380 if (defAccurate)
176381 flags |= IS_DEF_ACCURATE;
178383 flags &= ~IS_DEF_ACCURATE;
179384 }
180385
386 /// Returns true if the given index is a kill of this value.
387 bool isKill(MachineInstrIndex k) const {
388 KillSet::const_iterator
389 i = std::lower_bound(kills.begin(), kills.end(), k);
390 return (i != kills.end() && *i == k);
391 }
392
393 /// addKill - Add a kill instruction index to the specified value
394 /// number.
395 void addKill(MachineInstrIndex k) {
396 if (kills.empty()) {
397 kills.push_back(k);
398 } else {
399 KillSet::iterator
400 i = std::lower_bound(kills.begin(), kills.end(), k);
401 kills.insert(i, k);
402 }
403 }
404
405 /// Remove the specified kill index from this value's kills list.
406 /// Returns true if the value was present, otherwise returns false.
407 bool removeKill(MachineInstrIndex k) {
408 KillSet::iterator i = std::lower_bound(kills.begin(), kills.end(), k);
409 if (i != kills.end() && *i == k) {
410 kills.erase(i);
411 return true;
412 }
413 return false;
414 }
415
416 /// Remove all kills in the range [s, e).
417 void removeKills(MachineInstrIndex s, MachineInstrIndex e) {
418 KillSet::iterator
419 si = std::lower_bound(kills.begin(), kills.end(), s),
420 se = std::upper_bound(kills.begin(), kills.end(), e);
421
422 kills.erase(si, se);
423 }
424
181425 };
182
183 inline bool operator<(const VNInfo::KillInfo &k1, const VNInfo::KillInfo &k2){
184 return k1.killIdx < k2.killIdx;
185 }
186
187 inline bool operator<(const VNInfo::KillInfo &k, unsigned idx) {
188 return k.killIdx < idx;
189 }
190
191 inline bool operator<(unsigned idx, const VNInfo::KillInfo &k) {
192 return idx < k.killIdx;
193 }
194426
195427 /// LiveRange structure - This represents a simple register range in the
196428 /// program, with an inclusive start point and an exclusive end point.
197429 /// These ranges are rendered as [start,end).
198430 struct LiveRange {
199 unsigned start; // Start point of the interval (inclusive)
200 unsigned end; // End point of the interval (exclusive)
431 MachineInstrIndex start; // Start point of the interval (inclusive)
432 MachineInstrIndex end; // End point of the interval (exclusive)
201433 VNInfo *valno; // identifier for the value contained in this interval.
202434
203 LiveRange(unsigned S, unsigned E, VNInfo *V) : start(S), end(E), valno(V) {
435 LiveRange(MachineInstrIndex S, MachineInstrIndex E, VNInfo *V)
436 : start(S), end(E), valno(V) {
437
204438 assert(S < E && "Cannot create empty or backwards range");
205439 }
206440
207441 /// contains - Return true if the index is covered by this range.
208442 ///
209 bool contains(unsigned I) const {
443 bool contains(MachineInstrIndex I) const {
210444 return start <= I && I < end;
445 }
446
447 /// containsRange - Return true if the given range, [S, E), is covered by
448 /// this range.
449 bool containsRange(MachineInstrIndex S, MachineInstrIndex E) const {
450 assert((S < E) && "Backwards interval?");
451 return (start <= S && S < end) && (start < E && E <= end);
211452 }
212453
213454 bool operator<(const LiveRange &LR) const {
227468 raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
228469
229470
230 inline bool operator<(unsigned V, const LiveRange &LR) {
471 inline bool operator<(MachineInstrIndex V, const LiveRange &LR) {
231472 return V < LR.start;
232473 }
233474
234 inline bool operator<(const LiveRange &LR, unsigned V) {
475 inline bool operator<(const LiveRange &LR, MachineInstrIndex V) {
235476 return LR.start < V;
236477 }
237478
259500 NUM = 4
260501 };
261502
262 static unsigned scale(unsigned slot, unsigned factor) {
263 unsigned index = slot / NUM,
264 offset = slot % NUM;
265 assert(index <= ~0U / (factor * NUM) &&
266 "Rescaled interval would overflow");
267 return index * NUM * factor + offset;
268 }
269
270503 };
271504
272505 LiveInterval(unsigned Reg, float Weight, bool IsSS = false)
296529 /// end of the interval. If no LiveRange contains this position, but the
297530 /// position is in a hole, this method returns an iterator pointing the the
298531 /// LiveRange immediately after the hole.
299 iterator advanceTo(iterator I, unsigned Pos) {
300 if (Pos >= endNumber())
532 iterator advanceTo(iterator I, MachineInstrIndex Pos) {
533 if (Pos >= endIndex())
301534 return end();
302535 while (I->end <= Pos) ++I;
303536 return I;
343576
344577 /// getNextValue - Create a new value number and return it. MIIdx specifies
345578 /// the instruction that defines the value number.
346 VNInfo *getNextValue(unsigned MIIdx, MachineInstr *CopyMI,
579 VNInfo *getNextValue(MachineInstrIndex def, MachineInstr *CopyMI,
347580 bool isDefAccurate, BumpPtrAllocator &VNInfoAllocator){
348
349 assert(MIIdx != ~0u && MIIdx != ~1u &&
350 "PHI def / unused flags should now be passed explicitly.");
351581 VNInfo *VNI =
352582 static_cast(VNInfoAllocator.Allocate((unsigned)sizeof(VNInfo),
353583 alignof()));
354 new (VNI) VNInfo((unsigned)valnos.size(), MIIdx, CopyMI);
584 new (VNI) VNInfo((unsigned)valnos.size(), def, CopyMI);
355585 VNI->setIsDefAccurate(isDefAccurate);
356586 valnos.push_back(VNI);
357587 return VNI;
369599 new (VNI) VNInfo((unsigned)valnos.size(), *orig);
370600 valnos.push_back(VNI);
371601 return VNI;
372 }
373
374 /// addKill - Add a kill instruction index to the specified value
375 /// number.
376 static void addKill(VNInfo *VNI, unsigned KillIdx, bool phiKill) {
377 VNInfo::KillSet &kills = VNI->kills;
378 VNInfo::KillInfo newKill(phiKill, KillIdx);
379 if (kills.empty()) {
380 kills.push_back(newKill);
381 } else {
382 VNInfo::KillSet::iterator
383 I = std::lower_bound(kills.begin(), kills.end(), newKill);
384 kills.insert(I, newKill);
385 }
386602 }
387603
388604 /// addKills - Add a number of kills into the VNInfo kill vector. If this
390606 void addKills(VNInfo *VNI, const VNInfo::KillSet &kills) {
391607 for (unsigned i = 0, e = static_cast(kills.size());
392608 i != e; ++i) {
393 const VNInfo::KillInfo &Kill = kills[i];
394 if (!liveBeforeAndAt(Kill.killIdx)) {
395 VNInfo::KillSet::iterator
396 I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), Kill);
397 VNI->kills.insert(I, Kill);
609 if (!liveBeforeAndAt(kills[i])) {
610 VNI->addKill(kills[i]);
398611 }
399612 }
400613 }
401614
615 /* REMOVE_ME
616 /// addKill - Add a kill instruction index to the specified value
617 /// number.
618 static void addKill(VNInfo *VNI, MachineInstrIndex killIdx) {
619 assert(killIdx.isUse() && "Kill must be a use.");
620 if (VNI->kills.empty()) {
621 VNI->kills.push_back(killIdx);
622 } else {
623 VNInfo::KillSet::iterator
624 I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), killIdx);
625 VNI->kills.insert(I, killIdx);
626 }
627 }
628
402629 /// removeKill - Remove the specified kill from the list of kills of
403630 /// the specified val#.
404 static bool removeKill(VNInfo *VNI, unsigned KillIdx) {
405 VNInfo::KillSet &kills = VNI->kills;
631 static bool removeKill(VNInfo *VNI, MachineInstrIndex Kill) {
632
406633 VNInfo::KillSet::iterator
407 I = std::lower_bound(kills.begin(), kills.end(), KillIdx);
408 if (I != kills.end() && I->killIdx == KillIdx) {
409 kills.erase(I);
634 I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), Kill);
635 if (I != VNI->kills.end() && (*I == Kill)) {
636 VNI->kills.erase(I);
410637 return true;
411638 }
412639 return false;
413 }
640
641 }
642
643
414644
415645 /// removeKills - Remove all the kills in specified range
416646 /// [Start, End] of the specified val#.
417 static void removeKills(VNInfo *VNI, unsigned Start, unsigned End) {
647 static void removeKills(VNInfo *VNI, MachineInstrIndex Start,
648 MachineInstrIndex End) {
649
418650 VNInfo::KillSet &kills = VNI->kills;
419651
420652 VNInfo::KillSet::iterator
423655 E = std::upper_bound(kills.begin(), kills.end(), End);
424656 kills.erase(I, E);
425657 }
658
426659
427660 /// isKill - Return true if the specified index is a kill of the
428661 /// specified val#.
429 static bool isKill(const VNInfo *VNI, unsigned KillIdx) {
430 const VNInfo::KillSet &kills = VNI->kills;
662 static bool isKill(const VNInfo *VNI, MachineInstrIndex Kill) {
431663 VNInfo::KillSet::const_iterator
432 I = std::lower_bound(kills.begin(), kills.end(), KillIdx);
433 return I != kills.end() && I->killIdx == KillIdx;
434 }
664 I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), Kill);
665 return I != VNI->kills.end() && (*I == Kill);
666 }
667 */
435668
436669 /// isOnlyLROfValNo - Return true if the specified live range is the only
437670 /// one defined by the its val#.
459692
460693 /// MergeInClobberRange - Same as MergeInClobberRanges except it merge in a
461694 /// single LiveRange only.
462 void MergeInClobberRange(unsigned Start, unsigned End,
695 void MergeInClobberRange(MachineInstrIndex Start,
696 MachineInstrIndex End,
463697 BumpPtrAllocator &VNInfoAllocator);
464698
465699 /// MergeValueInAsValue - Merge all of the live ranges of a specific val#
484718
485719 bool empty() const { return ranges.empty(); }
486720
487 /// beginNumber - Return the lowest numbered slot covered by interval.
488 unsigned beginNumber() const {
721 /// beginIndex - Return the lowest numbered slot covered by interval.
722 MachineInstrIndex beginIndex() const {
489723 if (empty())
490 return 0;
724 return MachineInstrIndex();
491725 return ranges.front().start;
492726 }
493727
494728 /// endNumber - return the maximum point of the interval of the whole,
495729 /// exclusive.
496 unsigned endNumber() const {
730 MachineInstrIndex endIndex() const {
497731 if (empty())
498 return 0;
732 return MachineInstrIndex();
499733 return ranges.back().end;
500734 }
501735
502 bool expiredAt(unsigned index) const {
503 return index >= endNumber();
504 }
505
506 bool liveAt(unsigned index) const;
736 bool expiredAt(MachineInstrIndex index) const {
737 return index >= endIndex();
738 }
739
740 bool liveAt(MachineInstrIndex index) const;
507741
508742 // liveBeforeAndAt - Check if the interval is live at the index and the
509743 // index just before it. If index is liveAt, check if it starts a new live
510744 // range.If it does, then check if the previous live range ends at index-1.
511 bool liveBeforeAndAt(unsigned index) const;
745 bool liveBeforeAndAt(MachineInstrIndex index) const;
512746
513747 /// getLiveRangeContaining - Return the live range that contains the
514748 /// specified index, or null if there is none.
515 const LiveRange *getLiveRangeContaining(unsigned Idx) const {
749 const LiveRange *getLiveRangeContaining(MachineInstrIndex Idx) const {
516750 const_iterator I = FindLiveRangeContaining(Idx);
517751 return I == end() ? 0 : &*I;
518752 }
519753
520754 /// getLiveRangeContaining - Return the live range that contains the
521755 /// specified index, or null if there is none.
522 LiveRange *getLiveRangeContaining(unsigned Idx) {
756 LiveRange *getLiveRangeContaining(MachineInstrIndex Idx) {
523757 iterator I = FindLiveRangeContaining(Idx);
524758 return I == end() ? 0 : &*I;
525759 }
526760
527761 /// FindLiveRangeContaining - Return an iterator to the live range that
528762 /// contains the specified index, or end() if there is none.
529 const_iterator FindLiveRangeContaining(unsigned Idx) const;
763 const_iterator FindLiveRangeContaining(MachineInstrIndex Idx) const;
530764
531765 /// FindLiveRangeContaining - Return an iterator to the live range that
532766 /// contains the specified index, or end() if there is none.
533 iterator FindLiveRangeContaining(unsigned Idx);
534
535 /// findDefinedVNInfo - Find the VNInfo that's defined at the specified
536 /// index (register interval) or defined by the specified register (stack
537 /// inteval).
538 VNInfo *findDefinedVNInfo(unsigned DefIdxOrReg) const;
767 iterator FindLiveRangeContaining(MachineInstrIndex Idx);
768
769 /// findDefinedVNInfo - Find the by the specified
770 /// index (register interval) or defined
771 VNInfo *findDefinedVNInfoForRegInt(MachineInstrIndex Idx) const;
772
773 /// findDefinedVNInfo - Find the VNInfo that's defined by the specified
774 /// register (stack inteval only).
775 VNInfo *findDefinedVNInfoForStackInt(unsigned Reg) const;
776
539777
540778 /// overlaps - Return true if the intersection of the two live intervals is
541779 /// not empty.
545783
546784 /// overlaps - Return true if the live interval overlaps a range specified
547785 /// by [Start, End).
548 bool overlaps(unsigned Start, unsigned End) const;
786 bool overlaps(MachineInstrIndex Start, MachineInstrIndex End) const;
549787
550788 /// overlapsFrom - Return true if the intersection of the two live intervals
551789 /// is not empty. The specified iterator is a hint that we can begin
569807
570808 /// isInOneLiveRange - Return true if the range specified is entirely in the
571809 /// a single LiveRange of the live interval.
572 bool isInOneLiveRange(unsigned Start, unsigned End);
810 bool isInOneLiveRange(MachineInstrIndex Start, MachineInstrIndex End);
573811
574812 /// removeRange - Remove the specified range from this interval. Note that
575813 /// the range must be a single LiveRange in its entirety.
576 void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);
814 void removeRange(MachineInstrIndex Start, MachineInstrIndex End,
815 bool RemoveDeadValNo = false);
577816
578817 void removeRange(LiveRange LR, bool RemoveDeadValNo = false) {
579818 removeRange(LR.start, LR.end, RemoveDeadValNo);
596835 void ComputeJoinedWeight(const LiveInterval &Other);
597836
598837 bool operator<(const LiveInterval& other) const {
599 return beginNumber() < other.beginNumber();
838 return beginIndex() < other.beginIndex();
600839 }
601840
602841 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = 0) const;
605844 private:
606845
607846 Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From);
608 void extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd);
609 Ranges::iterator extendIntervalStartTo(Ranges::iterator I, unsigned NewStr);
847 void extendIntervalEndTo(Ranges::iterator I, MachineInstrIndex NewEnd);
848 Ranges::iterator extendIntervalStartTo(Ranges::iterator I, MachineInstrIndex NewStr);
610849 LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT
611850
612851 };
3939 class TargetInstrInfo;
4040 class TargetRegisterClass;
4141 class VirtRegMap;
42 typedef std::pair IdxMBBPair;
43
44 inline bool operator<(unsigned V, const IdxMBBPair &IM) {
42 typedef std::pair IdxMBBPair;
43
44 inline bool operator<(MachineInstrIndex V, const IdxMBBPair &IM) {
4545 return V < IM.first;
4646 }
4747
48 inline bool operator<(const IdxMBBPair &IM, unsigned V) {
48 inline bool operator<(const IdxMBBPair &IM, MachineInstrIndex V) {
4949 return IM.first < V;
5050 }
5151
6464 AliasAnalysis *aa_;
6565 LiveVariables* lv_;
6666
67
68
69
6770 /// Special pool allocator for VNInfo's (LiveInterval val#).
6871 ///
6972 BumpPtrAllocator VNInfoAllocator;
7073
7174 /// MBB2IdxMap - The indexes of the first and last instructions in the
7275 /// specified basic block.
73 std::vectorunsigned, unsigned> > MBB2IdxMap;
76 std::vectorMachineInstrIndex, MachineInstrIndex> > MBB2IdxMap;
7477
7578 /// Idx2MBBMap - Sorted list of pairs of index of first instruction
7679 /// and MBB id.
7982 /// FunctionSize - The number of instructions present in the function
8083 uint64_t FunctionSize;
8184
82 typedef DenseMapunsigned> Mi2IndexMap;
85 typedef DenseMapMachineInstrIndex> Mi2IndexMap;
8386 Mi2IndexMap mi2iMap_;
8487
8588 typedef std::vector Index2MiMap;
8891 typedef DenseMap Reg2IntervalMap;
8992 Reg2IntervalMap r2iMap_;
9093
91 DenseMapunsigned> terminatorGaps;
94 DenseMapMachineInstrIndex> terminatorGaps;
9295
9396 BitVector allocatableRegs_;
9497
100103 static char ID; // Pass identification, replacement for typeid
101104 LiveIntervals() : MachineFunctionPass(&ID) {}
102105
103 static unsigned getBaseIndex(unsigned index) {
104 return index - (index % InstrSlots::NUM);
105 }
106 static unsigned getBoundaryIndex(unsigned index) {
107 return getBaseIndex(index + InstrSlots::NUM - 1);
108 }
109 static unsigned getLoadIndex(unsigned index) {
110 return getBaseIndex(index) + InstrSlots::LOAD;
111 }
112 static unsigned getUseIndex(unsigned index) {
113 return getBaseIndex(index) + InstrSlots::USE;
114 }
115 static unsigned getDefIndex(unsigned index) {
116 return getBaseIndex(index) + InstrSlots::DEF;
117 }
118 static unsigned getStoreIndex(unsigned index) {
119 return getBaseIndex(index) + InstrSlots::STORE;
106 static MachineInstrIndex getBaseIndex(MachineInstrIndex index) {
107 return MachineInstrIndex(index, MachineInstrIndex::LOAD);
108 }
109 static MachineInstrIndex getBoundaryIndex(MachineInstrIndex index) {
110 return MachineInstrIndex(index,
111 (MachineInstrIndex::Slot)(MachineInstrIndex::NUM - 1));
112 }
113 static MachineInstrIndex getLoadIndex(MachineInstrIndex index) {
114 return MachineInstrIndex(index, MachineInstrIndex::LOAD);
115 }
116 static MachineInstrIndex getUseIndex(MachineInstrIndex index) {
117 return MachineInstrIndex(index, MachineInstrIndex::USE);
118 }
119 static MachineInstrIndex getDefIndex(MachineInstrIndex index) {
120 return MachineInstrIndex(index, MachineInstrIndex::DEF);
121 }
122 static MachineInstrIndex getStoreIndex(MachineInstrIndex index) {
123 return MachineInstrIndex(index, MachineInstrIndex::STORE);
124 }
125
126 MachineInstrIndex getNextSlot(MachineInstrIndex m) const {
127 return m.nextSlot();
128 }
129
130 MachineInstrIndex getNextIndex(MachineInstrIndex m) const {
131 return m.nextIndex();
132 }
133
134 MachineInstrIndex getPrevSlot(MachineInstrIndex m) const {
135 return m.prevSlot();
136 }
137
138 MachineInstrIndex getPrevIndex(MachineInstrIndex m) const {
139 return m.prevIndex();
120140 }
121141
122142 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
149169
150170 /// getMBBStartIdx - Return the base index of the first instruction in the
151171 /// specified MachineBasicBlock.
152 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
172 MachineInstrIndex getMBBStartIdx(MachineBasicBlock *MBB) const {
153173 return getMBBStartIdx(MBB->getNumber());
154174 }
155 unsigned getMBBStartIdx(unsigned MBBNo) const {
175 MachineInstrIndex getMBBStartIdx(unsigned MBBNo) const {
156176 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
157177 return MBB2IdxMap[MBBNo].first;
158178 }
159179
160180 /// getMBBEndIdx - Return the store index of the last instruction in the
161181 /// specified MachineBasicBlock.
162 unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
182 MachineInstrIndex getMBBEndIdx(MachineBasicBlock *MBB) const {
163183 return getMBBEndIdx(MBB->getNumber());
164184 }
165 unsigned getMBBEndIdx(unsigned MBBNo) const {
185 MachineInstrIndex getMBBEndIdx(unsigned MBBNo) const {
166186 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
167187 return MBB2IdxMap[MBBNo].second;
168188 }
183203
184204 /// getMBBFromIndex - given an index in any instruction of an
185205 /// MBB return a pointer the MBB
186 MachineBasicBlock* getMBBFromIndex(unsigned index) const {
206 MachineBasicBlock* getMBBFromIndex(MachineInstrIndex index) const {
187207 std::vector::const_iterator I =
188208 std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
189209 // Take the pair containing the index
191211 ((I != Idx2MBBMap.end() && I->first > index) ||
192212 (I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
193213
194 assert(J != Idx2MBBMap.end() && J->first < index+1 &&
214 assert(J != Idx2MBBMap.end() && J->first <= index &&
195215 index <= getMBBEndIdx(J->second) &&
196216 "index does not correspond to an MBB");
197217 return J->second;
198218 }
199219
200220 /// getInstructionIndex - returns the base index of instr
201 unsigned getInstructionIndex(const MachineInstr* instr) const {
221 MachineInstrIndex getInstructionIndex(const MachineInstr* instr) const {
202222 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
203223 assert(it != mi2iMap_.end() && "Invalid instruction!");
204224 return it->second;
206226
207227 /// getInstructionFromIndex - given an index in any slot of an
208228 /// instruction return a pointer the instruction
209 MachineInstr* getInstructionFromIndex(unsigned index) const {
210 index /= InstrSlots::NUM; // convert index to vector index
211 assert(index < i2miMap_.size() &&
229 MachineInstr* getInstructionFromIndex(MachineInstrIndex index) const {
230 // convert index to vector index
231 unsigned i = index.getVecIndex();
232 assert(i < i2miMap_.size() &&
212233 "index does not correspond to an instruction");
213 return i2miMap_[index];
234 return i2miMap_[i];
214235 }
215236
216237 /// hasGapBeforeInstr - Return true if the previous instruction slot,
217238 /// i.e. Index - InstrSlots::NUM, is not occupied.
218 bool hasGapBeforeInstr(unsigned Index) {
219 Index = getBaseIndex(Index - InstrSlots::NUM);
239 bool hasGapBeforeInstr(MachineInstrIndex Index) {
240 Index = getBaseIndex(Index.prevIndex());
220241 return getInstructionFromIndex(Index) == 0;
221242 }
222243
223244 /// hasGapAfterInstr - Return true if the successive instruction slot,
224245 /// i.e. Index + InstrSlots::Num, is not occupied.
225 bool hasGapAfterInstr(unsigned Index) {
226 Index = getBaseIndex(Index + InstrSlots::NUM);
246 bool hasGapAfterInstr(MachineInstrIndex Index) {
247 Index = getBaseIndex(Index.nextIndex());
227248 return getInstructionFromIndex(Index) == 0;
228249 }
229250
230251 /// findGapBeforeInstr - Find an empty instruction slot before the
231252 /// specified index. If "Furthest" is true, find one that's furthest
232253 /// away from the index (but before any index that's occupied).
233 unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
234 Index = getBaseIndex(Index - InstrSlots::NUM);
254 MachineInstrIndex findGapBeforeInstr(MachineInstrIndex Index,
255 bool Furthest = false) {
256 Index = getBaseIndex(Index.prevIndex());
235257 if (getInstructionFromIndex(Index))
236 return 0; // No gap!
258 return MachineInstrIndex(); // No gap!
237259 if (!Furthest)
238260 return Index;
239 unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
261 MachineInstrIndex PrevIndex = getBaseIndex(Index.prevIndex());
240262 while (getInstructionFromIndex(Index)) {
241263 Index = PrevIndex;
242 PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
264 PrevIndex = getBaseIndex(Index.prevIndex());
243265 }
244266 return Index;
245267 }
246268
247269 /// InsertMachineInstrInMaps - Insert the specified machine instruction
248270 /// into the instruction index map at the given index.
249 void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
250 i2miMap_[Index / InstrSlots::NUM] = MI;
271 void InsertMachineInstrInMaps(MachineInstr *MI, MachineInstrIndex Index) {
272 i2miMap_[Index.index / MachineInstrIndex::NUM] = MI;
251273 Mi2IndexMap::iterator it = mi2iMap_.find(MI);
252274 assert(it == mi2iMap_.end() && "Already in map!");
253275 mi2iMap_[MI] = Index;
267289 /// findLiveInMBBs - Given a live range, if the value of the range
268290 /// is live in any MBB returns true as well as the list of basic blocks
269291 /// in which the value is live.
270 bool findLiveInMBBs(unsigned Start, unsigned End,
292 bool findLiveInMBBs(MachineInstrIndex Start, MachineInstrIndex End,
271293 SmallVectorImpl &MBBs) const;
272294
273295 /// findReachableMBBs - Return a list MBB that can be reached via any
274296 /// branch or fallthroughs. Return true if the list is not empty.
275 bool findReachableMBBs(unsigned Start, unsigned End,
297 bool findReachableMBBs(MachineInstrIndex Start, MachineInstrIndex End,
276298 SmallVectorImpl &MBBs) const;
277299
278300 // Interval creation
291313 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
292314 /// adds a live range from that instruction to the end of its MBB.
293315 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
294 MachineInstr* startInst);
316 MachineInstr* startInst);
295317
296318 // Interval removal
297319
314336 // MachineInstr -> index mappings
315337 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
316338 if (mi2i != mi2iMap_.end()) {
317 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
339 i2miMap_[mi2i->second.index/InstrSlots::NUM] = 0;
318340 mi2iMap_.erase(mi2i);
319341 }
320342 }
325347 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
326348 if (mi2i == mi2iMap_.end())
327349 return;
328 i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
350 i2miMap_[mi2i->second.index/InstrSlots::NUM] = NewMI;
329351 Mi2IndexMap::iterator it = mi2iMap_.find(MI);
330352 assert(it != mi2iMap_.end() && "Invalid instruction!");
331 unsigned Index = it->second;
353 MachineInstrIndex Index = it->second;
332354 mi2iMap_.erase(it);
333355 mi2iMap_[NewMI] = Index;
334356 }
412434 /// (calls handlePhysicalRegisterDef and
413435 /// handleVirtualRegisterDef)
414436 void handleRegisterDef(MachineBasicBlock *MBB,
415 MachineBasicBlock::iterator MI, unsigned MIIdx,
437 MachineBasicBlock::iterator MI,
438 MachineInstrIndex MIIdx,
416439 MachineOperand& MO, unsigned MOIdx);
417440
418441 /// handleVirtualRegisterDef - update intervals for a virtual
419442 /// register def
420443 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
421444 MachineBasicBlock::iterator MI,
422 unsigned MIIdx, MachineOperand& MO,
423 unsigned MOIdx, LiveInterval& interval);
445 MachineInstrIndex MIIdx, MachineOperand& MO,
446 unsigned MOIdx,
447 LiveInterval& interval);
424448
425449 /// handlePhysicalRegisterDef - update intervals for a physical register
426450 /// def.
427451 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
428452 MachineBasicBlock::iterator mi,
429 unsigned MIIdx, MachineOperand& MO,
453 MachineInstrIndex MIIdx, MachineOperand& MO,
430454 LiveInterval &interval,
431455 MachineInstr *CopyMI);
432456
433457 /// handleLiveInRegister - Create interval for a livein register.
434458 void handleLiveInRegister(MachineBasicBlock* mbb,
435 unsigned MIIdx,
459 MachineInstrIndex MIIdx,
436460 LiveInterval &interval, bool isAlias = false);
437461
438462 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
445469 /// which reaches the given instruction also reaches the specified use
446470 /// index.
447471 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
448 unsigned UseIdx) const;
472 MachineInstrIndex UseIdx) const;
449473
450474 /// isReMaterializable - Returns true if the definition MI of the specified
451475 /// val# of the specified interval is re-materializable. Also returns true
460484 /// MI. If it is successul, MI is updated with the newly created MI and
461485 /// returns true.
462486 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
463 MachineInstr *DefMI, unsigned InstrIdx,
487 MachineInstr *DefMI, MachineInstrIndex InstrIdx,
464488 SmallVector &Ops,
465 bool isSS, int Slot, unsigned Reg);
489 bool isSS, int FrameIndex, unsigned Reg);
466490
467491 /// canFoldMemoryOperand - Return true if the specified load / store
468492 /// folding is possible.
473497 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
474498 /// VNInfo that's after the specified index but is within the basic block.
475499 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
476 MachineBasicBlock *MBB, unsigned Idx) const;
500 MachineBasicBlock *MBB,
501 MachineInstrIndex Idx) const;
477502
478503 /// hasAllocatableSuperReg - Return true if the specified physical register
479504 /// has any super register that's allocatable.
481506
482507 /// SRInfo - Spill / restore info.
483508 struct SRInfo {
484 int index;
509 MachineInstrIndex index;
485510 unsigned vreg;
486511 bool canFold;
487 SRInfo(int i, unsigned vr, bool f) : index(i), vreg(vr), canFold(f) {};
512 SRInfo(MachineInstrIndex i, unsigned vr, bool f)
513 : index(i), vreg(vr), canFold(f) {}
488514 };
489515
490 bool alsoFoldARestore(int Id, int index, unsigned vr,
516 bool alsoFoldARestore(int Id, MachineInstrIndex index, unsigned vr,
491517 BitVector &RestoreMBBs,
492518 DenseMap >&RestoreIdxes);
493 void eraseRestoreInfo(int Id, int index, unsigned vr,
519 void eraseRestoreInfo(int Id, MachineInstrIndex index, unsigned vr,
494520 BitVector &RestoreMBBs,
495521 DenseMap >&RestoreIdxes);
496522
509535 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
510536 /// live range.
511537 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
512 bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
513 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
538 bool TrySplit, MachineInstrIndex index, MachineInstrIndex end,
539 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
540 unsigned Slot, int LdSlot,
514541 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
515542 VirtRegMap &vrm, const TargetRegisterClass* rc,
516543 SmallVector &ReMatIds, const MachineLoopInfo *loopInfo,
2727 #include
2828 using namespace llvm;
2929
30 // Print a MachineInstrIndex to a raw_ostream.
31 void MachineInstrIndex::print(raw_ostream &os) const {
32 os << (index & ~PHI_BIT);
33 }
34
3035 // An example for liveAt():
3136 //
3237 // this = [1,4), liveAt(0) will return false. The instruction defining this
3439 // variable it represents. This is because slot 1 is used (def slot) and spans
3540 // up to slot 3 (store slot).
3641 //
37 bool LiveInterval::liveAt(unsigned I) const {
42 bool LiveInterval::liveAt(MachineInstrIndex I) const {
3843 Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
3944
4045 if (r == ranges.begin())
4752 // liveBeforeAndAt - Check if the interval is live at the index and the index
4853 // just before it. If index is liveAt, check if it starts a new live range.
4954 // If it does, then check if the previous live range ends at index-1.
50 bool LiveInterval::liveBeforeAndAt(unsigned I) const {
55 bool LiveInterval::liveBeforeAndAt(MachineInstrIndex I) const {
5156 Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
5257
5358 if (r == ranges.begin())
125130
126131 /// overlaps - Return true if the live interval overlaps a range specified
127132 /// by [Start, End).
128 bool LiveInterval::overlaps(unsigned Start, unsigned End) const {
133 bool LiveInterval::overlaps(MachineInstrIndex Start, MachineInstrIndex End) const {
129134 assert(Start < End && "Invalid range");
130135 const_iterator I = begin();
131136 const_iterator E = end();
143148 /// specified by I to end at the specified endpoint. To do this, we should
144149 /// merge and eliminate all ranges that this will overlap with. The iterator is
145150 /// not invalidated.
146 void LiveInterval::extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd) {
151 void LiveInterval::extendIntervalEndTo(Ranges::iterator I, MachineInstrIndex NewEnd) {
147152 assert(I != ranges.end() && "Not a valid interval!");
148153 VNInfo *ValNo = I->valno;
149 unsigned OldEnd = I->end;
154 MachineInstrIndex OldEnd = I->end;
150155
151156 // Search for the first interval that we can't merge with.
152157 Ranges::iterator MergeTo = next(I);
161166 ranges.erase(next(I), MergeTo);
162167
163168 // Update kill info.
164 removeKills(ValNo, OldEnd, I->end-1);
169 ValNo->removeKills(OldEnd, I->end.prevSlot());
165170
166171 // If the newly formed range now touches the range after it and if they have
167172 // the same value number, merge the two ranges into one range.
177182 /// specified by I to start at the specified endpoint. To do this, we should
178183 /// merge and eliminate all ranges that this will overlap with.
179184 LiveInterval::Ranges::iterator
180 LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
185 LiveInterval::extendIntervalStartTo(Ranges::iterator I, MachineInstrIndex NewStart) {
181186 assert(I != ranges.end() && "Not a valid interval!");
182187 VNInfo *ValNo = I->valno;
183188
210215
211216 LiveInterval::iterator
212217 LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
213 unsigned Start = LR.start, End = LR.end;
218 MachineInstrIndex Start = LR.start, End = LR.end;
214219 iterator it = std::upper_bound(From, ranges.end(), Start);
215220
216221 // If the inserted interval starts in the middle or right at the end of
244249 extendIntervalEndTo(it, End);
245250 else if (End < it->end)
246251 // Overlapping intervals, there might have been a kill here.
247 removeKill(it->valno, End);
252 it->valno->removeKill(End);
248253 return it;
249254 }
250255 } else {
260265 return ranges.insert(it, LR);
261266 }
262267
263 /// isInOneLiveRange - Return true if the range specified is entirely in the
268 /// isInOneLiveRange - Return true if the range specified is entirely in
264269 /// a single LiveRange of the live interval.
265 bool LiveInterval::isInOneLiveRange(unsigned Start, unsigned End) {
270 bool LiveInterval::isInOneLiveRange(MachineInstrIndex Start, MachineInstrIndex End) {
266271 Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
267272 if (I == ranges.begin())
268273 return false;
269274 --I;
270 return I->contains(Start) && I->contains(End-1);
275 return I->containsRange(Start, End);
271276 }
272277
273278
274279 /// removeRange - Remove the specified range from this interval. Note that
275280 /// the range must be in a single LiveRange in its entirety.
276 void LiveInterval::removeRange(unsigned Start, unsigned End,
281 void LiveInterval::removeRange(MachineInstrIndex Start, MachineInstrIndex End,
277282 bool RemoveDeadValNo) {
278283 // Find the LiveRange containing this span.
279284 Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
280285 assert(I != ranges.begin() && "Range is not in interval!");
281286 --I;
282 assert(I->contains(Start) && I->contains(End-1) &&
283 "Range is not entirely in interval!");
287 assert(I->containsRange(Start, End) && "Range is not entirely in interval!");
284288
285289 // If the span we are removing is at the start of the LiveRange, adjust it.
286290 VNInfo *ValNo = I->valno;
287291 if (I->start == Start) {
288292 if (I->end == End) {
289 removeKills(I->valno, Start, End);
293 ValNo->removeKills(Start, End);
290294 if (RemoveDeadValNo) {
291295 // Check if val# is dead.
292296 bool isDead = true;
320324 // Otherwise if the span we are removing is at the end of the LiveRange,
321325 // adjust the other way.
322326 if (I->end == End) {
323 removeKills(ValNo, Start, End);
327 ValNo->removeKills(Start, End);
324328 I->end = Start;
325329 return;
326330 }
327331
328332 // Otherwise, we are splitting the LiveRange into two pieces.
329 unsigned OldEnd = I->end;
333 MachineInstrIndex OldEnd = I->end;
330334 I->end = Start; // Trim the old interval.
331335
332336 // Insert the new one.
360364
361365 /// scaleNumbering - Renumber VNI and ranges to provide gaps for new
362366 /// instructions.
367
363368 void LiveInterval::scaleNumbering(unsigned factor) {
364369 // Scale ranges.
365370 for (iterator RI = begin(), RE = end(); RI != RE; ++RI) {
366 RI->start = InstrSlots::scale(RI->start, factor);
367 RI->end = InstrSlots::scale(RI->end, factor);
371 RI->start = RI->start.scale(factor);
372 RI->end = RI->end.scale(factor);
368373 }
369374
370375 // Scale VNI info.
372377 VNInfo *vni = *VNI;
373378
374379 if (vni->isDefAccurate())
375 vni->def = InstrSlots::scale(vni->def, factor);
380 vni->def = vni->def.scale(factor);
376381
377382 for (unsigned i = 0; i < vni->kills.size(); ++i) {
378 if (!vni->kills[i].isPHIKill)
379 vni->kills[i].killIdx =
380 InstrSlots::scale(vni->kills[i].killIdx, factor);
381 }
382 }
383 }
383 if (!vni->kills[i].isPHIIndex())
384 vni->kills[i] = vni->kills[i].scale(factor);
385 }
386 }
387 }
388
384389
385390 /// getLiveRangeContaining - Return the live range that contains the
386391 /// specified index, or null if there is none.
387392 LiveInterval::const_iterator
388 LiveInterval::FindLiveRangeContaining(unsigned Idx) const {
393 LiveInterval::FindLiveRangeContaining(MachineInstrIndex Idx) const {
389394 const_iterator It = std::upper_bound(begin(), end(), Idx);
390395 if (It != ranges.begin()) {
391396 --It;
397402 }
398403
399404 LiveInterval::iterator
400 LiveInterval::FindLiveRangeContaining(unsigned Idx) {
405 LiveInterval::FindLiveRangeContaining(MachineInstrIndex Idx) {
401406 iterator It = std::upper_bound(begin(), end(), Idx);
402407 if (It != begin()) {
403408 --It;
408413 return end();
409414 }
410415
411 /// findDefinedVNInfo - Find the VNInfo that's defined at the specified index
412 /// (register interval) or defined by the specified register (stack inteval).
413 VNInfo *LiveInterval::findDefinedVNInfo(unsigned DefIdxOrReg) const {
414 VNInfo *VNI = NULL;
416 /// findDefinedVNInfo - Find the VNInfo defined by the specified
417 /// index (register interval).
418 VNInfo *LiveInterval::findDefinedVNInfoForRegInt(MachineInstrIndex Idx) const {
415419 for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end();
416 i != e; ++i)
417 if ((*i)->def == DefIdxOrReg) {
418 VNI = *i;
419 break;
420 }
421 return VNI;
420 i != e; ++i) {
421 if ((*i)->def == Idx)
422 return *i;
423 }
424
425 return 0;
426 }
427
428 /// findDefinedVNInfo - Find the VNInfo defined by the specified
429 /// register (stack inteval).
430 VNInfo *LiveInterval::findDefinedVNInfoForStackInt(unsigned reg) const {
431 for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end();
432 i != e; ++i) {
433 if ((*i)->getReg() == reg)
434 return *i;
435 }
436 return 0;
422437 }
423438
424439 /// join - Join two live intervals (this, and other) together. This applies
545560 for (const_iterator I = RHS.begin(), E = RHS.end(); I != E; ++I) {
546561 if (I->valno != RHSValNo)
547562 continue;
548 unsigned Start = I->start, End = I->end;
563 MachineInstrIndex Start = I->start, End = I->end;
549564 IP = std::upper_bound(IP, end(), Start);
550565 // If the start of this range overlaps with an existing liverange, trim it.
551566 if (IP != begin() && IP[-1].end > Start) {
621636 else if (UnusedValNo)
622637 ClobberValNo = UnusedValNo;
623638 else {
624 UnusedValNo = ClobberValNo = getNextValue(0, 0, false, VNInfoAllocator);
639 UnusedValNo = ClobberValNo =
640 getNextValue(MachineInstrIndex(), 0, false, VNInfoAllocator);
625641 ValNoMaps.insert(std::make_pair(I->valno, ClobberValNo));
626642 }
627643
628644 bool Done = false;
629 unsigned Start = I->start, End = I->end;
645 MachineInstrIndex Start = I->start, End = I->end;
630646 // If a clobber range starts before an existing range and ends after
631647 // it, the clobber range will need to be split into multiple ranges.
632648 // Loop until the entire clobber range is handled.
633649 while (!Done) {
634650 Done = true;
635651 IP = std::upper_bound(IP, end(), Start);
636 unsigned SubRangeStart = Start;
637 unsigned SubRangeEnd = End;
652 MachineInstrIndex SubRangeStart = Start;
653 MachineInstrIndex SubRangeEnd = End;
638654
639655 // If the start of this range overlaps with an existing liverange, trim it.
640656 if (IP != begin() && IP[-1].end > SubRangeStart) {
670686 }
671687 }
672688
673 void LiveInterval::MergeInClobberRange(unsigned Start, unsigned End,
689 void LiveInterval::MergeInClobberRange(MachineInstrIndex Start,
690 MachineInstrIndex End,
674691 BumpPtrAllocator &VNInfoAllocator) {
675692 // Find a value # to use for the clobber ranges. If there is already a value#
676693 // for unknown values, use it.
677 VNInfo *ClobberValNo = getNextValue(0, 0, false, VNInfoAllocator);
694 VNInfo *ClobberValNo =
695 getNextValue(MachineInstrIndex(), 0, false, VNInfoAllocator);
678696
679697 iterator IP = begin();
680698 IP = std::upper_bound(IP, end(), Start);
787805 unsigned LiveInterval::getSize() const {
788806 unsigned Sum = 0;
789807 for (const_iterator I = begin(), E = end(); I != E; ++I)
790 Sum += I->end - I->start;
808 Sum += I->start.distance(I->end);
791809 return Sum;
792810 }
793811
861879 if (ee || vni->hasPHIKill()) {
862880 OS << "-(";
863881 for (unsigned j = 0; j != ee; ++j) {
864 OS << vni->kills[j].killIdx;
865 if (vni->kills[j].isPHIKill)
882 OS << vni->kills[j];
883 if (vni->kills[j].isPHIIndex())
866884 OS << "*";
867885 if (j != ee-1)
868886 OS << " ";
253253 }
254254 }
255255
256
256257 void LiveIntervals::computeNumbering() {
257258 Index2MiMap OldI2MI = i2miMap_;
258259 std::vector OldI2MBB = Idx2MBBMap;
267268
268269 // Number MachineInstrs and MachineBasicBlocks.
269270 // Initialize MBB indexes to a sentinal.
270 MBB2IdxMap.resize(mf_->getNumBlockIDs(), std::make_pair(~0U,~0U));
271 MBB2IdxMap.resize(mf_->getNumBlockIDs(),
272 std::make_pair(MachineInstrIndex(),MachineInstrIndex()));
271273
272 unsigned MIIndex = 0;
274 MachineInstrIndex MIIndex;
273275 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
274276 MBB != E; ++MBB) {
275 unsigned StartIdx = MIIndex;
277 MachineInstrIndex StartIdx = MIIndex;
276278
277279 // Insert an empty slot at the beginning of each block.
278 MIIndex += InstrSlots::NUM;
280 MIIndex = MIIndex.nextIndex();
279281 i2miMap_.push_back(0);
280282
281283 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
284286 if (I == MBB->getFirstTerminator()) {
285287 // Leave a gap for before terminators, this is where we will point
286288 // PHI kills.
289 MachineInstrIndex tGap(true, MIIndex);
287290 bool inserted =
288 terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
291 terminatorGaps.insert(std::make_pair(&*MBB, tGap)).second;
289292 assert(inserted &&
290293 "Multiple 'first' terminators encountered during numbering.");
291294 inserted = inserted; // Avoid compiler warning if assertions turned off.
292295 i2miMap_.push_back(0);
293296
294 MIIndex += InstrSlots::NUM;
297 MIIndex = MIIndex.nextIndex();
295298 }
296299
297300 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
298301 assert(inserted && "multiple MachineInstr -> index mappings");
299302 inserted = true;
300303 i2miMap_.push_back(I);
301 MIIndex += InstrSlots::NUM;
304 MIIndex = MIIndex.nextIndex();
302305 FunctionSize++;
303306
304307 // Insert max(1, numdefs) empty slots after every instruction.
305308 unsigned Slots = I->getDesc().getNumDefs();
306309 if (Slots == 0)
307310 Slots = 1;
308 MIIndex += InstrSlots::NUM * Slots;
309 while (Slots--)
311 while (Slots--) {
312 MIIndex = MIIndex.nextIndex();
310313 i2miMap_.push_back(0);
314 }
315
311316 }
312317
313318 if (MBB->getFirstTerminator() == MBB->end()) {
314319 // Leave a gap for before terminators, this is where we will point
315320 // PHI kills.
321 MachineInstrIndex tGap(true, MIIndex);
316322 bool inserted =
317 terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
323 terminatorGaps.insert(std::make_pair(&*MBB, tGap)).second;
318324 assert(inserted &&
319325 "Multiple 'first' terminators encountered during numbering.");
320326 inserted = inserted; // Avoid compiler warning if assertions turned off.
321327 i2miMap_.push_back(0);
322328
323 MIIndex += InstrSlots::NUM;
329 MIIndex = MIIndex.nextIndex();
324330 }
325331
326332 // Set the MBB2IdxMap entry for this MBB.
327 MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
333 MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex.prevSlot());
328334 Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
329335 }
330336
339345 // number, or our best guess at what it _should_ correspond to if the
340346 // original instruction has been erased. This is either the following
341347 // instruction or its predecessor.
342 unsigned index = LI->start / InstrSlots::NUM;
343 unsigned offset = LI->start % InstrSlots::NUM;
344 if (offset == InstrSlots::LOAD) {
348 unsigned index = LI->start.getVecIndex();
349 MachineInstrIndex::Slot offset = LI->start.getSlot();
350 if (LI->start.isLoad()) {
345351 std::vector::const_iterator I =
346352 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->start);
347353 // Take the pair containing the index
350356
351357 LI->start = getMBBStartIdx(J->second);
352358 } else {
353 LI->start = mi2iMap_[OldI2MI[index]] + offset;
359 LI->start = MachineInstrIndex(
360 MachineInstrIndex(mi2iMap_[OldI2MI[index]]),
361 (MachineInstrIndex::Slot)offset);
354362 }
355363
356364 // Remap the ending index in the same way that we remapped the start,
357365 // except for the final step where we always map to the immediately
358366 // following instruction.
359 index = (LI->end - 1) / InstrSlots::NUM;
360 offset = LI->end % InstrSlots::NUM;
361 if (offset == InstrSlots::LOAD) {
367 index = (LI->end.prevSlot()).getVecIndex();
368 offset = LI->end.getSlot();
369 if (LI->end.isLoad()) {
362370 // VReg dies at end of block.
363371 std::vector::const_iterator I =
364372 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
365373 --I;
366374
367 LI->end = getMBBEndIdx(I->second) + 1;
375 LI->end = getMBBEndIdx(I->second).nextSlot();
368376 } else {
369377 unsigned idx = index;
370378 while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
371379
372380 if (index != OldI2MI.size())
373 LI->end = mi2iMap_[OldI2MI[index]] + (idx == index ? offset : 0);
381 LI->end =
382 MachineInstrIndex(mi2iMap_[OldI2MI[index]],
383 (idx == index ? offset : MachineInstrIndex::LOAD));
374384 else
375 LI->end = InstrSlots::NUM * i2miMap_.size();
385 LI->end =
386 MachineInstrIndex(MachineInstrIndex::NUM * i2miMap_.size());
376387 }
377388 }
378389
384395 // start indices above. VN's with special sentinel defs
385396 // don't need to be remapped.
386397 if (vni->isDefAccurate() && !vni->isUnused()) {
387 unsigned index = vni->def / InstrSlots::NUM;
388 unsigned offset = vni->def % InstrSlots::NUM;
389 if (offset == InstrSlots::LOAD) {
398 unsigned index = vni->def.getVecIndex();
399 MachineInstrIndex::Slot offset = vni->def.getSlot();
400 if (vni->def.isLoad()) {
390401 std::vector::const_iterator I =
391402 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->def);
392403 // Take the pair containing the index
395406
396407 vni->def = getMBBStartIdx(J->second);
397408 } else {
398 vni->def = mi2iMap_[OldI2MI[index]] + offset;
409 vni->def = MachineInstrIndex(mi2iMap_[OldI2MI[index]], offset);
399410 }
400411 }
401412
402413 // Remap the VNInfo kill indices, which works the same as
403414 // the end indices above.
404415 for (size_t i = 0; i < vni->kills.size(); ++i) {
405 unsigned killIdx = vni->kills[i].killIdx;
406
407 unsigned index = (killIdx - 1) / InstrSlots::NUM;
408 unsigned offset = killIdx % InstrSlots::NUM;
409
410 if (offset == InstrSlots::LOAD) {
416 unsigned index = vni->kills[i].prevSlot().getVecIndex();
417 MachineInstrIndex::Slot offset = vni->kills[i].getSlot();
418
419 if (vni->kills[i].isLoad()) {
411420 assert("Value killed at a load slot.");
412421 /*std::vector::const_iterator I =
413422 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
415424
416425 vni->kills[i] = getMBBEndIdx(I->second);*/
417426 } else {
418 if (vni->kills[i].isPHIKill) {
427 if (vni->kills[i].isPHIIndex()) {
419428 std::vector::const_iterator I =
420 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), index);
429 std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
421430 --I;
422 vni->kills[i].killIdx = terminatorGaps[I->second];
431 vni->kills[i] = terminatorGaps[I->second];
423432 } else {
424433 assert(OldI2MI[index] != 0 &&
425434 "Kill refers to instruction not present in index maps.");
426 vni->kills[i].killIdx = mi2iMap_[OldI2MI[index]] + offset;
435 vni->kills[i] = MachineInstrIndex(mi2iMap_[OldI2MI[index]], offset);
427436 }
428437
429438 /*
453462 Idx2MBBMap.clear();
454463 for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end();
455464 MBB != MBBE; ++MBB) {
456 std::pair &mbbIndices = MBB2IdxMap[MBB->getNumber()];
457 mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor);
458 mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor);
465 std::pair &mbbIndices = MBB2IdxMap[MBB->getNumber()];
466 mbbIndices.first = mbbIndices.first.scale(factor);
467 mbbIndices.second = mbbIndices.second.scale(factor);
459468 Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB));
460469 }
461470 std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
462471
463472 // Scale terminator gaps.
464 for (DenseMapunsigned>::iterator
473 for (DenseMapMachineInstrIndex>::iterator
465474 TGI = terminatorGaps.begin(), TGE = terminatorGaps.end();
466475 TGI != TGE; ++TGI) {
467 terminatorGaps[TGI->first] = InstrSlots::scale(TGI->second, factor);
476 terminatorGaps[TGI->first] = TGI->second.scale(factor);
468477 }
469478
470479 // Scale the intervals.
474483
475484 // Scale MachineInstrs.
476485 Mi2IndexMap oldmi2iMap = mi2iMap_;
477 unsigned highestSlot = 0;
486 MachineInstrIndex highestSlot;
478487 for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end();
479488 MI != ME; ++MI) {
480 unsigned newSlot = InstrSlots::scale(MI->second, factor);
489 MachineInstrIndex newSlot = MI->second.scale(factor);
481490 mi2iMap_[MI->first] = newSlot;
482491 highestSlot = std::max(highestSlot, newSlot);
483492 }
484493
494 unsigned highestVIndex = highestSlot.getVecIndex();
485495 i2miMap_.clear();
486 i2miMap_.resize(highestSlot + 1);
496 i2miMap_.resize(highestVIndex + 1);
487497 for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end();
488498 MI != ME; ++MI) {
489 i2miMap_[MI->second] = const_cast(MI->first);
499 i2miMap_[MI->second.getVecIndex()] = const_cast(MI->first);
490500 }
491501
492502 }
540550 VirtRegMap &vrm, unsigned reg) {
541551 for (LiveInterval::Ranges::const_iterator
542552 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
543 for (unsigned index = getBaseIndex(I->start),
544 end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
545 index += InstrSlots::NUM) {
553 for (MachineInstrIndex index = getBaseIndex(I->start),
554 end = getBaseIndex(I->end.prevSlot()).nextIndex(); index != end;
555 index = index.nextIndex()) {
546556 // skip deleted instructions
547557 while (index != end && !getInstructionFromIndex(index))
548 index += InstrSlots::NUM;
558 index = index.nextIndex();
549559 if (index == end) break;
550560
551561 MachineInstr *MI = getInstructionFromIndex(index);
581591 SmallPtrSet &JoinedCopies) {
582592 for (LiveInterval::Ranges::const_iterator
583593 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
584 for (unsigned index = getBaseIndex(I->start),
585 end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
586 index += InstrSlots::NUM) {
594 for (MachineInstrIndex index = getBaseIndex(I->start),
595 end = getBaseIndex(I->end.prevSlot()).nextIndex(); index != end;
596 index = index.nextIndex()) {
587597 // Skip deleted instructions.
588598 MachineInstr *MI = 0;
589599 while (index != end) {
590600 MI = getInstructionFromIndex(index);
591601 if (MI)
592602 break;
593 index += InstrSlots::NUM;
603 index = index.nextIndex();
594604 }
595605 if (index == end) break;
596606
624634
625635 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
626636 MachineBasicBlock::iterator mi,
627 unsigned MIIdx, MachineOperand& MO,
637 MachineInstrIndex MIIdx,
638 MachineOperand& MO,
628639 unsigned MOIdx,
629640 LiveInterval &interval) {
630641 DEBUG({
639650 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
640651 if (interval.empty()) {
641652 // Get the Idx of the defining instructions.
642 unsigned defIndex = getDefIndex(MIIdx);
653 MachineInstrIndex defIndex = getDefIndex(MIIdx);
643654 // Earlyclobbers move back one.
644655 if (MO.isEarlyClobber())
645656 defIndex = getUseIndex(MIIdx);
662673 // will be a single kill, in MBB, which comes after the definition.
663674 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
664675 // FIXME: what about dead vars?
665 unsigned killIdx;
676 MachineInstrIndex killIdx;
666677 if (vi.Kills[0] != mi)
667 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
678 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0])).nextSlot();
668679 else
669 killIdx = defIndex+1;
680 killIdx = defIndex.nextSlot();
670681
671682 // If the kill happens after the definition, we have an intra-block
672683 // live range.
676687 LiveRange LR(defIndex, killIdx, ValNo);
677688 interval.addRange(LR);
678689 DEBUG(errs() << " +" << LR << "\n");
679 interval.addKill(ValNo, killIdx, false);
690 ValNo->addKill(killIdx);
680691 return;
681692 }
682693 }
685696 // of the defining block, potentially live across some blocks, then is
686697 // live into some number of blocks, but gets killed. Start by adding a
687698 // range that goes from this definition to the end of the defining block.
688 LiveRange NewLR(defIndex, getMBBEndIdx(mbb)+1, ValNo);
699 LiveRange NewLR(defIndex, getMBBEndIdx(mbb).nextSlot(), ValNo);
689700 DEBUG(errs() << " +" << NewLR);
690701 interval.addRange(NewLR);
691702
695706 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
696707 E = vi.AliveBlocks.end(); I != E; ++I) {
697708 LiveRange LR(getMBBStartIdx(*I),
698 getMBBEndIdx(*I)+1, // MBB ends at -1.
709 getMBBEndIdx(*I).nextSlot(), // MBB ends at -1.
699710 ValNo);
700711 interval.addRange(LR);
701712 DEBUG(errs() << " +" << LR);
705716 // block to the 'use' slot of the killing instruction.
706717 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
707718 MachineInstr *Kill = vi.Kills[i];
708 unsigned killIdx = getUseIndex(getInstructionIndex(Kill))+1;
719 MachineInstrIndex killIdx = getUseIndex(getInstructionIndex(Kill)).nextSlot();
709720 LiveRange LR(getMBBStartIdx(Kill->getParent()),
710721 killIdx, ValNo);
711722 interval.addRange(LR);
712 interval.addKill(ValNo, killIdx, false);
723 ValNo->addKill(killIdx);
713724 DEBUG(errs() << " +" << LR);
714725 }
715726
725736 // need to take the LiveRegion that defines this register and split it
726737 // into two values.
727738 assert(interval.containsOneValue());
728 unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
729 unsigned RedefIndex = getDefIndex(MIIdx);
739 MachineInstrIndex DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
740 MachineInstrIndex RedefIndex = getDefIndex(MIIdx);
730741 if (MO.isEarlyClobber())
731742 RedefIndex = getUseIndex(MIIdx);
732743
733 const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
744 const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex.prevSlot());
734745 VNInfo *OldValNo = OldLR->valno;
735746
736747 // Delete the initial value, which should be short and continuous,
758769 LiveRange LR(DefIndex, RedefIndex, ValNo);
759770 DEBUG(errs() << " replace range with " << LR);
760771 interval.addRange(LR);
761 interval.addKill(ValNo, RedefIndex, false);
772 ValNo->addKill(RedefIndex);
762773
763774 // If this redefinition is dead, we need to add a dummy unit live
764775 // range covering the def slot.
765776 if (MO.isDead())
766 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
777 interval.addRange(LiveRange(RedefIndex, RedefIndex.nextSlot(), OldValNo));
767778
768779 DEBUG({
769780 errs() << " RESULT: ";
780791 // Remove the old range that we now know has an incorrect number.
781792 VNInfo *VNI = interval.getValNumInfo(0);
782793 MachineInstr *Killer = vi.Kills[0];
783 unsigned Start = getMBBStartIdx(Killer->getParent());
784 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
794 MachineInstrIndex Start = getMBBStartIdx(Killer->getParent());
795 MachineInstrIndex End = getUseIndex(getInstructionIndex(Killer)).nextSlot();
785796 DEBUG({
786797 errs() << " Removing [" << Start << "," << End << "] from: ";
787798 interval.print(errs(), tri_);
790801 interval.removeRange(Start, End);
791802 assert(interval.ranges.size() == 1 &&
792803 "newly discovered PHI interval has >1 ranges.");
793 MachineBasicBlock *killMBB = getMBBFromIndex(interval.endNumber());
794 interval.addKill(VNI, terminatorGaps[killMBB], true);
804 MachineBasicBlock *killMBB = getMBBFromIndex(interval.endIndex());
805 VNI->addKill(terminatorGaps[killMBB]);
795806 VNI->setHasPHIKill(true);
796807 DEBUG({
797808 errs() << " RESULT: ";
801812 // Replace the interval with one of a NEW value number. Note that this
802813 // value number isn't actually defined by an instruction, weird huh? :)
803814 LiveRange LR(Start, End,
804 interval.getNextValue(mbb->getNumber(), 0, false, VNInfoAllocator));
815 interval.getNextValue(MachineInstrIndex(mbb->getNumber()),
816 0, false, VNInfoAllocator));
805817 LR.valno->setIsPHIDef(true);
806818 DEBUG(errs() << " replace range with " << LR);
807819 interval.addRange(LR);
808 interval.addKill(LR.valno, End, false);
820 LR.valno->addKill(End);
809821 DEBUG({
810822 errs() << " RESULT: ";
811823 interval.print(errs(), tri_);
815827 // In the case of PHI elimination, each variable definition is only
816828 // live until the end of the block. We've already taken care of the
817829 // rest of the live range.
818 unsigned defIndex = getDefIndex(MIIdx);
830 MachineInstrIndex defIndex = getDefIndex(MIIdx);
819831 if (MO.isEarlyClobber())
820832 defIndex = getUseIndex(MIIdx);
821833
829841 CopyMI = mi;
830842 ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
831843
832 unsigned killIndex = getMBBEndIdx(mbb) + 1;
844 MachineInstrIndex killIndex = getMBBEndIdx(mbb).nextSlot();
833845 LiveRange LR(defIndex, killIndex, ValNo);
834846 interval.addRange(LR);
835 interval.addKill(ValNo, terminatorGaps[mbb], true);
847 ValNo->addKill(terminatorGaps[mbb]);
836848 ValNo->setHasPHIKill(true);
837849 DEBUG(errs() << " +" << LR);
838850 }
843855
844856 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
845857 MachineBasicBlock::iterator mi,
846 unsigned MIIdx,
858 MachineInstrIndex MIIdx,
847859 MachineOperand& MO,
848860 LiveInterval &interval,
849861 MachineInstr *CopyMI) {
854866 printRegName(interval.reg);
855867 });
856868
857 unsigned baseIndex = MIIdx;
858 unsigned start = getDefIndex(baseIndex);
869 MachineInstrIndex baseIndex = MIIdx;
870 MachineInstrIndex start = getDefIndex(baseIndex);
859871 // Earlyclobbers move back one.
860872 if (MO.isEarlyClobber())
861873 start = getUseIndex(MIIdx);
862 unsigned end = start;
874 MachineInstrIndex end = start;
863875
864876 // If it is not used after definition, it is considered dead at
865877 // the instruction defining it. Hence its interval is:
866878 // [defSlot(def), defSlot(def)+1)
867879 if (MO.isDead()) {
868880 DEBUG(errs() << " dead");
869 end = start + 1;
881 end = start.nextSlot();
870882 goto exit;
871883 }
872884
873885 // If it is not dead on definition, it must be killed by a
874886 // subsequent instruction. Hence its interval is:
875887 // [defSlot(def), useSlot(kill)+1)
876 baseIndex += InstrSlots::NUM;
888 baseIndex = baseIndex.nextIndex();
877889 while (++mi != MBB->end()) {
878 while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
890 while (baseIndex.getVecIndex() < i2miMap_.size() &&
879891 getInstructionFromIndex(baseIndex) == 0)
880 baseIndex += InstrSlots::NUM;
892 baseIndex = baseIndex.nextIndex();
881893 if (mi->killsRegister(interval.reg, tri_)) {
882894 DEBUG(errs() << " killed");
883 end = getUseIndex(baseIndex) + 1;
895 end = getUseIndex(baseIndex).nextSlot();
884896 goto exit;
885897 } else {
886898 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_);
896908 // it. Hence its interval is:
897909 // [defSlot(def), defSlot(def)+1)
898910 DEBUG(errs() << " dead");
899 end = start + 1;
911 end = start.nextSlot();
900912 }
901913 goto exit;
902914 }
903915 }
904916
905 baseIndex += InstrSlots::NUM;
917 baseIndex = baseIndex.nextIndex();
906918 }
907919
908920 // The only case we should have a dead physreg here without a killing or
909921 // instruction where we know it's dead is if it is live-in to the function
910922 // and never used. Another possible case is the implicit use of the
911923 // physical register has been deleted by two-address pass.
912 end = start + 1;
924 end = start.nextSlot();
913925
914926 exit:
915927 assert(start < end && "did not find end of interval?");
923935 ValNo->setHasRedefByEC(true);
924936 LiveRange LR(start, end, ValNo);
925937 interval.addRange(LR);
926 interval.addKill(LR.valno, end, false);
938 LR.valno->addKill(end);
927939 DEBUG(errs() << " +" << LR << '\n');
928940 }
929941
930942 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
931943 MachineBasicBlock::iterator MI,
932 unsigned MIIdx,
944 MachineInstrIndex MIIdx,
933945 MachineOperand& MO,
934946 unsigned MOIdx) {
935947 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
956968 }
957969
958970 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
959 unsigned MIIdx,
971 MachineInstrIndex MIIdx,
960972 LiveInterval &interval, bool isAlias) {
961973 DEBUG({
962974 errs() << "\t\tlivein register: ";
966978 // Look for kills, if it reaches a def before it's killed, then it shouldn't
967979 // be considered a livein.
968980 MachineBasicBlock::iterator mi = MBB->begin();
969 unsigned baseIndex = MIIdx;
970 unsigned start = baseIndex;
971 while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
981 MachineInstrIndex baseIndex = MIIdx;
982 MachineInstrIndex start = baseIndex;
983 while (baseIndex.getVecIndex() < i2miMap_.size() &&
972984 getInstructionFromIndex(baseIndex) == 0)
973 baseIndex += InstrSlots::NUM;
974 unsigned end = baseIndex;
985 baseIndex = baseIndex.nextIndex();
986 MachineInstrIndex end = baseIndex;
975987 bool SeenDefUse = false;
976988
977989 while (mi != MBB->end()) {
978990 if (mi->killsRegister(interval.reg, tri_)) {
979991 DEBUG(errs() << " killed");
980 end = getUseIndex(baseIndex) + 1;
992 end = getUseIndex(baseIndex).nextSlot();
981993 SeenDefUse = true;
982994 break;
983995 } else if (mi->modifiesRegister(interval.reg, tri_)) {
986998 // it. Hence its interval is:
987999 // [defSlot(def), defSlot(def)+1)
9881000 DEBUG(errs() << " dead");
989 end = getDefIndex(start) + 1;
1001 end = getDefIndex(start).nextSlot();
9901002 SeenDefUse = true;
9911003 break;
9921004 }
9931005
994 baseIndex += InstrSlots::NUM;
1006 baseIndex = baseIndex.nextIndex();
9951007 ++mi;
9961008 if (mi != MBB->end()) {
997 while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
1009 while (baseIndex.getVecIndex() < i2miMap_.size() &&
9981010 getInstructionFromIndex(baseIndex) == 0)
999 baseIndex += InstrSlots::NUM;
1011 baseIndex = baseIndex.nextIndex();
10001012 }
10011013 }
10021014
10041016 if (!SeenDefUse) {
10051017 if (isAlias) {
10061018 DEBUG(errs() << " dead");
1007 end = getDefIndex(MIIdx) + 1;
1019 end = getDefIndex(MIIdx).nextSlot();
10081020 } else {
10091021 DEBUG(errs() << " live through");
10101022 end = baseIndex;
10121024 }
10131025
10141026 VNInfo *vni =
1015 interval.getNextValue(MBB->getNumber(), 0, false, VNInfoAllocator);
1027 interval.getNextValue(MachineInstrIndex(MBB->getNumber()),
1028 0, false, VNInfoAllocator);
10161029 vni->setIsPHIDef(true);
10171030 LiveRange LR(start, end, vni);
10181031
10191032 interval.addRange(LR);
1020 interval.addKill(LR.valno, end, false);
1033 LR.valno->addKill(end);
10211034 DEBUG(errs() << " +" << LR << '\n');
10221035 }
10231036
10351048 MBBI != E; ++MBBI) {
10361049 MachineBasicBlock *MBB = MBBI;
10371050 // Track the index of the current machine instr.
1038 unsigned MIIndex = getMBBStartIdx(MBB);
1051 MachineInstrIndex MIIndex = getMBBStartIdx(MBB);
10391052 DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
10401053
10411054 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
10521065 }
10531066
10541067 // Skip over empty initial indices.
1055 while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
1068 while (MIIndex.getVecIndex() < i2miMap_.size() &&
10561069 getInstructionFromIndex(MIIndex) == 0)
1057 MIIndex += InstrSlots::NUM;
1070 MIIndex = MIIndex.nextIndex();
10581071
10591072 for (; MI != miEnd; ++MI) {
10601073 DEBUG(errs() << MIIndex << "\t" << *MI);
10761089 unsigned Slots = MI->getDesc().getNumDefs();
10771090 if (Slots == 0)
10781091 Slots = 1;
1079 MIIndex += InstrSlots::NUM * Slots;
1092
1093 while (Slots--)
1094 MIIndex = MIIndex.nextIndex();
10801095
10811096 // Skip over empty indices.
1082 while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
1097 while (MIIndex.getVecIndex() < i2miMap_.size() &&
10831098 getInstructionFromIndex(MIIndex) == 0)
1084 MIIndex += InstrSlots::NUM;
1099 MIIndex = MIIndex.nextIndex();
10851100 }
10861101 }
10871102
10941109 }
10951110 }
10961111
1097 bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
1112 bool LiveIntervals::findLiveInMBBs(
1113 MachineInstrIndex Start, MachineInstrIndex End,
10981114 SmallVectorImpl &MBBs) const {
10991115 std::vector::const_iterator I =
11001116 std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
11101126 return ResVal;
11111127 }
11121128
1113 bool LiveIntervals::findReachableMBBs(unsigned Start, unsigned End,
1129 bool LiveIntervals::findReachableMBBs(
1130 MachineInstrIndex Start, MachineInstrIndex End,
11141131 SmallVectorImpl &MBBs) const {
11151132 std::vector::const_iterator I =
11161133 std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
12021219 /// isValNoAvailableAt - Return true if the val# of the specified interval
12031220 /// which reaches the given instruction also reaches the specified use index.
12041221 bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
1205 unsigned UseIdx) const {
1206 unsigned Index = getInstructionIndex(MI);
1222 MachineInstrIndex UseIdx) const {
1223 MachineInstrIndex Index = getInstructionIndex(MI);
12071224 VNInfo *ValNo = li.FindLiveRangeContaining(Index)->valno;
12081225 LiveInterval::const_iterator UI = li.FindLiveRangeContaining(UseIdx);
12091226 return UI != li.end() && UI->valno == ValNo;
13131330 for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
13141331 re = mri_->use_end(); ri != re; ++ri) {
13151332 MachineInstr *UseMI = &*ri;
1316 unsigned UseIdx = getInstructionIndex(UseMI);
1333 MachineInstrIndex UseIdx = getInstructionIndex(UseMI);
13171334 if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
13181335 continue;
13191336 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
13981415 /// returns true.
13991416 bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
14001417 VirtRegMap &vrm, MachineInstr *DefMI,
1401 unsigned InstrIdx,
1418 MachineInstrIndex InstrIdx,
14021419 SmallVector &Ops,
14031420 bool isSS, int Slot, unsigned Reg) {
14041421 // If it is an implicit def instruction, just delete it.
14371454 vrm.transferRestorePts(MI, fmi);
14381455 vrm.transferEmergencySpills(MI, fmi);
14391456 mi2iMap_.erase(MI);
1440 i2miMap_[InstrIdx /InstrSlots::NUM] = fmi;
1457 i2miMap_[InstrIdx.getVecIndex()] = fmi;
14411458 mi2iMap_[fmi] = InstrIdx;
14421459 MI = MBB.insert(MBB.erase(MI), fmi);
14431460 ++numFolds;
15101527 /// for addIntervalsForSpills to rewrite uses / defs for the given live range.
15111528 bool LiveIntervals::
15121529 rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
1513 bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
1530 bool TrySplit, MachineInstrIndex index, MachineInstrIndex end,
1531 MachineInstr *MI,
15141532 MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
15151533 unsigned Slot, int LdSlot,
15161534 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
16861704
16871705 if (HasUse) {
16881706 if (CreatedNewVReg) {
1689 LiveRange LR(getLoadIndex(index), getUseIndex(index)+1,
1690 nI.getNextValue(0, 0, false, VNInfoAllocator));
1707 LiveRange LR(getLoadIndex(index), getUseIndex(index).nextSlot(),
1708 nI.getNextValue(MachineInstrIndex(), 0, false,
1709 VNInfoAllocator));
16911710 DEBUG(errs() << " +" << LR);
16921711 nI.addRange(LR);
16931712 } else {
16941713 // Extend the split live interval to this def / use.
1695 unsigned End = getUseIndex(index)+1;
1714 MachineInstrIndex End = getUseIndex(index).nextSlot();
16961715 LiveRange LR(nI.ranges[nI.ranges.size()-1].end, End,
16971716 nI.getValNumInfo(nI.getNumValNums()-1));
16981717 DEBUG(errs() << " +" << LR);
17011720 }
17021721 if (HasDef) {
17031722 LiveRange LR(getDefIndex(index), getStoreIndex(index),
1704 nI.getNextValue(0, 0, false, VNInfoAllocator));
1723 nI.getNextValue(MachineInstrIndex(), 0, false,
1724 VNInfoAllocator));
17051725 DEBUG(errs() << " +" << LR);
17061726 nI.addRange(LR);
17071727 }
17161736 }
17171737 bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li,
17181738 const VNInfo *VNI,
1719 MachineBasicBlock *MBB, unsigned Idx) const {
1720 unsigned End = getMBBEndIdx(MBB);
1739 MachineBasicBlock *MBB,
1740 MachineInstrIndex Idx) const {
1741 MachineInstrIndex End = getMBBEndIdx(MBB);
17211742 for (unsigned j = 0, ee = VNI->kills.size(); j != ee; ++j) {
1722 if (VNI->kills[j].isPHIKill)
1743 if (VNI->kills[j].isPHIIndex())
17231744 continue;
17241745
1725 unsigned KillIdx = VNI->kills[j].killIdx;
1746 MachineInstrIndex KillIdx = VNI->kills[j];
17261747 if (KillIdx > Idx && KillIdx < End)
17271748 return true;
17281749 }
17331754 /// during spilling.
17341755 namespace {
17351756 struct RewriteInfo {
1736 unsigned Index;
1757 MachineInstrIndex Index;
17371758 MachineInstr *MI;
17381759 bool HasUse;
17391760 bool HasDef;
1740 RewriteInfo(unsigned i, MachineInstr *mi, bool u, bool d)
1761 RewriteInfo(MachineInstrIndex i, MachineInstr *mi, bool u, bool d)
17411762 : Index(i), MI(mi), HasUse(u), HasDef(d) {}
17421763 };
17431764
17661787 std::vector &NewLIs) {
17671788 bool AllCanFold = true;
17681789 unsigned NewVReg = 0;
1769 unsigned start = getBaseIndex(I->start);
1770 unsigned end = getBaseIndex(I->end-1) + InstrSlots::NUM;
1790 MachineInstrIndex start = getBaseIndex(I->start);
1791 MachineInstrIndex end = getBaseIndex(I->end.prevSlot()).nextIndex();
17711792
17721793 // First collect all the def / use in this live range that will be rewritten.
17731794 // Make sure they are sorted according to instruction index.
17781799 MachineOperand &O = ri.getOperand();
17791800 ++ri;
17801801 assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
1781 unsigned index = getInstructionIndex(MI);
1802 MachineInstrIndex index = getInstructionIndex(MI);
17821803 if (index < start || index >= end)
17831804 continue;
17841805
18021823 for (unsigned i = 0, e = RewriteMIs.size(); i != e; ) {
18031824 RewriteInfo &rwi = RewriteMIs[i];
18041825 ++i;
1805 unsigned index = rwi.Index;
1826 MachineInstrIndex index = rwi.Index;
18061827 bool MIHasUse = rwi.HasUse;
18071828 bool MIHasDef = rwi.HasDef;
18081829 MachineInstr *MI = rwi.MI;
18881909 HasKill = anyKillInMBBAfterIdx(li, I->valno, MBB, getDefIndex(index));
18891910 else {
18901911 // If this is a two-address code, then this index starts a new VNInfo.
1891 const VNInfo *VNI = li.findDefinedVNInfo(getDefIndex(index));
1912 const VNInfo *VNI = li.findDefinedVNInfoForRegInt(getDefIndex(index));
18921913 if (VNI)
18931914 HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index));
18941915 }
19011922 SpillIdxes.insert(std::make_pair(MBBId, S));
19021923 } else if (SII->second.back().vreg != NewVReg) {
19031924 SII->second.push_back(SRInfo(index, NewVReg, true));
1904 } else if ((int)index > SII->second.back().index) {
1925 } else if (index > SII->second.back().index) {
19051926 // If there is an earlier def and this is a two-address
19061927 // instruction, then it's not possible to fold the store (which
19071928 // would also fold the load).
19121933 SpillMBBs.set(MBBId);
19131934 } else if (SII != SpillIdxes.end() &&
19141935 SII->second.back().vreg == NewVReg &&
1915 (int)index > SII->second.back().index) {
1936 index > SII->second.back().index) {
19161937 // There is an earlier def that's not killed (must be two-address).
19171938 // The spill is no longer needed.
19181939 SII->second.pop_back();
19291950 SpillIdxes.find(MBBId);
19301951 if (SII != SpillIdxes.end() &&
19311952 SII->second.back().vreg == NewVReg &&
1932 (int)index > SII->second.back().index)
1953 index > SII->second.back().index)
19331954 // Use(s) following the last def, it's not safe to fold the spill.
19341955 SII->second.back().canFold = false;
19351956 DenseMap >::iterator RII =
19631984 }
19641985 }
19651986
1966 bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
1967 BitVector &RestoreMBBs,
1987 bool LiveIntervals::alsoFoldARestore(int Id, MachineInstrIndex index,
1988 unsigned vr, BitVector &RestoreMBBs,
19681989 DenseMap > &RestoreIdxes) {
19691990 if (!RestoreMBBs[Id])
19701991 return false;
19771998 return false;
19781999 }
19792000
1980 void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
1981 BitVector &RestoreMBBs,
2001 void LiveIntervals::eraseRestoreInfo(int Id, MachineInstrIndex index,
2002 unsigned vr, BitVector &RestoreMBBs,
19822003 DenseMap > &RestoreIdxes) {
19832004 if (!RestoreMBBs[Id])
19842005 return;
19852006 std::vector &Restores = RestoreIdxes[Id];
19862007 for (unsigned i = 0, e = Restores.size(); i != e; ++i)
19872008 if (Restores[i].index == index && Restores[i].vreg)
1988 Restores[i].index = -1;
2009 Restores[i].index = MachineInstrIndex();
19892010 }
19902011
19912012 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
20842105 }
20852106
20862107 // Fill in the new live interval.
2087 unsigned index = getInstructionIndex(MI);
2108 MachineInstrIndex index = getInstructionIndex(MI);
20882109 if (HasUse) {
20892110 LiveRange LR(getLoadIndex(index), getUseIndex(index),
2090 nI.getNextValue(0, 0, false, getVNInfoAllocator()));
2111 nI.getNextValue(MachineInstrIndex(), 0, false,
2112 getVNInfoAllocator()));
20912113 DEBUG(errs() << " +" << LR);
20922114 nI.addRange(LR);
20932115 vrm.addRestorePoint(NewVReg, MI);
20942116 }
20952117 if (HasDef) {
20962118 LiveRange LR(getDefIndex(index), getStoreIndex(index),
2097 nI.getNextValue(0, 0, false, getVNInfoAllocator()));
2119 nI.getNextValue(MachineInstrIndex(), 0, false,
2120 getVNInfoAllocator()));
20982121 DEBUG(errs() << " +" << LR);
20992122 nI.addRange(LR);
21002123 vrm.addSpillPoint(NewVReg, true, MI);
21572180 if (vrm.getPreSplitReg(li.reg)) {
21582181 vrm.setIsSplitFromReg(li.reg, 0);
21592182 // Unset the split kill marker on the last use.
2160 unsigned KillIdx = vrm.getKillPoint(li.reg);
2161 if (KillIdx) {
2183 MachineInstrIndex KillIdx = vrm.getKillPoint(li.reg);
2184 if (KillIdx != MachineInstrIndex()) {
21622185 MachineInstr *KillMI = getInstructionFromIndex(KillIdx);
21632186 assert(KillMI && "Last use disappeared?");
21642187 int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true);
22862309 while (Id != -1) {
22872310 std::vector &spills = SpillIdxes[Id];
22882311 for (unsigned i = 0, e = spills.size(); i != e; ++i) {
2289 int index = spills[i].index;
2312 MachineInstrIndex index = spills[i].index;
22902313 unsigned VReg = spills[i].vreg;
22912314 LiveInterval &nI = getOrCreateInterval(VReg);
22922315 bool isReMat = vrm.isReMaterialized(VReg);
23242347 if (FoundUse) {
23252348 // Also folded uses, do not issue a load.
23262349 eraseRestoreInfo(Id, index, VReg, RestoreMBBs, RestoreIdxes);
2327 nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
2350 nI.removeRange(getLoadIndex(index), getUseIndex(index).nextSlot());
23282351 }
23292352 nI.removeRange(getDefIndex(index), getStoreIndex(index));
23302353 }
23492372 while (Id != -1) {
23502373 std::vector &restores = RestoreIdxes[Id];
23512374 for (unsigned i = 0, e = restores.size(); i != e; ++i) {
2352 int index = restores[i].index;
2353 if (index == -1)
2375 MachineInstrIndex index = restores[i].index;
2376 if (index == MachineInstrIndex())
23542377 continue;
23552378 unsigned VReg = restores[i].vreg;
23562379 LiveInterval &nI = getOrCreateInterval(VReg);
24052428 // If folding is not possible / failed, then tell the spiller to issue a
24062429 // load / rematerialization for us.
24072430 if (Folded)
2408 nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
2431 nI.removeRange(getLoadIndex(index), getUseIndex(index).nextSlot());
24092432 else
24102433 vrm.addRestorePoint(VReg, MI);
24112434 }
24212444 LI->weight /= InstrSlots::NUM * getApproximateInstructionCount(*LI);
24222445 if (!AddedKill.count(LI)) {
24232446 LiveRange *LR = &LI->ranges[LI->ranges.size()-1];
2424 unsigned LastUseIdx = getBaseIndex(LR->end);
2447 MachineInstrIndex LastUseIdx = getBaseIndex(LR->end);
24252448 MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
24262449 int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false);
24272450 assert(UseIdx != -1);
24722495 E = mri_->reg_end(); I != E; ++I) {
24732496 MachineOperand &O = I.getOperand();
24742497 MachineInstr *MI = O.getParent();
2475 unsigned Index = getInstructionIndex(MI);
2498 MachineInstrIndex Index = getInstructionIndex(MI);
24762499 if (pli.liveAt(Index))
24772500 ++NumConflicts;
24782501 }
25032526 if (SeenMIs.count(MI))
25042527 continue;
25052528 SeenMIs.insert(MI);
2506 unsigned Index = getInstructionIndex(MI);
2529 MachineInstrIndex Index = getInstructionIndex(MI);
25072530 if (pli.liveAt(Index)) {
25082531 vrm.addEmergencySpill(SpillReg, MI);
2509 unsigned StartIdx = getLoadIndex(Index);
2510 unsigned EndIdx = getStoreIndex(Index)+1;
2532 MachineInstrIndex StartIdx = getLoadIndex(Index);
2533 MachineInstrIndex EndIdx = getStoreIndex(Index).nextSlot();
25112534 if (pli.isInOneLiveRange(StartIdx, EndIdx)) {
25122535 pli.removeRange(StartIdx, EndIdx);
25132536 Cut = true;
25272550 continue;
25282551 LiveInterval &spli = getInterval(*AS);
25292552 if (spli.liveAt(Index))
2530 spli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
2553 spli.removeRange(getLoadIndex(Index), getStoreIndex(Index).nextSlot());
25312554 }
25322555 }
25332556 }
25382561 MachineInstr* startInst) {
25392562 LiveInterval& Interval = getOrCreateInterval(reg);
25402563 VNInfo* VN = Interval.getNextValue(
2541 getInstructionIndex(startInst) + InstrSlots::DEF,
2542 startInst, true, getVNInfoAllocator());
2564 MachineInstrIndex(getInstructionIndex(startInst), MachineInstrIndex::DEF),
2565 startInst, true, getVNInfoAllocator());
25432566 VN->setHasPHIKill(true);
2544 VN->kills.push_back(
2545 VNInfo::KillInfo(terminatorGaps[startInst->getParent()], true));
2546 LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF,
2547 getMBBEndIdx(startInst->getParent()) + 1, VN);
2567 VN->kills.push_back(terminatorGaps[startInst->getParent()]);
2568 LiveRange LR(
2569 MachineInstrIndex(getInstructionIndex(startInst), MachineInstrIndex::DEF),
2570 getMBBEndIdx(startInst->getParent()).nextSlot(), VN);
25482571 Interval.addRange(LR);
25492572
25502573 return LR;
6767 MachineBasicBlock *BarrierMBB;
6868
6969 // Barrier - Current barrier index.
70 unsigned BarrierIdx;
70 MachineInstrIndex BarrierIdx;
7171
7272 // CurrLI - Current live interval being split.
7373 LiveInterval *CurrLI;
8282 DenseMap IntervalSSMap;
8383
8484 // Def2SpillMap - A map from a def instruction index to spill index.
85 DenseMap<unsigned, unsigned> Def2SpillMap;
85 DenseMap<MachineInstrIndex, MachineInstrIndex> Def2SpillMap;
8686
8787 public:
8888 static char ID;
128128 private:
129129 MachineBasicBlock::iterator
130130 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
131 unsigned&);
131 MachineInstrIndex&);
132132
133133 MachineBasicBlock::iterator
134134 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
135 SmallPtrSet&, unsigned&);
135 SmallPtrSet&, MachineInstrIndex&);
136136
137137 MachineBasicBlock::iterator
138 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
139 SmallPtrSet&, unsigned&);
138 findRestorePoint(MachineBasicBlock*, MachineInstr*, MachineInstrIndex,
139 SmallPtrSet&, MachineInstrIndex&);
140140
141141 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
142142
143 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
144 unsigned&, int&) const;
145
146 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
143 bool IsAvailableInStack(MachineBasicBlock*, unsigned,
144 MachineInstrIndex, MachineInstrIndex,
145 MachineInstrIndex&, int&) const;
146
147 void UpdateSpillSlotInterval(VNInfo*, MachineInstrIndex, MachineInstrIndex);
147148
148149 bool SplitRegLiveInterval(LiveInterval*);
149150
155156 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
156157 MachineInstr* DefMI,
157158 MachineBasicBlock::iterator RestorePt,
158 unsigned RestoreIdx,
159 MachineInstrIndex RestoreIdx,
159160 SmallPtrSet& RefsInMBB);
160161 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
161162 MachineInstr* DefMI,
207208 /// instruction index map. If there isn't one, return end().
208209 MachineBasicBlock::iterator
209210 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
210 unsigned &SpotIndex) {
211 MachineInstrIndex &SpotIndex) {
211212 MachineBasicBlock::iterator MII = MI;
212213 if (++MII != MBB->end()) {
213 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
214 if (Index) {
214 MachineInstrIndex Index =
215 LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
216 if (Index != MachineInstrIndex()) {
215217 SpotIndex = Index;
216218 return MII;
217219 }
227229 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
228230 MachineInstr *DefMI,
229231 SmallPtrSet &RefsInMBB,
230 unsigned &SpillIndex) {
232 MachineInstrIndex &SpillIndex) {
231233 MachineBasicBlock::iterator Pt = MBB->begin();
232234
233235 MachineBasicBlock::iterator MII = MI;
240242 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
241243
242244 while (MII != EndPt && !RefsInMBB.count(MII)) {
243 unsigned Index = LIs->getInstructionIndex(MII);
245 MachineInstrIndex Index = LIs->getInstructionIndex(MII);
244246
245247 // We can't insert the spill between the barrier (a call), and its
246248 // corresponding call frame setup.
273275 /// found.
274276 MachineBasicBlock::iterator
275277 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
276 unsigned LastIdx,
278 MachineInstrIndex LastIdx,
277279 SmallPtrSet &RefsInMBB,
278 unsigned &RestoreIndex) {
280 MachineInstrIndex &RestoreIndex) {
279281 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
280282 // begin index accordingly.
281283 MachineBasicBlock::iterator Pt = MBB->end();
296298 // FIXME: Limit the number of instructions to examine to reduce
297299 // compile time?
298300 while (MII != EndPt) {
299 unsigned Index = LIs->getInstructionIndex(MII);
301 MachineInstrIndex Index = LIs->getInstructionIndex(MII);
300302 if (Index > LastIdx)
301303 break;
302 unsigned Gap = LIs->findGapBeforeInstr(Index);
304 MachineInstrIndex Gap = LIs->findGapBeforeInstr(Index);
303305
304306 // We can't insert a restore between the barrier (a call) and its
305307 // corresponding call frame teardown.
308310 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
309311 ++MII;
310312 } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
311 } else if (Gap) {
313 } else if (Gap != MachineInstrIndex()) {
312314 Pt = MII;
313315 RestoreIndex = Gap;
314316 }
341343 if (CurrSLI->hasAtLeastOneValue())
342344 CurrSValNo = CurrSLI->getValNumInfo(0);
343345 else
344 CurrSValNo = CurrSLI->getNextValue(0, 0, false, LSs->getVNInfoAllocator());
346 CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
347 LSs->getVNInfoAllocator());
345348 return SS;
346349 }
347350
349352 /// slot at the specified index.
350353 bool
351354 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
352 unsigned Reg, unsigned DefIndex,
353 unsigned RestoreIndex, unsigned &SpillIndex,
355 unsigned Reg, MachineInstrIndex DefIndex,
356 MachineInstrIndex RestoreIndex,
357 MachineInstrIndex &SpillIndex,
354358 int& SS) const {
355359 if (!DefMBB)
356360 return false;
358362 DenseMap::iterator I = IntervalSSMap.find(Reg);
359363 if (I == IntervalSSMap.end())
360364 return false;
361 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
365 DenseMap<MachineInstrIndex, MachineInstrIndex>::iterator
366 II = Def2SpillMap.find(DefIndex);
362367 if (II == Def2SpillMap.end())
363368 return false;
364369
378383 /// interval being split, and the spill and restore indicies, update the live
379384 /// interval of the spill stack slot.
380385 void
381 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
382 unsigned RestoreIndex) {
386 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, MachineInstrIndex SpillIndex,
387 MachineInstrIndex RestoreIndex) {
383388 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
384389 "Expect restore in the barrier mbb");
385390
392397 }
393398
394399 SmallPtrSet Processed;
395 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
396 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
400 MachineInstrIndex EndIdx = LIs->getMBBEndIdx(MBB);
401 LiveRange SLR(SpillIndex, LIs->getNextSlot(EndIdx), CurrSValNo);
397402 CurrSLI->addRange(SLR);
398403 Processed.insert(MBB);
399404
412417 WorkList.pop_back();
413418 if (Processed.count(MBB))
414419 continue;
415 unsigned Idx = LIs->getMBBStartIdx(MBB);
420 MachineInstrIndex Idx = LIs->getMBBStartIdx(MBB);
416421 LR = CurrLI->getLiveRangeContaining(Idx);
417422 if (LR && LR->valno == ValNo) {
418423 EndIdx = LIs->getMBBEndIdx(MBB);
422427 CurrSLI->addRange(SLR);
423428 } else if (LR->end > EndIdx) {
424429 // Live range extends beyond end of mbb, process successors.
425 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
430 LiveRange SLR(Idx, LIs->getNextIndex(EndIdx), CurrSValNo);
426431 CurrSLI->addRange(SLR);
427432 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
428433 SE = MBB->succ_end(); SI != SE; ++SI)
485490 }
486491
487492 // Once we've found it, extend its VNInfo to our instruction.
488 unsigned DefIndex = LIs->getInstructionIndex(Walker);
493 MachineInstrIndex DefIndex = LIs->getInstructionIndex(Walker);
489494 DefIndex = LiveIntervals::getDefIndex(DefIndex);
490 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
495 MachineInstrIndex EndIndex = LIs->getMBBEndIdx(MBB);
491496
492497 RetVNI = NewVNs[Walker];
493 LI->addRange(LiveRange(DefIndex, EndIndex+1, RetVNI));
498 LI->addRange(LiveRange(DefIndex, LIs->getNextSlot(EndIndex), RetVNI));
494499 } else if (!ContainsDefs && ContainsUses) {
495500 SmallPtrSet& BlockUses = Uses[MBB];
496501
522527 IsTopLevel, IsIntraBlock);
523528 }
524529
525 unsigned UseIndex = LIs->getInstructionIndex(Walker);
530 MachineInstrIndex UseIndex = LIs->getInstructionIndex(Walker);
526531 UseIndex = LiveIntervals::getUseIndex(UseIndex);
527 unsigned EndIndex = 0;
532 MachineInstrIndex EndIndex;
528533 if (IsIntraBlock) {
529534 EndIndex = LIs->getInstructionIndex(UseI);
530535 EndIndex = LiveIntervals::getUseIndex(EndIndex);
536541 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
537542 NewVNs, LiveOut, Phis, false, true);
538543
539 LI->addRange(LiveRange(UseIndex, EndIndex+1, RetVNI));
544 LI->addRange(LiveRange(UseIndex, LIs->getNextSlot(EndIndex), RetVNI));
540545
541546 // FIXME: Need to set kills properly for inter-block stuff.
542 if (LI->isKill(RetVNI, UseIndex)) LI->removeKill(RetVNI, UseIndex);
547 if (RetVNI->isKill(UseIndex)) RetVNI->removeKill(UseIndex);
543548 if (IsIntraBlock)
544 LI->addKill(RetVNI, EndIndex, false);
549 RetVNI->addKill(EndIndex);
545550 } else if (ContainsDefs && ContainsUses) {
546551 SmallPtrSet& BlockDefs = Defs[MBB];
547552 SmallPtrSet& BlockUses = Uses[MBB];
582587 IsTopLevel, IsIntraBlock);
583588 }
584589
585 unsigned StartIndex = LIs->getInstructionIndex(Walker);
590 MachineInstrIndex StartIndex = LIs->getInstructionIndex(Walker);
586591 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
587592 LiveIntervals::getUseIndex(StartIndex);
588 unsigned EndIndex = 0;
593 MachineInstrIndex EndIndex;
589594 if (IsIntraBlock) {
590595 EndIndex = LIs->getInstructionIndex(UseI);
591596 EndIndex = LiveIntervals::getUseIndex(EndIndex);
598603 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
599604 NewVNs, LiveOut, Phis, false, true);
600605
601 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
602
603 if (foundUse && LI->isKill(RetVNI, StartIndex))
604 LI->removeKill(RetVNI, StartIndex);
606 LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
607
608 if (foundUse && RetVNI->isKill(StartIndex))
609 RetVNI->removeKill(StartIndex);
605610 if (IsIntraBlock) {
606 LI->addKill(RetVNI, EndIndex, false);
611 RetVNI->addKill(EndIndex);
607612 }
608613 }
609614
634639 // assume that we are not intrablock here.
635640 if (Phis.count(MBB)) return Phis[MBB];
636641
637 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
642 MachineInstrIndex StartIndex = LIs->getMBBStartIdx(MBB);
638643 VNInfo *RetVNI = Phis[MBB] =
639 LI->getNextValue(0, /*FIXME*/ 0, false, LIs->getVNInfoAllocator());
644 LI->getNextValue(MachineInstrIndex(), /*FIXME*/ 0, false,
645 LIs->getVNInfoAllocator());
640646
641647 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
642648
678684 for (DenseMap::iterator I =
679685 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
680686 I->second->setHasPHIKill(true);
681 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
682 if (!LiveInterval::isKill(I->second, KillIndex))
683 LI->addKill(I->second, KillIndex, false);
687 MachineInstrIndex KillIndex = LIs->getMBBEndIdx(I->first);
688 if (!I->second->isKill(KillIndex))
689 I->second->addKill(KillIndex);
684690 }
685691 }
686692
687 unsigned EndIndex = 0;
693 MachineInstrIndex EndIndex;
688694 if (IsIntraBlock) {
689695 EndIndex = LIs->getInstructionIndex(UseI);
690696 EndIndex = LiveIntervals::getUseIndex(EndIndex);
691697 } else
692698 EndIndex = LIs->getMBBEndIdx(MBB);
693 LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
699 LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
694700 if (IsIntraBlock)
695 LI->addKill(RetVNI, EndIndex, false);
701 RetVNI->addKill(EndIndex);
696702
697703 // Memoize results so we don't have to recompute them.
698704 if (!IsIntraBlock)
726732 DE = MRI->def_end(); DI != DE; ++DI) {
727733 Defs[(*DI).getParent()].insert(&*DI);
728734
729 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
735 MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
730736 DefIdx = LiveIntervals::getDefIndex(DefIdx);
731737
732738 assert(DI->getOpcode() != TargetInstrInfo::PHI &&
762768 // Add ranges for dead defs
763769 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
764770 DE = MRI->def_end(); DI != DE; ++DI) {
765 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
771 MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
766772 DefIdx = LiveIntervals::getDefIndex(DefIdx);
767773
768774 if (LI->liveAt(DefIdx)) continue;
769775
770776 VNInfo* DeadVN = NewVNs[&*DI];
771 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
772 LI->addKill(DeadVN, DefIdx, false);
777 LI->addRange(LiveRange(DefIdx, LIs->getNextSlot(DefIdx), DeadVN));
778 DeadVN->addKill(DefIdx);
773779 }
774780 }
775781
801807 // Locate two-address redefinitions
802808 for (VNInfo::KillSet::iterator KI = OldVN->kills.begin(),
803809 KE = OldVN->kills.end(); KI != KE; ++KI) {
804 assert(!KI->isPHIKill && "VN previously reported having no PHI kills.");
805 MachineInstr* MI = LIs->getInstructionFromIndex(KI->killIdx);
810 assert(!KI->isPHIIndex() &&
811 "VN previously reported having no PHI kills.");
812 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
806813 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
807814 if (DefIdx == ~0U) continue;
808815 if (MI->isRegTiedToUseOperand(DefIdx)) {
809816 VNInfo* NextVN =
810 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(KI->killIdx));
817 CurrLI->findDefinedVNInfoForRegInt(
818 LiveIntervals::getDefIndex(*KI));
811819 if (NextVN == OldVN) continue;
812820 Stack.push_back(NextVN);
813821 }
839847 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
840848 E = MRI->reg_end(); I != E; ++I) {
841849 MachineOperand& MO = I.getOperand();
842 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
850 MachineInstrIndex InstrIdx = LIs->getInstructionIndex(&*I);
843851
844852 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
845853 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
867875 bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
868876 MachineInstr* DefMI,
869877 MachineBasicBlock::iterator RestorePt,
870 unsigned RestoreIdx,
878 MachineInstrIndex RestoreIdx,
871879 SmallPtrSet& RefsInMBB) {
872880 MachineBasicBlock& MBB = *RestorePt->getParent();
873881
874882 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
875 unsigned KillIdx = 0;
883 MachineInstrIndex KillIdx;
876884 if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
877885 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
878886 else
885893 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
886894
887895 ReconstructLiveInterval(CurrLI);
888 unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt));
896 MachineInstrIndex RematIdx = LIs->getInstructionIndex(prior(RestorePt));
889897 RematIdx = LiveIntervals::getDefIndex(RematIdx);
890 RenumberValno(CurrLI->findDefinedVNInfo(RematIdx));
898 RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx));
891899
892900 ++NumSplits;
893901 ++NumRemats;
942950 if (CurrSLI->hasAtLeastOneValue())
943951 CurrSValNo = CurrSLI->getValNumInfo(0);
944952 else
945 CurrSValNo = CurrSLI->getNextValue(0, 0, false, LSs->getVNInfoAllocator());
953 CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
954 LSs->getVNInfoAllocator());
946955 }
947956
948957 return FMI;
10511060 }
10521061
10531062 // Find a point to restore the value after the barrier.
1054 unsigned RestoreIndex = 0;
1063 MachineInstrIndex RestoreIndex;
10551064 MachineBasicBlock::iterator RestorePt =
10561065 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
10571066 if (RestorePt == BarrierMBB->end())
10651074 // Add a spill either before the barrier or after the definition.
10661075 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
10671076 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1068 unsigned SpillIndex = 0;
1077 MachineInstrIndex SpillIndex;
10691078 MachineInstr *SpillMI = NULL;
10701079 int SS = -1;
10711080 if (!ValNo->isDefAccurate()) {
11371146 }
11381147
11391148 // Update spill stack slot live interval.
1140 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1149 UpdateSpillSlotInterval(ValNo, LIs->getNextSlot(LIs->getUseIndex(SpillIndex)),
11411150 LIs->getDefIndex(RestoreIndex));
11421151
11431152 ReconstructLiveInterval(CurrLI);
11441153
11451154 if (!FoldedRestore) {
1146 unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1155 MachineInstrIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
11471156 RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx);
1148 RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx));
1157 RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx));
11491158 }
11501159
11511160 ++NumSplits;
12311240 // reaching definition (VNInfo).
12321241 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
12331242 UE = MRI->use_end(); UI != UE; ++UI) {
1234 unsigned index = LIs->getInstructionIndex(&*UI);
1243 MachineInstrIndex index = LIs->getInstructionIndex(&*UI);
12351244 index = LiveIntervals::getUseIndex(index);
12361245
12371246 const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
13811390 if (LR->valno->hasPHIKill())
13821391 return false;
13831392
1384 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1393 MachineInstrIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
13851394 if (LR->end < MBBEnd)
13861395 return false;
13871396
175175
176176 /// processActiveIntervals - expire old intervals and move non-overlapping
177177 /// ones to the inactive list.
178 void processActiveIntervals(unsigned CurPoint);
178 void processActiveIntervals(MachineInstrIndex CurPoint);
179179
180180 /// processInactiveIntervals - expire old intervals and move overlapping
181181 /// ones to the active list.
182 void processInactiveIntervals(unsigned CurPoint);
182 void processInactiveIntervals(MachineInstrIndex CurPoint);
183183
184184 /// hasNextReloadInterval - Return the next liveinterval that's being
185185 /// defined by a reload from the same SS as the specified one.
365365 return Reg;
366366
367367 VNInfo *vni = cur.begin()->valno;
368 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
368 if ((vni->def == MachineInstrIndex()) ||
369 vni->isUnused() || !vni->isDefAccurate())
369370 return Reg;
370371 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
371372 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
502503 DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
503504
504505 if (!cur->empty()) {
505 processActiveIntervals(cur->beginNumber());
506 processInactiveIntervals(cur->beginNumber());
506 processActiveIntervals(cur->beginIndex());
507 processInactiveIntervals(cur->beginIndex());
507508
508509 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
509510 "Can only allocate virtual registers!");
584585
585586 /// processActiveIntervals - expire old intervals and move non-overlapping ones
586587 /// to the inactive list.
587 void RALinScan::processActiveIntervals(unsigned CurPoint)
588 void RALinScan::processActiveIntervals(MachineInstrIndex CurPoint)
588589 {
589590 DEBUG(errs() << "\tprocessing active intervals:\n");
590591
630631
631632 /// processInactiveIntervals - expire old intervals and move overlapping
632633 /// ones to the active list.
633 void RALinScan::processInactiveIntervals(unsigned CurPoint)
634 void RALinScan::processInactiveIntervals(MachineInstrIndex CurPoint)
634635 {
635636 DEBUG(errs() << "\tprocessing inactive intervals:\n");
636637
711712 return IP.end();
712713 }
713714
714 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
715 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, MachineInstrIndex Point){
715716 for (unsigned i = 0, e = V.size(); i != e; ++i) {
716717 RALinScan::IntervalPtr &IP = V[i];
717718 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
737738 if (SI.hasAtLeastOneValue())
738739 VNI = SI.getValNumInfo(0);
739740 else
740 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
741 VNI = SI.getNextValue(MachineInstrIndex(), 0, false,
742 ls_->getVNInfoAllocator());
741743
742744 LiveInterval &RI = li_->getInterval(cur->reg);
743745 // FIXME: This may be overly conservative.
879881 namespace {
880882 struct LISorter {
881883 bool operator()(LiveInterval* A, LiveInterval* B) {
882 return A->beginNumber() < B->beginNumber();
884 return A->beginIndex() < B->beginIndex();
883885 }
884886 };
885887 }
904906 backUpRegUses();
905907
906908 std::vector > SpillWeightsToAdd;
907 unsigned StartPosition = cur->beginNumber();
909 MachineInstrIndex StartPosition = cur->beginIndex();
908910 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
909911
910912 // If start of this live interval is defined by a move instruction and its
914916 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
915917 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
916918 VNInfo *vni = cur->begin()->valno;
917 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
919 if ((vni->def != MachineInstrIndex()) && !vni->isUnused() &&
920 vni->isDefAccurate()) {
918921 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
919922 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
920923 if (CopyMI &&
976979 // Okay, this reg is on the fixed list. Check to see if we actually
977980 // conflict.
978981 LiveInterval *I = IP.first;
979 if (I->endNumber() > StartPosition) {
982 if (I->endIndex() > StartPosition) {
980983 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
981984 IP.second = II;
982985 if (II != I->begin() && II->start > StartPosition)
10011004
10021005 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
10031006 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1004 I->endNumber() > StartPosition) {
1007 I->endIndex() > StartPosition) {
10051008 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
10061009 IP.second = II;
10071010 if (II != I->begin() && II->start > StartPosition)
11691172 LiveInterval *ReloadLi = added[i];
11701173 if (ReloadLi->weight == HUGE_VALF &&
11711174 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1172 unsigned ReloadIdx = ReloadLi->beginNumber();
1175 MachineInstrIndex ReloadIdx = ReloadLi->beginIndex();
11731176 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
11741177 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
11751178 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
11761179 // Last reload of same SS is in the same MBB. We want to try to
11771180 // allocate both reloads the same register and make sure the reg
11781181 // isn't clobbered in between if at all possible.
1179 assert(LastReload->beginNumber() < ReloadIdx);
1182 assert(LastReload->beginIndex() < ReloadIdx);
11801183 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
11811184 }
11821185 LastReloadMBB = ReloadMBB;
12251228 spillIs.pop_back();
12261229 DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
12271230 earliestStartInterval =
1228 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1231 (earliestStartInterval->beginIndex() < sli->beginIndex()) ?
12291232 earliestStartInterval : sli;
12301233
12311234 std::vector newIs;
12391242 spilled.insert(sli->reg);
12401243 }
12411244
1242 unsigned earliestStart = earliestStartInterval->beginNumber();
1245 MachineInstrIndex earliestStart = earliestStartInterval->beginIndex();
12431246
12441247 DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
12451248
12491252 while (!handled_.empty()) {
12501253 LiveInterval* i = handled_.back();
12511254 // If this interval starts before t we are done.
1252 if (i->beginNumber() < earliestStart)
1255 if (i->beginIndex() < earliestStart)
12531256 break;
12541257 DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
12551258 handled_.pop_back();
13001303 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
13011304 LiveInterval *HI = handled_[i];
13021305 if (!HI->expiredAt(earliestStart) &&
1303 HI->expiredAt(cur->beginNumber())) {
1306 HI->expiredAt(cur->beginIndex())) {
13041307 DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
13051308 active_.push_back(std::make_pair(HI, HI->begin()));
13061309 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
13201323 LiveInterval *ReloadLi = added[i];
13211324 if (ReloadLi->weight == HUGE_VALF &&
13221325 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1323 unsigned ReloadIdx = ReloadLi->beginNumber();
1326 MachineInstrIndex ReloadIdx = ReloadLi->beginIndex();
13241327 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
13251328 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
13261329 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
13271330 // Last reload of same SS is in the same MBB. We want to try to
13281331 // allocate both reloads the same register and make sure the reg
13291332 // isn't clobbered in between if at all possible.
1330 assert(LastReload->beginNumber() < ReloadIdx);
1333 assert(LastReload->beginIndex() < ReloadIdx);
13311334 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
13321335 }
13331336 LastReloadMBB = ReloadMBB;
682682 if (stackInterval.getNumValNums() != 0)
683683 vni = stackInterval.getValNumInfo(0);
684684 else
685 vni = stackInterval.getNextValue(0, 0, false, lss->getVNInfoAllocator());
685 vni = stackInterval.getNextValue(
686 MachineInstrIndex(), 0, false, lss->getVNInfoAllocator());
686687
687688 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
688689 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
107107 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
108108 LiveInterval &IntB,
109109 MachineInstr *CopyMI) {
110 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
110 MachineInstrIndex CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
111111
112112 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
113113 // the example above.
122122 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
123123
124124 // AValNo is the value number in A that defines the copy, A3 in the example.
125 unsigned CopyUseIdx = li_->getUseIndex(CopyIdx);
125 MachineInstrIndex CopyUseIdx = li_->getUseIndex(CopyIdx);
126126 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
127127 assert(ALR != IntA.end() && "Live range not found!");
128128 VNInfo *AValNo = ALR->valno;
159159 if (SrcReg != IntB.reg) return false;
160160
161161 // Get the LiveRange in IntB that this value number starts with.
162 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
162 LiveInterval::iterator ValLR =
163 IntB.FindLiveRangeContaining(li_->getPrevSlot(AValNo->def));
163164 assert(ValLR != IntB.end() && "Live range not found!");
164165
165166 // Make sure that the end of the live range is inside the same block as
166167 // CopyMI.
167 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
168 MachineInstr *ValLREndInst =
169 li_->getInstructionFromIndex(li_->getPrevSlot(ValLR->end));
168170 if (!ValLREndInst ||
169171 ValLREndInst->getParent() != CopyMI->getParent()) return false;
170172
193195 IntB.print(errs(), tri_);
194196 });
195197
196 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
198 MachineInstrIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
197199 // We are about to delete CopyMI, so need to remove it as the 'instruction
198200 // that defines this value #'. Update the the valnum with the new defining
199201 // instruction #.
232234 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
233235 if (UIdx != -1) {
234236 ValLREndInst->getOperand(UIdx).setIsKill(false);
235 IntB.removeKill(ValLR->valno, FillerStart);
237 ValLR->valno->removeKill(FillerStart);
236238 }
237239
238240 // If the copy instruction was killing the destination register before the
296298 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
297299 LiveInterval &IntB,
298300 MachineInstr *CopyMI) {
299 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
301 MachineInstrIndex CopyIdx =
302 li_->getDefIndex(li_->getInstructionIndex(CopyMI));
300303
301304 // FIXME: For now, only eliminate the copy by commuting its def when the
302305 // source register is a virtual register. We want to guard against cases
318321 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
319322
320323 // AValNo is the value number in A that defines the copy, A3 in the example.
321 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
324 LiveInterval::iterator ALR =
325 IntA.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
326
322327 assert(ALR != IntA.end() && "Live range not found!");
323328 VNInfo *AValNo = ALR->valno;
324329 // If other defs can reach uses of this def, then it's not safe to perform
363368 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
364369 UE = mri_->use_end(); UI != UE; ++UI) {
365370 MachineInstr *UseMI = &*UI;
366 unsigned UseIdx = li_->getInstructionIndex(UseMI);
371 MachineInstrIndex UseIdx = li_->getInstructionIndex(UseMI);
367372 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
368373 if (ULR == IntA.end())
369374 continue;
388393 bool BHasPHIKill = BValNo->hasPHIKill();
389394 SmallVector BDeadValNos;
390395 VNInfo::KillSet BKills;
391 std::map<unsigned, unsigned> BExtend;
396 std::map<MachineInstrIndex, MachineInstrIndex> BExtend;
392397
393398 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
394399 // A = or A, B
415420 ++UI;
416421 if (JoinedCopies.count(UseMI))
417422 continue;
418 unsigned UseIdx = li_->getInstructionIndex(UseMI);
423 MachineInstrIndex UseIdx = li_->getInstructionIndex(UseMI);
419424 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
420425 if (ULR == IntA.end() || ULR->valno != AValNo)
421426 continue;
426431 if (Extended)
427432 UseMO.setIsKill(false);
428433 else
429 BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
434 BKills.push_back(li_->getNextSlot(li_->getUseIndex(UseIdx)));
430435 }
431436 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
432437 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
435440 // This copy will become a noop. If it's defining a new val#,
436441 // remove that val# as well. However this live range is being
437442 // extended to the end of the existing live range defined by the copy.
438 unsigned DefIdx = li_->getDefIndex(UseIdx);
443 MachineInstrIndex DefIdx = li_->getDefIndex(UseIdx);
439444 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
440445 BHasPHIKill |= DLR->valno->hasPHIKill();
441446 assert(DLR->valno->def == DefIdx);
475480 ValNo->def = AValNo->def;
476481 ValNo->setCopy(0);
477482 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
478 unsigned Kill = ValNo->kills[j].killIdx;
479 if (Kill != BLR->end)
480 BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
483 if (ValNo->kills[j] != BLR->end)
484 BKills.push_back(ValNo->kills[j]);
481485 }
482486 ValNo->kills.clear();
483487 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
484488 AI != AE; ++AI) {
485489 if (AI->valno != AValNo) continue;
486 unsigned End = AI->end;
487 std::map::iterator EI = BExtend.find(End);
490 MachineInstrIndex End = AI->end;
491 std::map::iterator
492 EI = BExtend.find(End);
488493 if (EI != BExtend.end())
489494 End = EI->second;
490495 IntB.addRange(LiveRange(AI->start, End, ValNo));
537542 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
538543 /// from a physical register live interval as well as from the live intervals
539544 /// of its sub-registers.
540 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
545 static void removeRange(LiveInterval &li,
546 MachineInstrIndex Start, MachineInstrIndex End,
541547 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
542548 li.removeRange(Start, End, true);
543549 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
545551 if (!li_->hasInterval(*SR))
546552 continue;
547553 LiveInterval &sli = li_->getInterval(*SR);
548 unsigned RemoveEnd = Start;
554 MachineInstrIndex RemoveEnd = Start;
549555 while (RemoveEnd != End) {
550556 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
551557 if (LR == sli.end())
562568 /// as the copy instruction, trim the live interval to the last use and return
563569 /// true.
564570 bool
565 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
571 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(MachineInstrIndex CopyIdx,
566572 MachineBasicBlock *CopyMBB,
567573 LiveInterval &li,
568574 const LiveRange *LR) {
569 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
570 unsigned LastUseIdx;
571 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
572 LastUseIdx);
575 MachineInstrIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
576 MachineInstrIndex LastUseIdx;
577 MachineOperand *LastUse =
578 lastRegisterUse(LR->start, li_->getPrevSlot(CopyIdx), li.reg, LastUseIdx);
573579 if (LastUse) {
574580 MachineInstr *LastUseMI = LastUse->getParent();
575581 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
589595 // of last use.
590596 LastUse->setIsKill();
591597 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
592 li.addKill(LR->valno, LastUseIdx+1, false);
598 LR->valno->addKill(li_->getNextSlot(LastUseIdx));
593599 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
594600 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
595601 DstReg == li.reg) {
602608
603609 // Is it livein?
604610 if (LR->start <= MBBStart && LR->end > MBBStart) {
605 if (LR->start == 0) {
611 if (LR->start == MachineInstrIndex()) {
606612 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
607613 // Live-in to the function but dead. Remove it from entry live-in set.
608614 mf_->begin()->removeLiveIn(li.reg);
619625 unsigned DstReg,
620626 unsigned DstSubIdx,
621627 MachineInstr *CopyMI) {
622 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
628 MachineInstrIndex CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
623629 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
624630 assert(SrcLR != SrcInt.end() && "Live range not found!");
625631 VNInfo *ValNo = SrcLR->valno;
653659 return false;
654660 }
655661
656 unsigned DefIdx = li_->getDefIndex(CopyIdx);
662 MachineInstrIndex DefIdx = li_->getDefIndex(CopyIdx);
657663 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
658664 DLR->valno->setCopy(0);
659665 // Don't forget to update sub-register intervals.
686692 // should mark it dead:
687693 if (DefMI->getParent() == MBB) {
688694 DefMI->addRegisterDead(SrcInt.reg, tri_);
689 SrcLR->end = SrcLR->start + 1;
695 SrcLR->end = li_->getNextSlot(SrcLR->start);
690696 }
691697 }
692698
725731 return false;
726732
727733 LiveInterval &LI = li_->getInterval(DstReg);
728 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
734 MachineInstrIndex DefIdx = li_->getInstructionIndex(CopyMI);
729735 LiveInterval::const_iterator DstLR =
730736 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
731737 if (DstLR == LI.end())
732738 return false;
733 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
739 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIIndex())
734740 return true;
735741 return false;
736742 }
806812 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
807813 allocatableRegs_[CopyDstReg])) {