llvm.org GIT mirror llvm / 864e2ef
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
26 changed file(s) with 1 addition(s) and 211 deletion(s). Raw diff Collapse all Expand all
462462 bool UnfoldLoad, bool UnfoldStore,
463463 unsigned *LoadRegIndex = 0) const {
464464 return 0;
465 }
466
467 /// BlockHasNoFallThrough - Return true if the specified block does not
468 /// fall-through into its successor block. This is primarily used when a
469 /// branch is unanalyzable. It is useful for things like unconditional
470 /// indirect branches (jump tables).
471 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
472 return false;
473465 }
474466
475467 /// ReverseBranchCondition - Reverses the branch condition of the specified
11391139 // falls through into MBB and we can't understand the prior block's branch
11401140 // condition.
11411141 if (MBB->empty()) {
1142 bool PredHasNoFallThrough = TII->BlockHasNoFallThrough(PrevBB);
1142 bool PredHasNoFallThrough = !PrevBB.canFallThrough();
11431143 if (PredHasNoFallThrough || !PriorUnAnalyzable ||
11441144 !PrevBB.isSuccessor(MBB)) {
11451145 // If the prior block falls through into us, turn it into an
373373 // Block does not fall through.
374374 if (MBB->empty()) {
375375 report("MBB doesn't fall through but is empty!", MBB);
376 }
377 }
378 if (TII->BlockHasNoFallThrough(*MBB)) {
379 if (MBB->empty()) {
380 report("TargetInstrInfo says the block has no fall through, but the "
381 "block is empty!", MBB);
382 } else if (!MBB->back().getDesc().isBarrier()) {
383 report("TargetInstrInfo says the block has no fall through, but the "
384 "block does not end in a barrier!", MBB);
385376 }
386377 }
387378 } else {
189189 // if there is not such an opcode.
190190 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
191191
192 // Return true if the block does not fall through.
193 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
194
195192 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
196193 MachineBasicBlock::iterator &MBBI,
197194 LiveVariables *LV) const;
5959 return 0;
6060 }
6161
62 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
63 if (MBB.empty()) return false;
64
65 switch (MBB.back().getOpcode()) {
66 case ARM::BX_RET: // Return.
67 case ARM::LDM_RET:
68 case ARM::B:
69 case ARM::BRIND:
70 case ARM::BR_JTr: // Jumptable branch.
71 case ARM::BR_JTm: // Jumptable branch through mem.
72 case ARM::BR_JTadd: // Jumptable branch add to pc.
73 return true;
74 default:
75 break;
76 }
77
78 return false;
79 }
80
8162 void ARMInstrInfo::
8263 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
8364 unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
3131 // if there is not such an opcode.
3232 unsigned getUnindexedOpcode(unsigned Opc) const;
3333
34 // Return true if the block does not fall through.
35 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
36
3734 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
3835 unsigned DestReg, unsigned SubIdx,
3936 const MachineInstr *Orig,
2929
3030 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
3131 return 0;
32 }
33
34 bool
35 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
36 if (MBB.empty()) return false;
37
38 switch (MBB.back().getOpcode()) {
39 case ARM::tBX_RET:
40 case ARM::tBX_RET_vararg:
41 case ARM::tPOP_RET:
42 case ARM::tB:
43 case ARM::tBRIND:
44 case ARM::tBR_JTr:
45 return true;
46 default:
47 break;
48 }
49
50 return false;
5132 }
5233
5334 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
2929 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3030 // if there is not such an opcode.
3131 unsigned getUnindexedOpcode(unsigned Opc) const;
32
33 // Return true if the block does not fall through.
34 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
3532
3633 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3734 /// such, whenever a client has an instance of instruction info, it should
3232 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
3333 // FIXME
3434 return 0;
35 }
36
37 bool
38 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
39 if (MBB.empty()) return false;
40
41 switch (MBB.back().getOpcode()) {
42 case ARM::t2LDM_RET:
43 case ARM::t2B: // Uncond branch.
44 case ARM::t2BR_JT: // Jumptable branch.
45 case ARM::t2TBB: // Table branch byte.
46 case ARM::t2TBH: // Table branch halfword.
47 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
48 case ARM::tBX_RET:
49 case ARM::tBX_RET_vararg:
50 case ARM::tPOP_RET:
51 case ARM::tB:
52 case ARM::tBRIND:
53 return true;
54 default:
55 break;
56 }
57
58 return false;
5935 }
6036
6137 bool
3030 // if there is not such an opcode.
3131 unsigned getUnindexedOpcode(unsigned Opc) const;
3232
33 // Return true if the block does not fall through.
34 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
35
3633 bool copyRegToReg(MachineBasicBlock &MBB,
3734 MachineBasicBlock::iterator I,
3835 unsigned DestReg, unsigned SrcReg,
391391 .addReg(Alpha::R31);
392392 }
393393
394 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
395 if (MBB.empty()) return false;
396
397 switch (MBB.back().getOpcode()) {
398 case Alpha::RETDAG: // Return.
399 case Alpha::RETDAGp:
400 case Alpha::BR: // Uncond branch.
401 case Alpha::JMP: // Indirect branch.
402 return true;
403 default: return false;
404 }
405 }
406394 bool AlphaInstrInfo::
407395 ReverseBranchCondition(SmallVectorImpl &Cond) const {
408396 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
7777 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
7878 void insertNoop(MachineBasicBlock &MBB,
7979 MachineBasicBlock::iterator MI) const;
80 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
8180 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
8281
8382 /// getGlobalBaseReg - Return a virtual register initialized with the
579579 }
580580 }
581581
582 bool
583 SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
584 return (!MBB.empty() && isUncondBranch(&MBB.back()));
585 }
586582 //! Reverses a branch's condition, returning false on success.
587583 bool
588584 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl &Cond)
7878 bool canFoldMemoryOperand(const MachineInstr *MI,
7979 const SmallVectorImpl &Ops) const;
8080
81 //! Return true if the specified block does not fall through
82 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
83
8481 //! Reverses a branch's condition, returning false on success.
8582 virtual
8683 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
216216
217217 Cond[0].setImm(CC);
218218 return false;
219 }
220
221 bool MSP430InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB)const{
222 if (MBB.empty()) return false;
223
224 switch (MBB.back().getOpcode()) {
225 case MSP430::RET: // Return.
226 case MSP430::JMP: // Uncond branch.
227 return true;
228 default: return false;
229 }
230219 }
231220
232221 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
6060
6161 // Branch folding goodness
6262 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
63 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
6463 bool isUnpredicatedTerminator(const MachineInstr *MI) const;
6564 bool AnalyzeBranch(MachineBasicBlock &MBB,
6665 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
589589 return 2;
590590 }
591591
592 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
593 /// fall-through into its successor block.
594 bool MipsInstrInfo::
595 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
596 {
597 if (MBB.empty()) return false;
598
599 switch (MBB.back().getOpcode()) {
600 case Mips::RET: // Return.
601 case Mips::JR: // Indirect branch.
602 case Mips::J: // Uncond branch.
603 return true;
604 default: return false;
605 }
606 }
607
608592 /// ReverseBranchCondition - Return the inverse opcode of the
609593 /// specified Branch instruction.
610594 bool MipsInstrInfo::
231231 return 0;
232232 }
233233
234 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
235234 virtual
236235 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
237236
739739 }
740740
741741
742 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
743 if (MBB.empty()) return false;
744
745 switch (MBB.back().getOpcode()) {
746 case PPC::BLR: // Return.
747 case PPC::B: // Uncond branch.
748 case PPC::BCTR: // Indirect branch.
749 return true;
750 default: return false;
751 }
752 }
753
754742 bool PPCInstrInfo::
755743 ReverseBranchCondition(SmallVectorImpl &Cond) const {
756744 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
142142 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
143143 const SmallVectorImpl &Ops) const;
144144
145 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
146145 virtual
147146 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
148147
401401 return false;
402402 }
403403
404 bool SystemZInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB)const{
405 if (MBB.empty()) return false;
406
407 switch (MBB.back().getOpcode()) {
408 case SystemZ::RET: // Return.
409 case SystemZ::JMP: // Uncond branch.
410 case SystemZ::JMPr: // Indirect branch.
411 return true;
412 default: return false;
413 }
414 }
415
416404 bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
417405 const TargetInstrDesc &TID = MI->getDesc();
418406 if (!TID.isTerminator()) return false;
8888 const std::vector &CSI) const;
8989
9090 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
91 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
9291 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
9392 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
9493 MachineBasicBlock *&TBB,
27182718 return I->second.first;
27192719 }
27202720
2721 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2722 if (MBB.empty()) return false;
2723
2724 switch (MBB.back().getOpcode()) {
2725 case X86::TCRETURNri:
2726 case X86::TCRETURNdi:
2727 case X86::RET: // Return.
2728 case X86::RETI:
2729 case X86::TAILJMPd:
2730 case X86::TAILJMPr:
2731 case X86::TAILJMPm:
2732 case X86::JMP: // Uncond branch.
2733 case X86::JMP32r: // Indirect branch.
2734 case X86::JMP64r: // Indirect branch (64-bit).
2735 case X86::JMP32m: // Indirect branch through mem.
2736 case X86::JMP64m: // Indirect branch through mem (64-bit).
2737 return true;
2738 default: return false;
2739 }
2740 }
2741
27422721 bool X86InstrInfo::
27432722 ReverseBranchCondition(SmallVectorImpl &Cond) const {
27442723 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
599599 bool UnfoldLoad, bool UnfoldStore,
600600 unsigned *LoadRegIndex = 0) const;
601601
602 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
603602 virtual
604603 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
605604
452452 return true;
453453 }
454454
455 /// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
456 /// fall-through into its successor block.
457 bool XCoreInstrInfo::
458 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
459 {
460 if (MBB.empty()) return false;
461
462 switch (MBB.back().getOpcode()) {
463 case XCore::RETSP_u6: // Return.
464 case XCore::RETSP_lu6:
465 case XCore::BAU_1r: // Indirect branch.
466 case XCore::BRFU_u6: // Uncond branch.
467 case XCore::BRFU_lu6:
468 case XCore::BRBU_u6:
469 case XCore::BRBU_lu6:
470 return true;
471 default: return false;
472 }
473 }
474
475455 /// ReverseBranchCondition - Return the inverse opcode of the
476456 /// specified Branch instruction.
477457 bool XCoreInstrInfo::
8686 MachineBasicBlock::iterator MI,
8787 const std::vector &CSI) const;
8888
89 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
90
9189 virtual bool ReverseBranchCondition(
9290 SmallVectorImpl &Cond) const;
9391 };