llvm.org GIT mirror llvm / 8634b0e
'svn add' the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190929 91177308-0d34-0410-b5e6-96231b3b80d8 Joey Gouly 6 years ago
5 changed file(s) with 92 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
1 @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
2 crc32b r0, r1, r2
3 crc32h r0, r1, r2
4 crc32w r0, r1, r2
5
6 @ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
7 @ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
8 @ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
9 @ CHECK-V7: error: instruction requires: armv8
10 @ CHECK-V7: error: instruction requires: armv8
11 @ CHECK-V7: error: instruction requires: armv8
12
13 crc32cb r0, r1, r2
14 crc32ch r0, r1, r2
15 crc32cw r0, r1, r2
16
17 @ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
18 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
19 @ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
20 @ CHECK-V7: error: instruction requires: armv8
21 @ CHECK-V7: error: instruction requires: armv8
22 @ CHECK-V7: error: instruction requires: armv8
0 @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
1 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
2 crc32b r0, r1, r2
3 crc32h r0, r1, r2
4 crc32w r0, r1, r2
5
6 @ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
7 @ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
8 @ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
9 @ CHECK-V7: error: instruction requires: armv8
10 @ CHECK-V7: error: instruction requires: armv8
11 @ CHECK-V7: error: instruction requires: armv8
12
13 crc32cb r0, r1, r2
14 crc32ch r0, r1, r2
15 crc32cw r0, r1, r2
16
17 @ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
18 @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
19 @ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
20 @ CHECK-V7: error: instruction requires: armv8
21 @ CHECK-V7: error: instruction requires: armv8
22 @ CHECK-V7: error: instruction requires: armv8
0 @ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s
1 @ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s
2
3 crc32cbeq r0, r1, r2
4 crc32bne r0, r1, r2
5 crc32chcc r0, r1, r2
6 crc32hpl r0, r1, r2
7 crc32cwgt r0, r1, r2
8 crc32wle r0, r1, r2
9
10 @ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified
11 @ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified
12 @ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified
13 @ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified
14 @ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified
15 @ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified
0 # RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s
1
2 # CHECK: crc32b r0, r1, r2
3 # CHECK: crc32h r0, r1, r2
4 # CHECK: crc32w r0, r1, r2
5 # CHECK: crc32cb r0, r1, r2
6 # CHECK: crc32ch r0, r1, r2
7 # CHECK: crc32cw r0, r1, r2
8
9 0xc1 0xfa 0x82 0xf0
10 0xc1 0xfa 0x92 0xf0
11 0xc1 0xfa 0xa2 0xf0
12 0xd1 0xfa 0x82 0xf0
13 0xd1 0xfa 0x92 0xf0
14 0xd1 0xfa 0xa2 0xf0
0 # RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s
1
2 # CHECK: crc32b r0, r1, r2
3 # CHECK: crc32h r0, r1, r2
4 # CHECK: crc32w r0, r1, r2
5 # CHECK: crc32cb r0, r1, r2
6 # CHECK: crc32ch r0, r1, r2
7 # CHECK: crc32cw r0, r1, r2
8
9 0x42 0x00 0x01 0xe1
10 0x42 0x00 0x21 0xe1
11 0x42 0x00 0x41 0xe1
12 0x42 0x02 0x01 0xe1
13 0x42 0x02 0x21 0xe1
14 0x42 0x02 0x41 0xe1