llvm.org GIT mirror llvm / 8603a3d
R600: Implement getRsqrtEstimate Only do for f32 since I'm unclear on both what this is expecting for the refinement steps in terms of accuracy, and what f64 instruction actually provides. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225827 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 5 years ago
4 changed file(s) with 63 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
25662566 }
25672567 }
25682568
2569 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2570 DAGCombinerInfo &DCI,
2571 unsigned &RefinementSteps,
2572 bool &UseOneConstNR) const {
2573 SelectionDAG &DAG = DCI.DAG;
2574 EVT VT = Operand.getValueType();
2575
2576 if (VT == MVT::f32) {
2577 RefinementSteps = 0;
2578 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2579 }
2580
2581 // TODO: There is also f64 rsq instruction, but the documentation is less
2582 // clear on its precision.
2583
2584 return SDValue();
2585 }
2586
25692587 static void computeKnownBitsForMinMax(const SDValue Op0,
25702588 const SDValue Op1,
25712589 APInt &KnownZero,
165165 SelectionDAG &DAG) const;
166166
167167 const char* getTargetNodeName(unsigned Opcode) const override;
168
169 SDValue getRsqrtEstimate(SDValue Operand,
170 DAGCombinerInfo &DCI,
171 unsigned &RefinementSteps,
172 bool &UseOneConstNR) const override;
168173
169174 virtual SDNode *PostISelFolding(MachineSDNode *N,
170175 SelectionDAG &DAG) const {
None ; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
0 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s
2
3 ; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x)
14
25 ; CHECK: {{^}}fsqrt_f32:
36 ; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
0 ; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s
11 ; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s
22
3 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
34 declare float @llvm.sqrt.f32(float) nounwind readnone
45 declare double @llvm.sqrt.f64(double) nounwind readnone
56
3536 store float %div, float addrspace(1)* %out, align 4
3637 ret void
3738 }
39
40 ; Recognize that this is rsqrt(a) * rcp(b) * c,
41 ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
42
43 ; SI-LABEL: @rsqrt_fmul
44 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
45 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
46 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
47
48 ; SI-UNSAFE-DAG: v_rsq_f32_e32 [[RSQA:v[0-9]+]], [[A]]
49 ; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCPB:v[0-9]+]], [[B]]
50 ; SI-UNSAFE-DAG: v_mul_f32_e32 [[TMP:v[0-9]+]], [[RCPB]], [[RSQA]]
51 ; SI-UNSAFE: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
52 ; SI-UNSAFE: buffer_store_dword [[RESULT]]
53
54 ; SI-SAFE-NOT: v_rsq_f32
55
56 ; SI: s_endpgm
57 define void @rsqrt_fmul(float addrspace(1)* %out, float addrspace(1)* %in) {
58 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
59 %out.gep = getelementptr float addrspace(1)* %out, i32 %tid
60 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
61 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
62 %gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
63
64 %a = load float addrspace(1)* %gep.0
65 %b = load float addrspace(1)* %gep.1
66 %c = load float addrspace(1)* %gep.2
67
68 %x = call float @llvm.sqrt.f32(float %a)
69 %y = fmul float %x, %b
70 %z = fdiv float %c, %y
71 store float %z, float addrspace(1)* %out.gep
72 ret void
73 }