llvm.org GIT mirror llvm / 85e42b4
Reserve G1 for frame offset stuff and use it to handle large stack frames. For example, instead of emitting this: test: save -40112, %o6, %o6 ;; imm too large add %i6, -40016, %o0 ;; imm too large call caller nop restore %g0, %g0, %g0 retl nop emit this: test: sethi 4194264, %g1 or %g1, 848, %g1 save %o6, %g1, %o6 sethi 4194264, %g1 add %g1, %i6, %g1 add %i1, 944, %o0 call caller nop restore %g0, %g0, %g0 retl nop which doesn't cause the assembler to barf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
4 changed file(s) with 84 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
9595
9696 int FrameIndex = MI.getOperand(i).getFrameIndex();
9797
98 // Replace frame index with a frame pointer reference
99 MI.SetMachineOperandReg (i, V8::I6);
100
10198 // Addressable stack objects are accessed using neg. offsets from %fp
10299 MachineFunction &MF = *MI.getParent()->getParent();
103100 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
104101 MI.getOperand(i+1).getImmedValue();
105 // note: Offset < 0
106 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
102
103 // Replace frame index with a frame pointer reference.
104 if (Offset >= -4096 && Offset <= 4095) {
105 // If the offset is small enough to fit in the immediate field, directly
106 // encode it.
107 MI.SetMachineOperandReg(i, V8::I6);
108 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
109 } else {
110 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
111 // scavenge a register here instead of reserving G1 all of the time.
112 unsigned OffHi = (unsigned)Offset >> 10U;
113 BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
114 // Emit G1 = G1 + I6
115 BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
116 V8::G1).addReg(V8::G1).addReg(V8::I6);
117 // Insert: G1+%lo(offset) into the user.
118 MI.SetMachineOperandReg(i, V8::I1);
119 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
120 Offset & ((1 << 10)-1));
121 }
107122 }
108123
109124 void SparcV8RegisterInfo::
127142 // Round up to next doubleword boundary -- a double-word boundary
128143 // is required by the ABI.
129144 NumBytes = (NumBytes + 7) & ~7;
130 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
131 V8::O6).addImm(-NumBytes).addReg(V8::O6);
145 NumBytes = -NumBytes;
146
147 if (NumBytes >= -4096) {
148 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
149 V8::O6).addImm(NumBytes).addReg(V8::O6);
150 } else {
151 MachineBasicBlock::iterator InsertPt = MBB.begin();
152 // Emit this the hard way. This clobbers G1 which we always know is
153 // available here.
154 unsigned OffHi = (unsigned)NumBytes >> 10U;
155 BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
156 // Emit G1 = G1 + I6
157 BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
158 .addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
159 BuildMI(MBB, InsertPt, V8::SAVErr, 2,
160 V8::O6).addReg(V8::O6).addReg(V8::G1);
161 }
132162 }
133163
134164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
8383 //
8484 def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
8585 I0, I1, I2, I3, I4, I5,
86 O0, O1, O2, O3, O4, O5, O7,
87
88 // FIXME: G1 reserved for now for large imm generation by frame code.
8689 G1,
87 O0, O1, O2, O3, O4, O5, O7,
8890 // Non-allocatable regs:
8991 G2, G3, G4, // FIXME: OK for use only in
9092 // applications, not libraries.
101103 IntRegsClass::iterator
102104 IntRegsClass::allocation_order_end(MachineFunction &MF) const {
103105 // FIXME: These special regs should be taken out of the regclass!
104 return end()-10; // Don't allocate special registers
106 return end()-10 // Don't allocate special registers
107 -1; // FIXME: G1 reserved for large imm generation by frame code.
105108 }
106109 }];
107110 }
9595
9696 int FrameIndex = MI.getOperand(i).getFrameIndex();
9797
98 // Replace frame index with a frame pointer reference
99 MI.SetMachineOperandReg (i, V8::I6);
100
10198 // Addressable stack objects are accessed using neg. offsets from %fp
10299 MachineFunction &MF = *MI.getParent()->getParent();
103100 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
104101 MI.getOperand(i+1).getImmedValue();
105 // note: Offset < 0
106 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
102
103 // Replace frame index with a frame pointer reference.
104 if (Offset >= -4096 && Offset <= 4095) {
105 // If the offset is small enough to fit in the immediate field, directly
106 // encode it.
107 MI.SetMachineOperandReg(i, V8::I6);
108 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
109 } else {
110 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
111 // scavenge a register here instead of reserving G1 all of the time.
112 unsigned OffHi = (unsigned)Offset >> 10U;
113 BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
114 // Emit G1 = G1 + I6
115 BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
116 V8::G1).addReg(V8::G1).addReg(V8::I6);
117 // Insert: G1+%lo(offset) into the user.
118 MI.SetMachineOperandReg(i, V8::I1);
119 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
120 Offset & ((1 << 10)-1));
121 }
107122 }
108123
109124 void SparcV8RegisterInfo::
127142 // Round up to next doubleword boundary -- a double-word boundary
128143 // is required by the ABI.
129144 NumBytes = (NumBytes + 7) & ~7;
130 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
131 V8::O6).addImm(-NumBytes).addReg(V8::O6);
145 NumBytes = -NumBytes;
146
147 if (NumBytes >= -4096) {
148 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
149 V8::O6).addImm(NumBytes).addReg(V8::O6);
150 } else {
151 MachineBasicBlock::iterator InsertPt = MBB.begin();
152 // Emit this the hard way. This clobbers G1 which we always know is
153 // available here.
154 unsigned OffHi = (unsigned)NumBytes >> 10U;
155 BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
156 // Emit G1 = G1 + I6
157 BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
158 .addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
159 BuildMI(MBB, InsertPt, V8::SAVErr, 2,
160 V8::O6).addReg(V8::O6).addReg(V8::G1);
161 }
132162 }
133163
134164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
8383 //
8484 def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
8585 I0, I1, I2, I3, I4, I5,
86 O0, O1, O2, O3, O4, O5, O7,
87
88 // FIXME: G1 reserved for now for large imm generation by frame code.
8689 G1,
87 O0, O1, O2, O3, O4, O5, O7,
8890 // Non-allocatable regs:
8991 G2, G3, G4, // FIXME: OK for use only in
9092 // applications, not libraries.
101103 IntRegsClass::iterator
102104 IntRegsClass::allocation_order_end(MachineFunction &MF) const {
103105 // FIXME: These special regs should be taken out of the regclass!
104 return end()-10; // Don't allocate special registers
106 return end()-10 // Don't allocate special registers
107 -1; // FIXME: G1 reserved for large imm generation by frame code.
105108 }
106109 }];
107110 }