llvm.org GIT mirror llvm / 85cf938
[PowerPC][UpdateTestChecks] powerpc- triple support There are quite some old testcases with powerpc- triple, we should add this triple support so that we can update them with script. Differential Revision: https://reviews.llvm.org/D63723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364213 91177308-0d34-0410-b5e6-96231b3b80d8 Jinsong Ji 1 year, 5 months ago
2 changed file(s) with 34 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck -check-prefix=P32 %s
12 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
23 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
34
45 ; PR8327
56 define i8* @test1(i8** %foo) nounwind {
7 ; P32-LABEL: test1:
8 ; P32: # %bb.0:
9 ; P32-NEXT: lbz r4, 0(r3)
10 ; P32-NEXT: addi r5, r4, 1
11 ; P32-NEXT: stb r5, 0(r3)
12 ; P32-NEXT: cmpwi r4, 8
13 ; P32-NEXT: lwz r5, 4(r3)
14 ; P32-NEXT: slwi r4, r4, 2
15 ; P32-NEXT: addi r6, r5, 4
16 ; P32-NEXT: bc 12, lt, .LBB0_1
17 ; P32-NEXT: b .LBB0_2
18 ; P32-NEXT: .LBB0_1:
19 ; P32-NEXT: addi r6, r5, 0
20 ; P32-NEXT: .LBB0_2:
21 ; P32-NEXT: stw r6, 4(r3)
22 ; P32-NEXT: lwz r3, 8(r3)
23 ; P32-NEXT: add r3, r3, r4
24 ; P32-NEXT: bc 12, lt, .LBB0_4
25 ; P32-NEXT: # %bb.3:
26 ; P32-NEXT: ori r3, r5, 0
27 ; P32-NEXT: b .LBB0_4
28 ; P32-NEXT: .LBB0_4:
29 ; P32-NEXT: lwz r3, 0(r3)
30 ; P32-NEXT: blr
31 ;
32 ; P64-LABEL: test1:
33 ; P64: # %bb.0:
34 ; P64-NEXT: ld r4, 0(r3)
35 ; P64-NEXT: addi r5, r4, 8
36 ; P64-NEXT: std r5, 0(r3)
37 ; P64-NEXT: ld r3, 0(r4)
38 ; P64-NEXT: blr
639 %A = va_arg i8** %foo, i8*
740 ret i8* %A
841 }
942
10 ; P32-LABEL: test1:
11 ; P32: lbz [[REG1:r[0-9]+]], 0(r3)
12 ; P32: addi [[REG2:r[0-9]+]], [[REG1]], 1
13 ; P32: stb [[REG2]], 0(r3)
14 ; P32: cmpwi [[REG1]], 8
15 ; P32: lwz [[REG3:r[0-9]+]], 4(r3)
16 ; P32: slwi [[REG4:r[0-9]+]], [[REG1]], 2
17 ; P32: addi [[REG5:r[0-9]+]], [[REG3]], 4
18 ; P32: bc 12, lt, .LBB0_1
19 ; P32: b .LBB0_2
20 ; P32: .LBB0_1:
21 ; P32: addi [[REG5]], [[REG3]], 0
22 ; P32: .LBB0_2:
23 ; P32: stw [[REG5]], 4(r3)
24 ; P32: lwz [[REG6:r[0-9]+]], 8(r3)
25 ; P32: add [[REG6]], [[REG6]], [[REG4]]
26 ; P32: bc 12, lt, .LBB0_4
27 ; P32: # %bb.3:
28 ; P32: ori [[REG6]], [[REG2]], 0
29 ; P32: b .LBB0_4
30 ; P32: .LBB0_4:
31 ; P32: lwz r3, 0([[REG6]])
32 ; P32: blr
3343
34 ; P64-LABEL: test1:
35 ; P64: ld [[REG1:r[0-9]+]], 0(r3)
36 ; P64: addi [[REG2:r[0-9]+]], [[REG1]], 8
37 ; P64: std [[REG2]], 0(r3)
38 ; P64: ld r3, 0([[REG1]])
39 ; P64: blr
40
307307 'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
308308 'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE),
309309 'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
310 'powerpc64': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
311 'powerpc64le': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
310 'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
312311 'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
313312 'riscv64': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
314313 'lanai': (scrub_asm_lanai, ASM_FUNCTION_LANAI_RE),