llvm.org GIT mirror llvm / 85aa6fd
Have getCallPreservedMask and getThisCallPreservedMask take a MachineFunction argument so that we can grab subtarget specific features off of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231979 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 4 years ago
28 changed file(s) with 78 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
427427 getCalleeSavedRegs(const MachineFunction *MF) const = 0;
428428
429429 /// getCallPreservedMask - Return a mask of call-preserved registers for the
430 /// given calling convention on the current sub-target. The mask should
430 /// given calling convention on the current function. The mask should
431431 /// include all call-preserved aliases. This is used by the register
432432 /// allocator to determine which registers can be live across a call.
433433 ///
444444 /// instructions should use implicit-def operands to indicate call clobbered
445445 /// registers.
446446 ///
447 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
447 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
448 CallingConv::ID) const {
448449 // The default mask clobbers everything. All targets should override.
449450 return nullptr;
450451 }
800800 return false;
801801
802802 // Push the register mask info.
803 Ops.push_back(MachineOperand::CreateRegMask(TRI.getCallPreservedMask(CC)));
803 Ops.push_back(MachineOperand::CreateRegMask(
804 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
804805
805806 // Add scratch registers as implicit def and early clobber.
806807 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
31573157
31583158 // Add a register mask with the call-preserved registers.
31593159 // Proper defs for return values will be added by setPhysRegsDeadExcept().
3160 MIB.addRegMask(TRI.getCallPreservedMask(CC));
3160 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
31613161
31623162 CLI.Call = MIB;
31633163
27932793 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
27942794 if (IsThisReturn) {
27952795 // For 'this' returns, use the X0-preserving mask if applicable
2796 Mask = TRI->getThisReturnPreservedMask(CallConv);
2796 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
27972797 if (!Mask) {
27982798 IsThisReturn = false;
2799 Mask = TRI->getCallPreservedMask(CallConv);
2799 Mask = TRI->getCallPreservedMask(MF, CallConv);
28002800 }
28012801 } else
2802 Mask = TRI->getCallPreservedMask(CallConv);
2802 Mask = TRI->getCallPreservedMask(MF, CallConv);
28032803
28042804 assert(Mask && "Missing call preserved mask for calling convention");
28052805 Ops.push_back(DAG.getRegisterMask(Mask));
5454 }
5555
5656 const uint32_t *
57 AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
57 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
58 CallingConv::ID CC) const {
5859 if (CC == CallingConv::GHC)
5960 // This is academic becase all GHC calls are (supposed to be) tail calls
6061 return CSR_AArch64_NoRegs_RegMask;
7374 }
7475
7576 const uint32_t *
76 AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const {
77 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
78 CallingConv::ID CC) const {
7779 // This should return a register mask that is the same as that returned by
7880 // getCallPreservedMask but that additionally preserves the register used for
7981 // the first i64 argument (which must also be the register used to return a
3636
3737 /// Code Generation virtual methods...
3838 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
39 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
39 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
40 CallingConv::ID) const override;
4041
4142 unsigned getCSRFirstUseCost() const override {
4243 // The cost will be compared against BlockFrequency where entry has the
5758 ///
5859 /// Should return NULL in the case that the calling convention does not have
5960 /// this property
60 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
61 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
62 CallingConv::ID) const;
6163
6264 BitVector getReservedRegs(const MachineFunction &MF) const override;
6365 const TargetRegisterClass *
8686 return RegList;
8787 }
8888
89 const uint32_t*
90 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
89 const uint32_t *
90 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
91 CallingConv::ID CC) const {
9192 if (CC == CallingConv::GHC)
9293 // This is academic becase all GHC calls are (supposed to be) tail calls
9394 return CSR_NoRegs_RegMask;
99100 return CSR_NoRegs_RegMask;
100101 }
101102
102 const uint32_t*
103 ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const {
103 const uint32_t *
104 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
105 CallingConv::ID CC) const {
104106 // This should return a register mask that is the same as that returned by
105107 // getCallPreservedMask but that additionally preserves the register used for
106108 // the first i32 argument (which must also be the register used to return a
100100 public:
101101 /// Code Generation virtual methods...
102102 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
103 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
103 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
104 CallingConv::ID) const override;
104105 const uint32_t *getNoPreservedMask() const;
105106
106107 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
111112 ///
112113 /// Should return NULL in the case that the calling convention does not have
113114 /// this property
114 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
115 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
116 CallingConv::ID) const;
115117
116118 BitVector getReservedRegs(const MachineFunction &MF) const override;
117119
22642264
22652265 // Add a register mask with the call-preserved registers.
22662266 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2267 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2267 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
22682268
22692269 // Finish off the call including any return values.
22702270 SmallVector UsedRegs;
24152415
24162416 // Add a register mask with the call-preserved registers.
24172417 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2418 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2418 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
24192419
24202420 // Finish off the call including any return values.
24212421 SmallVector UsedRegs;
18131813 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
18141814 if (isThisReturn) {
18151815 // For 'this' returns, use the R0-preserving mask if applicable
1816 Mask = ARI->getThisReturnPreservedMask(CallConv);
1816 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
18171817 if (!Mask) {
18181818 // Set isThisReturn to false if the calling convention is not one that
18191819 // allows 'returned' to be modeled in this way, so LowerCallResult does
18201820 // not try to pass 'this' straight through
18211821 isThisReturn = false;
1822 Mask = ARI->getCallPreservedMask(CallConv);
1822 Mask = ARI->getCallPreservedMask(MF, CallConv);
18231823 }
18241824 } else
1825 Mask = ARI->getCallPreservedMask(CallConv);
1825 Mask = ARI->getCallPreservedMask(MF, CallConv);
18261826
18271827 assert(Mask && "Missing call preserved mask for calling convention");
18281828 Ops.push_back(DAG.getRegisterMask(Mask));
11661166
11671167 // Add a register mask with the call-preserved registers.
11681168 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1169 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1169 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
11701170
11711171 CLI.Call = MIB;
11721172
24802480
24812481 // Add a register mask operand representing the call-preserved registers.
24822482 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2483 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2483 const uint32_t *Mask =
2484 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
24842485 assert(Mask && "Missing call preserved mask for calling convention");
24852486 if (Subtarget.inMips16HardFloat()) {
24862487 if (GlobalAddressSDNode *G = dyn_cast(CLI.Callee)) {
9999 return CSR_O32_SaveList;
100100 }
101101
102 const uint32_t*
103 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
102 const uint32_t *
103 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
104 CallingConv::ID) const {
104105 if (Subtarget.isSingleFloat())
105106 return CSR_SingleFloatOnly_RegMask;
106107
4747 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
4848 MachineFunction &MF) const override;
4949 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
50 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
50 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
51 CallingConv::ID) const override;
5152 static const uint32_t *getMips16RetHelperMask();
5253
5354 BitVector getReservedRegs(const MachineFunction &MF) const override;
15311531
15321532 // Add a register mask with the call-preserved registers. Proper
15331533 // defs for return values will be added by setPhysRegsDeadExcept().
1534 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1534 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
15351535
15361536 CLI.Call = MIB;
15371537
41864186
41874187 // Add a register mask operand representing the call-preserved registers.
41884188 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
4189 const uint32_t *Mask =
4190 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
41904191 assert(Mask && "Missing call preserved mask for calling convention");
41914192 Ops.push_back(DAG.getRegisterMask(Mask));
41924193
127127 CSR_SVR432_SaveList);
128128 }
129129
130 const uint32_t*
131 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
130 const uint32_t *
131 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
132 CallingConv::ID CC) const {
132133 if (CC == CallingConv::AnyReg) {
133134 if (Subtarget.hasVSX())
134135 return CSR_64_AllRegs_VSX_RegMask;
4545
4646 /// Code Generation virtual methods...
4747 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
48 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
48 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
49 CallingConv::ID CC) const override;
4950 const uint32_t *getNoPreservedMask() const;
5051
5152 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
914914
915915 // Add a register mask operand representing the call-preserved registers.
916916 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
917 const uint32_t *Mask = ((hasReturnsTwice)
918 ? TRI->getRTCallPreservedMask(CallConv)
919 : TRI->getCallPreservedMask(CallConv));
917 const uint32_t *Mask =
918 ((hasReturnsTwice)
919 ? TRI->getRTCallPreservedMask(CallConv)
920 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
920921 assert(Mask && "Missing call preserved mask for calling convention");
921922 Ops.push_back(DAG.getRegisterMask(Mask));
922923
12281229 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
12291230 const uint32_t *Mask =
12301231 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1231 : TRI->getCallPreservedMask(CLI.CallConv));
1232 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1233 CLI.CallConv));
12321234 assert(Mask && "Missing call preserved mask for calling convention");
12331235 Ops.push_back(DAG.getRegisterMask(Mask));
12341236
19031905 Ops.push_back(Callee);
19041906 Ops.push_back(Symbol);
19051907 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1906 const uint32_t *Mask =
1907 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
1908 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1909 DAG.getMachineFunction(), CallingConv::C);
19081910 assert(Mask && "Missing call preserved mask for calling convention");
19091911 Ops.push_back(DAG.getRegisterMask(Mask));
19101912 Ops.push_back(InFlag);
4242 return CSR_SaveList;
4343 }
4444
45 const uint32_t*
46 SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
45 const uint32_t *
46 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
47 CallingConv::ID CC) const {
4748 return CSR_RegMask;
4849 }
4950
3131
3232 /// Code Generation virtual methods...
3333 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
34 const uint32_t* getCallPreservedMask(CallingConv::ID CC) const override;
34 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
35 CallingConv::ID CC) const override;
3536
3637 const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
3738
919919
920920 // Add a register mask operand representing the call-preserved registers.
921921 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
922 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
922 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
923923 assert(Mask && "Missing call preserved mask for calling convention");
924924 Ops.push_back(DAG.getRegisterMask(Mask));
925925
18571857
18581858 // Add a register mask operand representing the call-preserved registers.
18591859 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1860 const uint32_t *Mask = TRI->getCallPreservedMask(CallingConv::C);
1860 const uint32_t *Mask =
1861 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
18611862 assert(Mask && "Missing call preserved mask for calling convention");
18621863 Ops.push_back(DAG.getRegisterMask(Mask));
18631864
2727 }
2828
2929 const uint32_t *
30 SystemZRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
30 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
31 CallingConv::ID CC) const {
3132 return CSR_SystemZ_RegMask;
3233 }
3334
4343 return true;
4444 }
4545 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
46 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
46 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
47 CallingConv::ID CC) const override;
4748 BitVector getReservedRegs(const MachineFunction &MF) const override;
4849 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
4950 int SPAdj, unsigned FIOperandNum,
30613061
30623062 // Add a register mask operand representing the call-preserved registers.
30633063 // Proper defs for return values will be added by setPhysRegsDeadExcept().
3064 MIB.addRegMask(TRI.getCallPreservedMask(CC));
3064 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
30653065
30663066 // Add an implicit use GOT pointer in EBX.
30673067 if (Subtarget->isPICStyleGOT())
31603160
31613161 // Add a register mask operand representing the call-preserved registers.
31623162 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3163 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3163 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
31643164 assert(Mask && "Missing call preserved mask for calling convention");
31653165 Ops.push_back(DAG.getRegisterMask(Mask));
31663166
1845218452
1845318453 // Calls into a routine in libgcc to allocate more space from the heap.
1845418454 const uint32_t *RegMask =
18455 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18455 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
1845618456 if (IsLP64) {
1845718457 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
1845818458 .addReg(sizeVReg);
1853718537 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
1853818538 // proper register mask.
1853918539 const uint32_t *RegMask =
18540 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18540 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
1854118541 if (Subtarget->is64Bit()) {
1854218542 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
1854318543 TII->get(X86::MOV64rm), X86::RDI)
276276 return CSR_32_SaveList;
277277 }
278278
279 const uint32_t*
280 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
279 const uint32_t *
280 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
281 CallingConv::ID CC) const {
281282 bool HasAVX = Subtarget.hasAVX();
282283 bool HasAVX512 = Subtarget.hasAVX512();
283284
359360 // Set the base-pointer register and its aliases as reserved if needed.
360361 if (hasBasePointer(MF)) {
361362 CallingConv::ID CC = MF.getFunction()->getCallingConv();
362 const uint32_t* RegMask = getCallPreservedMask(CC);
363 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
363364 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
364365 report_fatal_error(
365366 "Stack realignment in presence of dynamic allocas is not supported with"
9898 /// callee-save registers on this target.
9999 const MCPhysReg *
100100 getCalleeSavedRegs(const MachineFunction* MF) const override;
101 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
101 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
102 CallingConv::ID) const override;
102103 const uint32_t *getNoPreservedMask() const;
103104
104105 /// getReservedRegs - Returns a bitset indexed by physical register number