llvm.org GIT mirror llvm / 8577619
[ARM] GlobalISel: Select s64 G_FCMP Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307763 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
2 changed file(s) with 643 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
347347 // The assumed register bank ID for the operands.
348348 static const unsigned OperandRegBankID;
349349
350 // The assumed size in bits for the operands.
351 static const unsigned OperandSize;
352
350353 // The assumed register bank ID for the result.
351354 static const unsigned ResultRegBankID = ARM::GPRRegBankID;
352355
419422 bool validateOpReg(unsigned OpReg, MachineRegisterInfo &MRI,
420423 const TargetRegisterInfo &TRI,
421424 const RegisterBankInfo &RBI) {
422 if (MRI.getType(OpReg).getSizeInBits() != 32) {
425 if (MRI.getType(OpReg).getSizeInBits() != OperandSize) {
423426 DEBUG(dbgs() << "Unsupported size for comparison operand");
424427 return false;
425428 }
451454 template <>
452455 const unsigned ARMInstructionSelector::CmpHelper::ComparisonOpcode =
453456 ARM::VCMPS;
457 template <>
458 const unsigned ARMInstructionSelector::CmpHelper::ComparisonOpcode =
459 ARM::VCMPD;
454460
455461 // Specialize the opcode to be used for reading the comparison flags for
456462 // different types of operands.
460466 template <>
461467 const unsigned ARMInstructionSelector::CmpHelper::ReadFlagsOpcode =
462468 ARM::FMSTAT;
469 template <>
470 const unsigned ARMInstructionSelector::CmpHelper::ReadFlagsOpcode =
471 ARM::FMSTAT;
463472
464473 // Specialize the register bank where the operands of the comparison are assumed
465474 // to live.
469478 template <>
470479 const unsigned ARMInstructionSelector::CmpHelper::OperandRegBankID =
471480 ARM::FPRRegBankID;
481 template <>
482 const unsigned ARMInstructionSelector::CmpHelper::OperandRegBankID =
483 ARM::FPRRegBankID;
484
485 // Specialize the size that the operands of the comparison are assumed to have.
486 template <>
487 const unsigned ARMInstructionSelector::CmpHelper::OperandSize = 32;
488 template <>
489 const unsigned ARMInstructionSelector::CmpHelper::OperandSize = 32;
490 template <>
491 const unsigned ARMInstructionSelector::CmpHelper::OperandSize = 64;
472492
473493 template
474494 bool ARMInstructionSelector::selectCmp(MachineInstrBuilder &MIB,
666686 return selectSelect(MIB, TII, MRI, TRI, RBI);
667687 case G_ICMP:
668688 return selectCmp(MIB, TII, MRI, TRI, RBI);
669 case G_FCMP:
689 case G_FCMP: {
670690 assert(TII.getSubtarget().hasVFP2() && "Can't select fcmp without VFP");
671 return selectCmp(MIB, TII, MRI, TRI, RBI);
691
692 unsigned OpReg = I.getOperand(2).getReg();
693 unsigned Size = MRI.getType(OpReg).getSizeInBits();
694 if (Size == 32)
695 return selectCmp(MIB, TII, MRI, TRI, RBI);
696 if (Size == 64) {
697 if (TII.getSubtarget().isFPOnlySP()) {
698 DEBUG(dbgs() << "Subtarget only supports single precision");
699 return false;
700 }
701 return selectCmp(MIB, TII, MRI, TRI, RBI);
702 }
703
704 DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
705 return false;
706 }
672707 case G_GEP:
673708 I.setDesc(TII.get(ARM::ADDrr));
674709 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
2929 define void @test_fcmp_one_s32() #0 { ret void }
3030 define void @test_fcmp_ueq_s32() #0 { ret void }
3131
32 define void @test_fcmp_true_s64() #0 { ret void }
33 define void @test_fcmp_false_s64() #0 { ret void }
34
35 define void @test_fcmp_oeq_s64() #0 { ret void }
36 define void @test_fcmp_ogt_s64() #0 { ret void }
37 define void @test_fcmp_oge_s64() #0 { ret void }
38 define void @test_fcmp_olt_s64() #0 { ret void }
39 define void @test_fcmp_ole_s64() #0 { ret void }
40 define void @test_fcmp_ord_s64() #0 { ret void }
41 define void @test_fcmp_ugt_s64() #0 { ret void }
42 define void @test_fcmp_uge_s64() #0 { ret void }
43 define void @test_fcmp_ult_s64() #0 { ret void }
44 define void @test_fcmp_ule_s64() #0 { ret void }
45 define void @test_fcmp_une_s64() #0 { ret void }
46 define void @test_fcmp_uno_s64() #0 { ret void }
47
48 define void @test_fcmp_one_s64() #0 { ret void }
49 define void @test_fcmp_ueq_s64() #0 { ret void }
50
3251 attributes #0 = { "target-features"="+vfp2" }
3352 ...
3453 ---
977996 BX_RET 14, _, implicit %r0
978997 ; CHECK: BX_RET 14, _, implicit %r0
979998 ...
999 ---
1000 name: test_fcmp_true_s64
1001 # CHECK-LABEL: name: test_fcmp_true_s64
1002 legalized: true
1003 regBankSelected: true
1004 selected: false
1005 # CHECK: selected: true
1006 registers:
1007 - { id: 0, class: fprb }
1008 - { id: 1, class: fprb }
1009 - { id: 2, class: gprb }
1010 - { id: 3, class: gprb }
1011 body: |
1012 bb.0:
1013 liveins: %d0, %d1
1014
1015 %0(s64) = COPY %d0
1016 %1(s64) = COPY %d1
1017
1018 %2(s1) = G_FCMP floatpred(true), %0(s64), %1
1019 ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
1020
1021 %3(s32) = G_ZEXT %2(s1)
1022 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1023
1024 %r0 = COPY %3(s32)
1025 ; CHECK: %r0 = COPY [[RET]]
1026
1027 BX_RET 14, _, implicit %r0
1028 ; CHECK: BX_RET 14, _, implicit %r0
1029 ...
1030 ---
1031 name: test_fcmp_false_s64
1032 # CHECK-LABEL: name: test_fcmp_false_s64
1033 legalized: true
1034 regBankSelected: true
1035 selected: false
1036 # CHECK: selected: true
1037 registers:
1038 - { id: 0, class: fprb }
1039 - { id: 1, class: fprb }
1040 - { id: 2, class: gprb }
1041 - { id: 3, class: gprb }
1042 body: |
1043 bb.0:
1044 liveins: %d0, %d1
1045
1046 %0(s64) = COPY %d0
1047 %1(s64) = COPY %d1
1048
1049 %2(s1) = G_FCMP floatpred(false), %0(s64), %1
1050 ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
1051
1052 %3(s32) = G_ZEXT %2(s1)
1053 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1054
1055 %r0 = COPY %3(s32)
1056 ; CHECK: %r0 = COPY [[RET]]
1057
1058 BX_RET 14, _, implicit %r0
1059 ; CHECK: BX_RET 14, _, implicit %r0
1060 ...
1061 ---
1062 name: test_fcmp_oeq_s64
1063 # CHECK-LABEL: name: test_fcmp_oeq_s64
1064 legalized: true
1065 regBankSelected: true
1066 selected: false
1067 # CHECK: selected: true
1068 registers:
1069 - { id: 0, class: fprb }
1070 - { id: 1, class: fprb }
1071 - { id: 2, class: gprb }
1072 - { id: 3, class: gprb }
1073 body: |
1074 bb.0:
1075 liveins: %d0, %d1
1076
1077 %0(s64) = COPY %d0
1078 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1079
1080 %1(s64) = COPY %d1
1081 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1082
1083 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
1084 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1085 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1086 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1087 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
1088
1089 %3(s32) = G_ZEXT %2(s1)
1090 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1091
1092 %r0 = COPY %3(s32)
1093 ; CHECK: %r0 = COPY [[RET]]
1094
1095 BX_RET 14, _, implicit %r0
1096 ; CHECK: BX_RET 14, _, implicit %r0
1097 ...
1098 ---
1099 name: test_fcmp_ogt_s64
1100 # CHECK-LABEL: name: test_fcmp_ogt_s64
1101 legalized: true
1102 regBankSelected: true
1103 selected: false
1104 # CHECK: selected: true
1105 registers:
1106 - { id: 0, class: fprb }
1107 - { id: 1, class: fprb }
1108 - { id: 2, class: gprb }
1109 - { id: 3, class: gprb }
1110 body: |
1111 bb.0:
1112 liveins: %d0, %d1
1113
1114 %0(s64) = COPY %d0
1115 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1116
1117 %1(s64) = COPY %d1
1118 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1119
1120 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
1121 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1122 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1123 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1124 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
1125
1126 %3(s32) = G_ZEXT %2(s1)
1127 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1128
1129 %r0 = COPY %3(s32)
1130 ; CHECK: %r0 = COPY [[RET]]
1131
1132 BX_RET 14, _, implicit %r0
1133 ; CHECK: BX_RET 14, _, implicit %r0
1134 ...
1135 ---
1136 name: test_fcmp_oge_s64
1137 # CHECK-LABEL: name: test_fcmp_oge_s64
1138 legalized: true
1139 regBankSelected: true
1140 selected: false
1141 # CHECK: selected: true
1142 registers:
1143 - { id: 0, class: fprb }
1144 - { id: 1, class: fprb }
1145 - { id: 2, class: gprb }
1146 - { id: 3, class: gprb }
1147 body: |
1148 bb.0:
1149 liveins: %d0, %d1
1150
1151 %0(s64) = COPY %d0
1152 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1153
1154 %1(s64) = COPY %d1
1155 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1156
1157 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1
1158 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1159 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1160 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1161 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
1162
1163 %3(s32) = G_ZEXT %2(s1)
1164 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1165
1166 %r0 = COPY %3(s32)
1167 ; CHECK: %r0 = COPY [[RET]]
1168
1169 BX_RET 14, _, implicit %r0
1170 ; CHECK: BX_RET 14, _, implicit %r0
1171 ...
1172 ---
1173 name: test_fcmp_olt_s64
1174 # CHECK-LABEL: name: test_fcmp_olt_s64
1175 legalized: true
1176 regBankSelected: true
1177 selected: false
1178 # CHECK: selected: true
1179 registers:
1180 - { id: 0, class: fprb }
1181 - { id: 1, class: fprb }
1182 - { id: 2, class: gprb }
1183 - { id: 3, class: gprb }
1184 body: |
1185 bb.0:
1186 liveins: %d0, %d1
1187
1188 %0(s64) = COPY %d0
1189 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1190
1191 %1(s64) = COPY %d1
1192 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1193
1194 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1
1195 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1196 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1197 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1198 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
1199
1200 %3(s32) = G_ZEXT %2(s1)
1201 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1202
1203 %r0 = COPY %3(s32)
1204 ; CHECK: %r0 = COPY [[RET]]
1205
1206 BX_RET 14, _, implicit %r0
1207 ; CHECK: BX_RET 14, _, implicit %r0
1208 ...
1209 ---
1210 name: test_fcmp_ole_s64
1211 # CHECK-LABEL: name: test_fcmp_ole_s64
1212 legalized: true
1213 regBankSelected: true
1214 selected: false
1215 # CHECK: selected: true
1216 registers:
1217 - { id: 0, class: fprb }
1218 - { id: 1, class: fprb }
1219 - { id: 2, class: gprb }
1220 - { id: 3, class: gprb }
1221 body: |
1222 bb.0:
1223 liveins: %d0, %d1
1224
1225 %0(s64) = COPY %d0
1226 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1227
1228 %1(s64) = COPY %d1
1229 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1230
1231 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1
1232 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1233 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1234 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1235 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
1236
1237 %3(s32) = G_ZEXT %2(s1)
1238 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1239
1240 %r0 = COPY %3(s32)
1241 ; CHECK: %r0 = COPY [[RET]]
1242
1243 BX_RET 14, _, implicit %r0
1244 ; CHECK: BX_RET 14, _, implicit %r0
1245 ...
1246 ---
1247 name: test_fcmp_ord_s64
1248 # CHECK-LABEL: name: test_fcmp_ord_s64
1249 legalized: true
1250 regBankSelected: true
1251 selected: false
1252 # CHECK: selected: true
1253 registers:
1254 - { id: 0, class: fprb }
1255 - { id: 1, class: fprb }
1256 - { id: 2, class: gprb }
1257 - { id: 3, class: gprb }
1258 body: |
1259 bb.0:
1260 liveins: %d0, %d1
1261
1262 %0(s64) = COPY %d0
1263 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1264
1265 %1(s64) = COPY %d1
1266 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1267
1268 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1
1269 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1270 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1271 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1272 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
1273
1274 %3(s32) = G_ZEXT %2(s1)
1275 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1276
1277 %r0 = COPY %3(s32)
1278 ; CHECK: %r0 = COPY [[RET]]
1279
1280 BX_RET 14, _, implicit %r0
1281 ; CHECK: BX_RET 14, _, implicit %r0
1282 ...
1283 ---
1284 name: test_fcmp_ugt_s64
1285 # CHECK-LABEL: name: test_fcmp_ugt_s64
1286 legalized: true
1287 regBankSelected: true
1288 selected: false
1289 # CHECK: selected: true
1290 registers:
1291 - { id: 0, class: fprb }
1292 - { id: 1, class: fprb }
1293 - { id: 2, class: gprb }
1294 - { id: 3, class: gprb }
1295 body: |
1296 bb.0:
1297 liveins: %d0, %d1
1298
1299 %0(s64) = COPY %d0
1300 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1301
1302 %1(s64) = COPY %d1
1303 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1304
1305 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
1306 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1307 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1308 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1309 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
1310
1311 %3(s32) = G_ZEXT %2(s1)
1312 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1313
1314 %r0 = COPY %3(s32)
1315 ; CHECK: %r0 = COPY [[RET]]
1316
1317 BX_RET 14, _, implicit %r0
1318 ; CHECK: BX_RET 14, _, implicit %r0
1319 ...
1320 ---
1321 name: test_fcmp_uge_s64
1322 # CHECK-LABEL: name: test_fcmp_uge_s64
1323 legalized: true
1324 regBankSelected: true
1325 selected: false
1326 # CHECK: selected: true
1327 registers:
1328 - { id: 0, class: fprb }
1329 - { id: 1, class: fprb }
1330 - { id: 2, class: gprb }
1331 - { id: 3, class: gprb }
1332 body: |
1333 bb.0:
1334 liveins: %d0, %d1
1335
1336 %0(s64) = COPY %d0
1337 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1338
1339 %1(s64) = COPY %d1
1340 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1341
1342 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1
1343 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1344 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1345 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1346 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
1347
1348 %3(s32) = G_ZEXT %2(s1)
1349 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1350
1351 %r0 = COPY %3(s32)
1352 ; CHECK: %r0 = COPY [[RET]]
1353
1354 BX_RET 14, _, implicit %r0
1355 ; CHECK: BX_RET 14, _, implicit %r0
1356 ...
1357 ---
1358 name: test_fcmp_ult_s64
1359 # CHECK-LABEL: name: test_fcmp_ult_s64
1360 legalized: true
1361 regBankSelected: true
1362 selected: false
1363 # CHECK: selected: true
1364 registers:
1365 - { id: 0, class: fprb }
1366 - { id: 1, class: fprb }
1367 - { id: 2, class: gprb }
1368 - { id: 3, class: gprb }
1369 body: |
1370 bb.0:
1371 liveins: %d0, %d1
1372
1373 %0(s64) = COPY %d0
1374 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1375
1376 %1(s64) = COPY %d1
1377 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1378
1379 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1
1380 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1381 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1382 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1383 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
1384
1385 %3(s32) = G_ZEXT %2(s1)
1386 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1387
1388 %r0 = COPY %3(s32)
1389 ; CHECK: %r0 = COPY [[RET]]
1390
1391 BX_RET 14, _, implicit %r0
1392 ; CHECK: BX_RET 14, _, implicit %r0
1393 ...
1394 ---
1395 name: test_fcmp_ule_s64
1396 # CHECK-LABEL: name: test_fcmp_ule_s64
1397 legalized: true
1398 regBankSelected: true
1399 selected: false
1400 # CHECK: selected: true
1401 registers:
1402 - { id: 0, class: fprb }
1403 - { id: 1, class: fprb }
1404 - { id: 2, class: gprb }
1405 - { id: 3, class: gprb }
1406 body: |
1407 bb.0:
1408 liveins: %d0, %d1
1409
1410 %0(s64) = COPY %d0
1411 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1412
1413 %1(s64) = COPY %d1
1414 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1415
1416 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1
1417 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1418 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1419 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1420 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
1421
1422 %3(s32) = G_ZEXT %2(s1)
1423 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1424
1425 %r0 = COPY %3(s32)
1426 ; CHECK: %r0 = COPY [[RET]]
1427
1428 BX_RET 14, _, implicit %r0
1429 ; CHECK: BX_RET 14, _, implicit %r0
1430 ...
1431 ---
1432 name: test_fcmp_une_s64
1433 # CHECK-LABEL: name: test_fcmp_une_s64
1434 legalized: true
1435 regBankSelected: true
1436 selected: false
1437 # CHECK: selected: true
1438 registers:
1439 - { id: 0, class: fprb }
1440 - { id: 1, class: fprb }
1441 - { id: 2, class: gprb }
1442 - { id: 3, class: gprb }
1443 body: |
1444 bb.0:
1445 liveins: %d0, %d1
1446
1447 %0(s64) = COPY %d0
1448 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1449
1450 %1(s64) = COPY %d1
1451 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1452
1453 %2(s1) = G_FCMP floatpred(une), %0(s64), %1
1454 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1455 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1456 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1457 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
1458
1459 %3(s32) = G_ZEXT %2(s1)
1460 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1461
1462 %r0 = COPY %3(s32)
1463 ; CHECK: %r0 = COPY [[RET]]
1464
1465 BX_RET 14, _, implicit %r0
1466 ; CHECK: BX_RET 14, _, implicit %r0
1467 ...
1468 ---
1469 name: test_fcmp_uno_s64
1470 # CHECK-LABEL: name: test_fcmp_uno_s64
1471 legalized: true
1472 regBankSelected: true
1473 selected: false
1474 # CHECK: selected: true
1475 registers:
1476 - { id: 0, class: fprb }
1477 - { id: 1, class: fprb }
1478 - { id: 2, class: gprb }
1479 - { id: 3, class: gprb }
1480 body: |
1481 bb.0:
1482 liveins: %d0, %d1
1483
1484 %0(s64) = COPY %d0
1485 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1486
1487 %1(s64) = COPY %d1
1488 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1489
1490 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1
1491 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1492 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1493 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1494 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
1495
1496 %3(s32) = G_ZEXT %2(s1)
1497 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1498
1499 %r0 = COPY %3(s32)
1500 ; CHECK: %r0 = COPY [[RET]]
1501
1502 BX_RET 14, _, implicit %r0
1503 ; CHECK: BX_RET 14, _, implicit %r0
1504 ...
1505 ---
1506 name: test_fcmp_one_s64
1507 # CHECK-LABEL: name: test_fcmp_one_s64
1508 legalized: true
1509 regBankSelected: true
1510 selected: false
1511 # CHECK: selected: true
1512 registers:
1513 - { id: 0, class: fprb }
1514 - { id: 1, class: fprb }
1515 - { id: 2, class: gprb }
1516 - { id: 3, class: gprb }
1517 body: |
1518 bb.0:
1519 liveins: %d0, %d1
1520
1521 %0(s64) = COPY %d0
1522 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1523
1524 %1(s64) = COPY %d1
1525 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1526
1527 %2(s1) = G_FCMP floatpred(one), %0(s64), %1
1528 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1529 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1530 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1531 ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
1532 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1533 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1534 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
1535
1536 %3(s32) = G_ZEXT %2(s1)
1537 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1538
1539 %r0 = COPY %3(s32)
1540 ; CHECK: %r0 = COPY [[RET]]
1541
1542 BX_RET 14, _, implicit %r0
1543 ; CHECK: BX_RET 14, _, implicit %r0
1544 ...
1545 ---
1546 name: test_fcmp_ueq_s64
1547 # CHECK-LABEL: name: test_fcmp_ueq_s64
1548 legalized: true
1549 regBankSelected: true
1550 selected: false
1551 # CHECK: selected: true
1552 registers:
1553 - { id: 0, class: fprb }
1554 - { id: 1, class: fprb }
1555 - { id: 2, class: gprb }
1556 - { id: 3, class: gprb }
1557 body: |
1558 bb.0:
1559 liveins: %d0, %d1
1560
1561 %0(s64) = COPY %d0
1562 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1563
1564 %1(s64) = COPY %d1
1565 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1566
1567 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
1568 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1569 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1570 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1571 ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
1572 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1573 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1574 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
1575
1576 %3(s32) = G_ZEXT %2(s1)
1577 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1578
1579 %r0 = COPY %3(s32)
1580 ; CHECK: %r0 = COPY [[RET]]
1581
1582 BX_RET 14, _, implicit %r0
1583 ; CHECK: BX_RET 14, _, implicit %r0
1584 ...