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[AVR] Define the ROL instruction as an alias of ADC The 'rol Rd' instruction is equivalent to 'adc Rd'. This caused compile warnings from tablegen because of conflicting bits shared between each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341275 91177308-0d34-0410-b5e6-96231b3b80d8 Dylan McKay 2 years ago
4 changed file(s) with 16 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
12511251 bool DstIsKill = MI.getOperand(1).isKill();
12521252 bool ImpIsDead = MI.getOperand(2).isDead();
12531253 OpLo = AVR::LSLRd;
1254 OpHi = AVR::ROLRd;
1254 OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
12551255 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
12561256
12571257 // Low part
12611261
12621262 auto MIBHI = buildMI(MBB, MBBI, OpHi)
12631263 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1264 .addReg(DstHiReg)
12641265 .addReg(DstHiReg, getKillRegState(DstIsKill));
12651266
12661267 if (ImpIsDead)
1267 MIBHI->getOperand(2).setIsDead();
1268 MIBHI->getOperand(3).setIsDead();
12681269
12691270 // SREG is always implicitly killed
1270 MIBHI->getOperand(3).setIsKill();
1271 MIBHI->getOperand(4).setIsKill();
12711272
12721273 MI.eraseFromParent();
12731274 return true;
14291429 MachineBasicBlock *BB) const {
14301430 unsigned Opc;
14311431 const TargetRegisterClass *RC;
1432 bool HasRepeatedOperand = false;
14321433 MachineFunction *F = BB->getParent();
14331434 MachineRegisterInfo &RI = F->getRegInfo();
14341435 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
14631464 RC = &AVR::DREGSRegClass;
14641465 break;
14651466 case AVR::Rol8:
1466 Opc = AVR::ROLRd;
1467 Opc = AVR::ADCRdRr; // ROL is an alias of ADC Rd, Rd
14671468 RC = &AVR::GPR8RegClass;
1469 HasRepeatedOperand = true;
14681470 break;
14691471 case AVR::Rol16:
14701472 Opc = AVR::ROLWRd;
15341536 .addMBB(BB)
15351537 .addReg(ShiftAmtReg2)
15361538 .addMBB(LoopBB);
1537 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1539
1540 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1541 if (HasRepeatedOperand)
1542 ShiftMI.addReg(ShiftReg);
1543
15381544 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
15391545 .addReg(ShiftAmtReg)
15401546 .addImm(1);
16701670 // Bit rotate operations.
16711671 let Uses = [SREG] in
16721672 {
1673 def ROLRd : FRdRr<0b0001,
1674 0b11,
1675 (outs GPR8:$rd),
1676 (ins GPR8:$src),
1677 "rol\t$rd",
1678 [(set i8:$rd, (AVRrol i8:$src)), (implicit SREG)]>;
1673 // 8-bit ROL is an alias of ADC Rd, Rd
16791674
16801675 def ROLWRd : Pseudo<(outs DREGS:$rd),
16811676 (ins DREGS:$src),
17671762 // -------------
17681763 // Clears all bits in a register.
17691764 def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>;
1765
1766 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>;
17701767
17711768 // SER Rd
17721769 // Alias for LDI Rd, 0xff
1515 ; CHECK-LABEL: test
1616
1717 ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
18 ; CHECK-NEXT: $r15 = ROLRd $r15, implicit-def $sreg, implicit killed $sreg
18 ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
1919
2020 $r15r14 = LSLWRd $r15r14, implicit-def $sreg
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