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UpdateTestChecks: Lanai triple support Summary: The assembly structure most resembles the SPARC pattern: ``` .globl f6 ! -- Begin function f6 .p2align 2 .type f6,@function f6: ! @f6 .cfi_startproc ! %bb.0: st %fp, [--%sp] <...> ld -8[%fp], %fp .Lfunc_end0: .size f6, .Lfunc_end0-f6 .cfi_endproc ! -- End function ``` Test being affected by upcoming patch, so regenerate it. Reviewers: RKSimon, jpienaar Reviewed By: RKSimon Subscribers: jyknight, fedor.sergeev, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62545 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362019 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev 1 year, 5 months ago
2 changed file(s) with 148 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s | FileCheck %s
12
23 ; Test custom lowering for 32-bit integer multiplication.
45 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
56 target triple = "lanai"
67
8 define i32 @f6(i32 inreg %a) #0 {
79 ; CHECK-LABEL: f6:
8 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
9 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
10 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
11 define i32 @f6(i32 inreg %a) #0 {
10 ; CHECK: ! %bb.0:
11 ; CHECK-NEXT: st %fp, [--%sp]
12 ; CHECK-NEXT: add %sp, 0x8, %fp
13 ; CHECK-NEXT: sub %sp, 0x8, %sp
14 ; CHECK-NEXT: sh %r6, 0x1, %r3
15 ; CHECK-NEXT: sh %r6, 0x3, %r9
16 ; CHECK-NEXT: sub %r9, %r3, %rv
17 ; CHECK-NEXT: ld -4[%fp], %pc ! return
18 ; CHECK-NEXT: add %fp, 0x0, %sp
19 ; CHECK-NEXT: ld -8[%fp], %fp
1220 %1 = mul nsw i32 %a, 6
1321 ret i32 %1
1422 }
1523
24 define i32 @f7(i32 inreg %a) #0 {
1625 ; CHECK-LABEL: f7:
17 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
18 ; CHECK: sub %r{{[0-9]+}}, %r6, %rv
19 define i32 @f7(i32 inreg %a) #0 {
26 ; CHECK: ! %bb.0:
27 ; CHECK-NEXT: st %fp, [--%sp]
28 ; CHECK-NEXT: add %sp, 0x8, %fp
29 ; CHECK-NEXT: sub %sp, 0x8, %sp
30 ; CHECK-NEXT: sh %r6, 0x3, %r3
31 ; CHECK-NEXT: sub %r3, %r6, %rv
32 ; CHECK-NEXT: ld -4[%fp], %pc ! return
33 ; CHECK-NEXT: add %fp, 0x0, %sp
34 ; CHECK-NEXT: ld -8[%fp], %fp
2035 %1 = mul nsw i32 %a, 7
2136 ret i32 %1
2237 }
2338
39 define i32 @f8(i32 inreg %a) #0 {
2440 ; CHECK-LABEL: f8:
25 ; CHECK: sh %r6, 0x3, %rv
26 define i32 @f8(i32 inreg %a) #0 {
41 ; CHECK: ! %bb.0:
42 ; CHECK-NEXT: st %fp, [--%sp]
43 ; CHECK-NEXT: add %sp, 0x8, %fp
44 ; CHECK-NEXT: sub %sp, 0x8, %sp
45 ; CHECK-NEXT: sh %r6, 0x3, %rv
46 ; CHECK-NEXT: ld -4[%fp], %pc ! return
47 ; CHECK-NEXT: add %fp, 0x0, %sp
48 ; CHECK-NEXT: ld -8[%fp], %fp
2749 %1 = shl nsw i32 %a, 3
2850 ret i32 %1
2951 }
3052
53 define i32 @f9(i32 inreg %a) #0 {
3154 ; CHECK-LABEL: f9:
32 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
33 ; CHECK: add %r{{[0-9]+}}, %r6, %rv
34 define i32 @f9(i32 inreg %a) #0 {
55 ; CHECK: ! %bb.0:
56 ; CHECK-NEXT: st %fp, [--%sp]
57 ; CHECK-NEXT: add %sp, 0x8, %fp
58 ; CHECK-NEXT: sub %sp, 0x8, %sp
59 ; CHECK-NEXT: sh %r6, 0x3, %r3
60 ; CHECK-NEXT: add %r3, %r6, %rv
61 ; CHECK-NEXT: ld -4[%fp], %pc ! return
62 ; CHECK-NEXT: add %fp, 0x0, %sp
63 ; CHECK-NEXT: ld -8[%fp], %fp
3564 %1 = mul nsw i32 %a, 9
3665 ret i32 %1
3766 }
3867
68 define i32 @f10(i32 inreg %a) #0 {
3969 ; CHECK-LABEL: f10:
40 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
41 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
42 ; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
43 define i32 @f10(i32 inreg %a) #0 {
70 ; CHECK: ! %bb.0:
71 ; CHECK-NEXT: st %fp, [--%sp]
72 ; CHECK-NEXT: add %sp, 0x8, %fp
73 ; CHECK-NEXT: sub %sp, 0x8, %sp
74 ; CHECK-NEXT: sh %r6, 0x1, %r3
75 ; CHECK-NEXT: sh %r6, 0x3, %r9
76 ; CHECK-NEXT: add %r9, %r3, %rv
77 ; CHECK-NEXT: ld -4[%fp], %pc ! return
78 ; CHECK-NEXT: add %fp, 0x0, %sp
79 ; CHECK-NEXT: ld -8[%fp], %fp
4480 %1 = mul nsw i32 %a, 10
4581 ret i32 %1
4682 }
4783
84 define i32 @f1280(i32 inreg %a) #0 {
4885 ; CHECK-LABEL: f1280:
49 ; CHECK: sh %r6, 0x8, %r{{[0-9]+}}
50 ; CHECK: sh %r6, 0xa, %r{{[0-9]+}}
51 ; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
52 define i32 @f1280(i32 inreg %a) #0 {
86 ; CHECK: ! %bb.0:
87 ; CHECK-NEXT: st %fp, [--%sp]
88 ; CHECK-NEXT: add %sp, 0x8, %fp
89 ; CHECK-NEXT: sub %sp, 0x8, %sp
90 ; CHECK-NEXT: sh %r6, 0x8, %r3
91 ; CHECK-NEXT: sh %r6, 0xa, %r9
92 ; CHECK-NEXT: add %r9, %r3, %rv
93 ; CHECK-NEXT: ld -4[%fp], %pc ! return
94 ; CHECK-NEXT: add %fp, 0x0, %sp
95 ; CHECK-NEXT: ld -8[%fp], %fp
5396 %1 = mul nsw i32 %a, 1280
5497 ret i32 %1
5598 }
5699
100 define i32 @fm6(i32 inreg %a) #0 {
57101 ; CHECK-LABEL: fm6:
58 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
59 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
60 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
61 define i32 @fm6(i32 inreg %a) #0 {
102 ; CHECK: ! %bb.0:
103 ; CHECK-NEXT: st %fp, [--%sp]
104 ; CHECK-NEXT: add %sp, 0x8, %fp
105 ; CHECK-NEXT: sub %sp, 0x8, %sp
106 ; CHECK-NEXT: sh %r6, 0x3, %r3
107 ; CHECK-NEXT: sh %r6, 0x1, %r9
108 ; CHECK-NEXT: sub %r9, %r3, %rv
109 ; CHECK-NEXT: ld -4[%fp], %pc ! return
110 ; CHECK-NEXT: add %fp, 0x0, %sp
111 ; CHECK-NEXT: ld -8[%fp], %fp
62112 %1 = mul nsw i32 %a, -6
63113 ret i32 %1
64114 }
65115
116 define i32 @fm7(i32 inreg %a) #0 {
66117 ; CHECK-LABEL: fm7:
67 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
68 ; CHECK: sub %r6, %r{{[0-9]+}}, %rv
69 define i32 @fm7(i32 inreg %a) #0 {
118 ; CHECK: ! %bb.0:
119 ; CHECK-NEXT: st %fp, [--%sp]
120 ; CHECK-NEXT: add %sp, 0x8, %fp
121 ; CHECK-NEXT: sub %sp, 0x8, %sp
122 ; CHECK-NEXT: sh %r6, 0x3, %r3
123 ; CHECK-NEXT: sub %r6, %r3, %rv
124 ; CHECK-NEXT: ld -4[%fp], %pc ! return
125 ; CHECK-NEXT: add %fp, 0x0, %sp
126 ; CHECK-NEXT: ld -8[%fp], %fp
70127 %1 = mul nsw i32 %a, -7
71128 ret i32 %1
72129 }
73130
131 define i32 @fm8(i32 inreg %a) #0 {
74132 ; CHECK-LABEL: fm8:
75 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
76 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
77 define i32 @fm8(i32 inreg %a) #0 {
133 ; CHECK: ! %bb.0:
134 ; CHECK-NEXT: st %fp, [--%sp]
135 ; CHECK-NEXT: add %sp, 0x8, %fp
136 ; CHECK-NEXT: sub %sp, 0x8, %sp
137 ; CHECK-NEXT: sh %r6, 0x3, %r3
138 ; CHECK-NEXT: sub %r0, %r3, %rv
139 ; CHECK-NEXT: ld -4[%fp], %pc ! return
140 ; CHECK-NEXT: add %fp, 0x0, %sp
141 ; CHECK-NEXT: ld -8[%fp], %fp
78142 %1 = mul nsw i32 %a, -8
79143 ret i32 %1
80144 }
81145
146 define i32 @fm9(i32 inreg %a) #0 {
82147 ; CHECK-LABEL: fm9:
83 ; CHECK: sub %r0, %r6, %r{{[0-9]+}}
84 ; CHECK: sh %r6, 0x3, %r9
85 ; CHECK: sub %r{{[0-9]+}}, %r9, %rv
86 define i32 @fm9(i32 inreg %a) #0 {
148 ; CHECK: ! %bb.0:
149 ; CHECK-NEXT: st %fp, [--%sp]
150 ; CHECK-NEXT: add %sp, 0x8, %fp
151 ; CHECK-NEXT: sub %sp, 0x8, %sp
152 ; CHECK-NEXT: sub %r0, %r6, %r3
153 ; CHECK-NEXT: sh %r6, 0x3, %r9
154 ; CHECK-NEXT: sub %r3, %r9, %rv
155 ; CHECK-NEXT: ld -4[%fp], %pc ! return
156 ; CHECK-NEXT: add %fp, 0x0, %sp
157 ; CHECK-NEXT: ld -8[%fp], %fp
87158 %1 = mul nsw i32 %a, -9
88159 ret i32 %1
89160 }
90161
162 define i32 @fm10(i32 inreg %a) #0 {
91163 ; CHECK-LABEL: fm10:
92 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
93 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
94 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
95 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
96 define i32 @fm10(i32 inreg %a) #0 {
164 ; CHECK: ! %bb.0:
165 ; CHECK-NEXT: st %fp, [--%sp]
166 ; CHECK-NEXT: add %sp, 0x8, %fp
167 ; CHECK-NEXT: sub %sp, 0x8, %sp
168 ; CHECK-NEXT: sh %r6, 0x1, %r3
169 ; CHECK-NEXT: sub %r0, %r3, %r3
170 ; CHECK-NEXT: sh %r6, 0x3, %r9
171 ; CHECK-NEXT: sub %r3, %r9, %rv
172 ; CHECK-NEXT: ld -4[%fp], %pc ! return
173 ; CHECK-NEXT: add %fp, 0x0, %sp
174 ; CHECK-NEXT: ld -8[%fp], %fp
97175 %1 = mul nsw i32 %a, -10
98176 ret i32 %1
99177 }
100178
179 define i32 @h1(i32 inreg %a) #0 {
101180 ; CHECK-LABEL: h1:
102 ; CHECK: __mulsi3
103 define i32 @h1(i32 inreg %a) #0 {
181 ; CHECK: ! %bb.0:
182 ; CHECK-NEXT: st %fp, [--%sp]
183 ; CHECK-NEXT: add %sp, 0x8, %fp
184 ; CHECK-NEXT: sub %sp, 0x8, %sp
185 ; CHECK-NEXT: mov 0xaaaa0000, %r3
186 ; CHECK-NEXT: add %pc, 0x10, %rca
187 ; CHECK-NEXT: st %rca, [--%sp]
188 ; CHECK-NEXT: bt __mulsi3
189 ; CHECK-NEXT: or %r3, 0xaaab, %r7
190 ; CHECK-NEXT: ld -4[%fp], %pc ! return
191 ; CHECK-NEXT: add %fp, 0x0, %sp
192 ; CHECK-NEXT: ld -8[%fp], %fp
104193 %1 = mul i32 %a, -1431655765
105194 ret i32 %1
106195 }
6565 ASM_FUNCTION_RISCV_RE = re.compile(
6666 r'^_?(?P[^:]+):[ \t]*#+[ \t]*@(?P=func)\n[^:]*?'
6767 r'(?P^##?[ \t]+[^:]+:.*?)\s*'
68 r'.Lfunc_end[0-9]+:\n',
69 flags=(re.M | re.S))
70
71 ASM_FUNCTION_LANAI_RE = re.compile(
72 r'^_?(?P[^:]+):[ \t]*!+[ \t]*@(?P=func)\n'
73 r'(?:[ \t]+.cfi_startproc\n)?' # drop optional cfi noise
74 r'(?P.*?)\s*'
6875 r'.Lfunc_end[0-9]+:\n',
6976 flags=(re.M | re.S))
7077
176183 return asm
177184
178185 def scrub_asm_riscv(asm, args):
186 # Scrub runs of whitespace out of the assembly, but leave the leading
187 # whitespace in place.
188 asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
189 # Expand the tabs used for indentation.
190 asm = string.expandtabs(asm, 2)
191 # Strip trailing whitespace.
192 asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
193 return asm
194
195 def scrub_asm_lanai(asm, args):
179196 # Scrub runs of whitespace out of the assembly, but leave the leading
180197 # whitespace in place.
181198 asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
265282 'powerpc64le': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
266283 'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
267284 'riscv64': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
285 'lanai': (scrub_asm_lanai, ASM_FUNCTION_LANAI_RE),
268286 'sparc': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
269287 'sparcv9': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
270288 's390x': (scrub_asm_systemz, ASM_FUNCTION_SYSTEMZ_RE),